Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1516286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241194

1

T1

40

T2

25

T3

328

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596363	1			T1	91		T2	50		T3	745
values[0x0]	563515	1			T1	108		T2	46		T3	818
values[0x1]	597602	1			T1	98		T2	48		T3	789

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1172154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585326

1

T1

84

T2

52

T3

776

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28712	1			T1	3		T3	38		T7	556
valid_sources[0x01]	27405	1			T1	2		T3	33		T7	643
valid_sources[0x02]	26869	1			T1	8		T2	5		T3	41
valid_sources[0x03]	27181	1			T1	3		T2	4		T3	39
valid_sources[0x04]	28075	1			T1	4		T2	2		T3	36
valid_sources[0x05]	27730	1			T1	5		T2	2		T3	34
valid_sources[0x06]	27760	1			T1	8		T2	5		T3	35
valid_sources[0x07]	26585	1			T1	2		T2	5		T3	36
valid_sources[0x08]	27002	1			T1	4		T2	5		T3	29
valid_sources[0x09]	27490	1			T1	13		T2	3		T3	36
valid_sources[0x0a]	25718	1			T1	3		T2	1		T3	34
valid_sources[0x0b]	27815	1			T1	4		T2	2		T3	41
valid_sources[0x0c]	27744	1			T1	5		T2	2		T3	33
valid_sources[0x0d]	28244	1			T1	3		T2	1		T3	41
valid_sources[0x0e]	27711	1			T1	5		T3	37		T7	613
valid_sources[0x0f]	27208	1			T1	4		T2	3		T3	34
valid_sources[0x10]	28191	1			T1	2		T2	2		T3	30
valid_sources[0x11]	27273	1			T1	2		T2	1		T3	45
valid_sources[0x12]	28376	1			T1	3		T2	2		T3	45
valid_sources[0x13]	27743	1			T1	7		T2	4		T3	40
valid_sources[0x14]	27940	1			T1	3		T2	6		T3	41
valid_sources[0x15]	27350	1			T1	3		T2	3		T3	36
valid_sources[0x16]	26712	1			T1	3		T2	1		T3	34
valid_sources[0x17]	28557	1			T2	3		T3	48		T7	678
valid_sources[0x18]	26628	1			T1	4		T2	3		T3	41
valid_sources[0x19]	27801	1			T1	7		T2	3		T3	35
valid_sources[0x1a]	27870	1			T1	2		T2	2		T3	42
valid_sources[0x1b]	27699	1			T1	5		T2	2		T3	37
valid_sources[0x1c]	26463	1			T1	5		T2	3		T3	38
valid_sources[0x1d]	26720	1			T1	2		T2	3		T3	29
valid_sources[0x1e]	28475	1			T1	1		T3	38		T7	665
valid_sources[0x1f]	27559	1			T1	5		T2	2		T3	27
valid_sources[0x20]	26648	1			T1	4		T2	3		T3	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25497

1

T1

3

T2

3

T3

30

values[0x0]

all_enables

biggest_size

190115

1

T1

35

T2

19

T3

272

values[0x1]

all_enables

biggest_size

25582

1

T1

2

T2

3

T3

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247792

1

T1

43

T2

18

T3

345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	606171	1			T1	99		T2	40		T3	819
values[0x0]	558463	1			T1	87		T2	35		T3	753
values[0x1]	603972	1			T1	87		T2	51		T3	897

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

601414

1

T1

103

T2

42

T3

834

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27495	1			T1	2		T2	1		T3	45
valid_sources[0x01]	27239	1			T1	5		T2	1		T3	37
valid_sources[0x02]	27794	1			T1	7		T2	1		T3	43
valid_sources[0x03]	27161	1			T1	4		T2	1		T3	35
valid_sources[0x04]	28814	1			T1	2		T2	2		T3	34
valid_sources[0x05]	27536	1			T1	3		T2	1		T3	31
valid_sources[0x06]	27193	1			T1	5		T2	5		T3	40
valid_sources[0x07]	27864	1			T1	2		T2	5		T3	44
valid_sources[0x08]	27314	1			T1	1		T3	34		T7	659
valid_sources[0x09]	27803	1			T1	4		T2	5		T3	33
valid_sources[0x0a]	27364	1			T1	5		T2	4		T3	32
valid_sources[0x0b]	27695	1			T1	3		T2	1		T3	31
valid_sources[0x0c]	27786	1			T1	3		T2	2		T3	38
valid_sources[0x0d]	27933	1			T1	12		T2	1		T3	23
valid_sources[0x0e]	27859	1			T1	4		T2	1		T3	38
valid_sources[0x0f]	28040	1			T1	7		T2	3		T3	49
valid_sources[0x10]	28084	1			T1	6		T2	1		T3	47
valid_sources[0x11]	27086	1			T1	2		T3	30		T7	622
valid_sources[0x12]	27510	1			T1	4		T3	21		T7	607
valid_sources[0x13]	27598	1			T1	3		T2	1		T3	44
valid_sources[0x14]	26787	1			T1	1		T2	1		T3	30
valid_sources[0x15]	27574	1			T1	2		T2	2		T3	50
valid_sources[0x16]	27559	1			T1	2		T2	1		T3	21
valid_sources[0x17]	27899	1			T1	5		T3	42		T7	609
valid_sources[0x18]	27226	1			T1	4		T3	31		T7	562
valid_sources[0x19]	28212	1			T1	4		T2	2		T3	33
valid_sources[0x1a]	27009	1			T1	2		T2	1		T3	43
valid_sources[0x1b]	27475	1			T1	5		T2	2		T3	36
valid_sources[0x1c]	27754	1			T1	5		T3	36		T7	621
valid_sources[0x1d]	27835	1			T1	6		T3	29		T7	644
valid_sources[0x1e]	28374	1			T1	3		T2	2		T3	42
valid_sources[0x1f]	27430	1			T1	5		T2	5		T3	41
valid_sources[0x20]	27637	1			T1	7		T2	1		T3	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26314

1

T1

10

T2

4

T3

27

values[0x0]

all_enables

biggest_size

195339

1

T1

30

T2

12

T3

285

values[0x1]

all_enables

biggest_size

26139

1

T1

3

T2

2

T3

33

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1527399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242338

1

T1

42

T2

14

T3

364

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	602036	1			T1	104		T2	39		T3	888
values[0x0]	566979	1			T1	94		T2	27		T3	866
values[0x1]	600722	1			T1	90		T2	37		T3	880

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1179662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

590075

1

T1

94

T2

37

T3

849

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27048	1			T1	1		T3	37		T7	517
valid_sources[0x01]	27678	1			T1	10		T3	44		T7	568
valid_sources[0x02]	28765	1			T1	6		T3	40		T7	606
valid_sources[0x03]	27149	1			T1	5		T2	6		T3	43
valid_sources[0x04]	28715	1			T1	3		T3	48		T7	673
valid_sources[0x05]	27043	1			T3	50		T7	630		T6	158
valid_sources[0x06]	27412	1			T1	7		T3	44		T7	606
valid_sources[0x07]	28065	1			T1	9		T3	51		T7	602
valid_sources[0x08]	27267	1			T1	1		T3	50		T7	577
valid_sources[0x09]	28730	1			T1	5		T3	41		T7	615
valid_sources[0x0a]	28305	1			T1	5		T3	35		T7	624
valid_sources[0x0b]	28178	1			T1	7		T3	41		T7	604
valid_sources[0x0c]	28017	1			T1	4		T3	32		T7	565
valid_sources[0x0d]	27456	1			T1	8		T3	37		T7	582
valid_sources[0x0e]	28329	1			T1	1		T3	36		T7	623
valid_sources[0x0f]	27370	1			T1	7		T3	34		T7	654
valid_sources[0x10]	27410	1			T1	1		T3	43		T7	592
valid_sources[0x11]	27458	1			T1	3		T3	38		T7	776
valid_sources[0x12]	27588	1			T3	32		T7	607		T6	159
valid_sources[0x13]	27228	1			T1	4		T3	44		T7	553
valid_sources[0x14]	27454	1			T1	3		T3	38		T7	674
valid_sources[0x15]	27244	1			T1	14		T3	36		T7	690
valid_sources[0x16]	27492	1			T1	4		T3	36		T7	617
valid_sources[0x17]	27540	1			T1	3		T3	39		T7	595
valid_sources[0x18]	27971	1			T1	5		T3	42		T7	516
valid_sources[0x19]	28028	1			T1	2		T3	43		T7	563
valid_sources[0x1a]	26825	1			T1	4		T3	47		T7	519
valid_sources[0x1b]	27734	1			T1	7		T3	49		T7	659
valid_sources[0x1c]	27325	1			T1	5		T2	1		T3	45
valid_sources[0x1d]	26855	1			T1	7		T3	35		T7	686
valid_sources[0x1e]	27597	1			T1	7		T3	36		T7	586
valid_sources[0x1f]	27681	1			T1	3		T2	28		T3	57
valid_sources[0x20]	27126	1			T1	8		T3	43		T7	521

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25680

1

T1

4

T2

4

T3

32

values[0x0]

all_enables

biggest_size

191020

1

T1

30

T2

9

T3

299

values[0x1]

all_enables

biggest_size

25638

1

T1

8

T2

1

T3

33