Cond Coverage for Module :
tlul_fifo_sync
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_fifo_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_27.fifo_h
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.fifo_h
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[0].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[1].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[2].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_27.gen_dfifo[3].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[2].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_28.gen_host_fifo[2].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[2].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_29.gen_host_fifo[2].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_30.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_30.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[2].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_30.gen_host_fifo[2].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[2].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_31.gen_host_fifo[2].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.fifo_h
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.fifo_h
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[0].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[1].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[2].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[3].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[4].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[5].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[6].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[7].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[8].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[9].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[10].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[11].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[12].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[13].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[14].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[15].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[16].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[17].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[18].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[19].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[20].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[21].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[22].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_32.gen_dfifo[23].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T6 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T2,T7,T6 |
Cond Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_34.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_34.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_34.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_34.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_36.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_36.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_36.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_36.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_36.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_36.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_38.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_38.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_40.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_42.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T6 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T2,T7,T6 |
Cond Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T6 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T7,T6 |
Cond Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T3,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T7,T6 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T6 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T2,T7,T6 |
Cond Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T7,T6 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T2,T7,T6 |
Cond Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T7 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T2,T3,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T2,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T7 |
Cond Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[1].u_hostfifo
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_sm1_56.gen_host_fifo[1].u_hostfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.fifo_h
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.fifo_h
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[0].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[0].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[1].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[1].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[2].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[2].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[3].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[3].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[4].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[4].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[5].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[6].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[7].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[8].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[9].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[10].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[11].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[12].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[12].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[13].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[13].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[14].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[14].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[15].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[15].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[16].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[16].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[17].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[17].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[18].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[18].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[19].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[20].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T7,T6 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[21].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T7,T6 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[22].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T7 |
| 0 |
Covered |
T1,T2,T3 |
Cond Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 66
SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
LINE 66
SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_s1n_57.gen_dfifo[23].fifo_d
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
66 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 66 ((tl_d_i.d_opcode == AccessAckData)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T3 |
