Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7926248	0	0
GntImpliesValid_A	2147483647	7926248	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7926248	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	483825420	0	0
ReadyAndValidImplyGrant_A	2147483647	7926248	0	0
ReqAndReadyImplyGrant_A	2147483647	7926248	0	0
ReqImpliesValid_A	2147483647	35279324	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51625	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7926248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189672	188808	0	0
T2	51336	50328	0	0
T3	7514304	7514208	0	0
T6	5797488	5784888	0	0
T7	5244384	5230248	0	0
T8	975840	974496	0	0
T9	1103616	1102800	0	0
T10	7446408	7446384	0	0
T11	255456	255144	0	0
T12	1973304	1971816	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189672	188808	0	0
T2	51336	50328	0	0
T3	7514304	7514208	0	0
T6	5797488	5784888	0	0
T7	5244384	5230248	0	0
T8	975840	974496	0	0
T9	1103616	1102800	0	0
T10	7446408	7446384	0	0
T11	255456	255144	0	0
T12	1973304	1971816	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189672	188808	0	0
T2	51336	50328	0	0
T3	7514304	7514208	0	0
T6	5797488	5784888	0	0
T7	5244384	5230248	0	0
T8	975840	974496	0	0
T9	1103616	1102800	0	0
T10	7446408	7446384	0	0
T11	255456	255144	0	0
T12	1973304	1971816	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	483825420	0	0
T1	158060	9415	0	0
T2	51336	667	0	0
T3	7514304	289231	0	0
T6	5797488	338733	0	0
T7	5244384	131868	0	0
T8	975840	53464	0	0
T9	1103616	65930	0	0
T10	7446408	2437819	0	0
T11	255456	7158	0	0
T12	1973304	106550	0	0
T13	8664	225	0	0
T14	0	894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35279324	0	0
T1	39515	5830	0	0
T2	51336	411	0	0
T3	7514304	17961	0	0
T6	5797488	57031	0	0
T7	5244384	137867	0	0
T8	975840	3376	0	0
T9	1103616	7766	0	0
T10	7446408	484817	0	0
T11	255456	7552	0	0
T12	1973304	7614	0	0
T13	41154	240	0	0
T14	0	394	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51625	0	21600
T6	483124	4	0	2
T7	437032	2006	0	2
T8	81320	0	0	2
T9	91968	1	0	2
T10	620534	0	0	2
T11	21288	22	0	2
T12	164442	0	0	2
T13	4332	0	0	2
T14	15746	1	0	2
T15	0	1860	0	0
T16	0	432	0	0
T17	0	9	0	0
T18	0	6	0	0
T19	0	1	0	0
T20	0	22	0	0
T21	0	5	0	0
T22	0	36	0	0
T23	329388	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	189672	188808	0	0
T2	51336	50328	0	0
T3	7514304	7514208	0	0
T6	5797488	5784888	0	0
T7	5244384	5230248	0	0
T8	975840	974496	0	0
T9	1103616	1102800	0	0
T10	7446408	7446384	0	0
T11	255456	255144	0	0
T12	1973304	1971816	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7926248	0	0
T1	39515	858	0	0
T2	51336	373	0	0
T3	7514304	7455	0	0
T6	5797488	22236	0	0
T7	5244384	103605	0	0
T8	975840	1962	0	0
T9	1103616	3473	0	0
T10	7446408	7828	0	0
T11	255456	6549	0	0
T12	1973304	4351	0	0
T13	41154	203	0	0
T14	0	268	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	886553	0	0
GntImpliesValid_A	444360173	886553	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	886553	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	12789870	0	0
ReadyAndValidImplyGrant_A	444360173	886553	0	0
ReqAndReadyImplyGrant_A	444360173	886553	0	0
ReqImpliesValid_A	444360173	2638884	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	886553	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	12789870	0	0
T1	7903	494	0	0
T2	2139	36	0	0
T3	313096	2572	0	0
T6	241562	15994	0	0
T7	218516	8146	0	0
T8	40660	1812	0	0
T9	45984	2985	0	0
T10	310267	253999	0	0
T11	10644	505	0	0
T12	82221	3653	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	2638884	0	0
T1	7903	112	0	0
T2	2139	55	0	0
T3	313096	871	0	0
T6	241562	3539	0	0
T7	218516	12763	0	0
T8	40660	244	0	0
T9	45984	584	0	0
T10	310267	28954	0	0
T11	10644	916	0	0
T12	82221	571	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	886553	0	0
T1	7903	64	0	0
T2	2139	45	0	0
T3	313096	627	0	0
T6	241562	2157	0	0
T7	218516	10452	0	0
T8	40660	231	0	0
T9	45984	409	0	0
T10	310267	850	0	0
T11	10644	710	0	0
T12	82221	502	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	883505	0	0
GntImpliesValid_A	444360173	883505	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	883505	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	12794123	0	0
ReadyAndValidImplyGrant_A	444360173	883505	0	0
ReqAndReadyImplyGrant_A	444360173	883505	0	0
ReqImpliesValid_A	444360173	2550721	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	883505	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	12794123	0	0
T1	7903	529	0	0
T2	2139	29	0	0
T3	313096	2482	0	0
T6	241562	14965	0	0
T7	218516	8832	0	0
T8	40660	1617	0	0
T9	45984	2889	0	0
T10	310267	273220	0	0
T11	10644	518	0	0
T12	82221	3874	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	2550721	0	0
T1	7903	113	0	0
T2	2139	52	0	0
T3	313096	853	0	0
T6	241562	3023	0	0
T7	218516	16529	0	0
T8	40660	211	0	0
T9	45984	575	0	0
T10	310267	37350	0	0
T11	10644	833	0	0
T12	82221	576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	883505	0	0
T1	7903	73	0	0
T2	2139	40	0	0
T3	313096	588	0	0
T6	241562	2065	0	0
T7	218516	12678	0	0
T8	40660	202	0	0
T9	45984	378	0	0
T10	310267	893	0	0
T11	10644	675	0	0
T12	82221	500	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	222543	0	0
GntImpliesValid_A	444360173	222543	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	222543	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3154496	0	0
ReadyAndValidImplyGrant_A	444360173	222543	0	0
ReqAndReadyImplyGrant_A	444360173	222543	0	0
ReqImpliesValid_A	444360173	594217	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	222543	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3154496	0	0
T1	7903	1	0	0
T2	2139	24	0	0
T3	313096	1	0	0
T6	241562	8605	0	0
T7	218516	1829	0	0
T8	40660	438	0	0
T9	45984	687	0	0
T10	310267	64930	0	0
T11	10644	179	0	0
T12	82221	944	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	594217	0	0
T2	2139	29	0	0
T3	313096	0	0	0
T6	241562	3549	0	0
T7	218516	2956	0	0
T8	40660	83	0	0
T9	45984	107	0	0
T10	310267	1051	0	0
T11	10644	192	0	0
T12	82221	127	0	0
T13	2166	11	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	222543	0	0
T2	2139	26	0	0
T3	313096	0	0	0
T6	241562	1333	0	0
T7	218516	2390	0	0
T8	40660	69	0	0
T9	45984	92	0	0
T10	310267	192	0	0
T11	10644	185	0	0
T12	82221	118	0	0
T13	2166	10	0	0
T14	0	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	208191	0	0
GntImpliesValid_A	444360173	208191	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	208191	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3219424	0	0
ReadyAndValidImplyGrant_A	444360173	208191	0	0
ReqAndReadyImplyGrant_A	444360173	208191	0	0
ReqImpliesValid_A	444360173	535075	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	208191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3219424	0	0
T1	7903	1	0	0
T2	2139	8	0	0
T3	313096	1720	0	0
T6	241562	2728	0	0
T7	218516	2410	0	0
T8	40660	238	0	0
T9	45984	519	0	0
T10	310267	75815	0	0
T11	10644	175	0	0
T12	82221	763	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	535075	0	0
T2	2139	7	0	0
T3	313096	1112	0	0
T6	241562	463	0	0
T7	218516	3419	0	0
T8	40660	43	0	0
T9	45984	79	0	0
T10	310267	6034	0	0
T11	10644	210	0	0
T12	82221	103	0	0
T13	2166	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208191	0	0
T2	2139	7	0	0
T3	313096	516	0	0
T6	241562	352	0	0
T7	218516	2912	0	0
T8	40660	40	0	0
T9	45984	70	0	0
T10	310267	232	0	0
T11	10644	192	0	0
T12	82221	103	0	0
T13	2166	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	213055	0	0
GntImpliesValid_A	444360173	213055	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	213055	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	5060584	0	0
ReadyAndValidImplyGrant_A	444360173	213055	0	0
ReqAndReadyImplyGrant_A	444360173	213055	0	0
ReqImpliesValid_A	444360173	1066690	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	213055	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	5060584	0	0
T2	2139	44	0	0
T3	313096	6487	0	0
T6	241562	2031	0	0
T7	218516	19959	0	0
T8	40660	1312	0	0
T9	45984	1681	0	0
T10	310267	41976	0	0
T11	10644	659	0	0
T12	82221	2704	0	0
T13	2166	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	1066690	0	0
T2	2139	6	0	0
T3	313096	2735	0	0
T6	241562	351	0	0
T7	218516	3508	0	0
T8	40660	62	0	0
T9	45984	224	0	0
T10	310267	2044	0	0
T11	10644	261	0	0
T12	82221	175	0	0
T13	2166	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213055	0	0
T2	2139	6	0	0
T3	313096	526	0	0
T6	241562	332	0	0
T7	218516	1976	0	0
T8	40660	54	0	0
T9	45984	95	0	0
T10	310267	197	0	0
T11	10644	184	0	0
T12	82221	116	0	0
T13	2166	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T7,T6
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T6
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T6

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	216849	0	0
GntImpliesValid_A	444360173	216849	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	216849	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	5818173	0	0
ReadyAndValidImplyGrant_A	444360173	216849	0	0
ReqAndReadyImplyGrant_A	444360173	216849	0	0
ReqImpliesValid_A	444360173	1163097	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	216849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	5818173	0	0
T2	2139	46	0	0
T3	313096	0	0	0
T6	241562	2648	0	0
T7	218516	29199	0	0
T8	40660	1107	0	0
T9	45984	605	0	0
T10	310267	18694	0	0
T11	10644	1326	0	0
T12	82221	1719	0	0
T13	2166	58	0	0
T14	0	147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	1163097	0	0
T2	2139	15	0	0
T3	313096	0	0	0
T6	241562	391	0	0
T7	218516	20266	0	0
T8	40660	48	0	0
T9	45984	111	0	0
T10	310267	1039	0	0
T11	10644	367	0	0
T12	82221	129	0	0
T13	2166	24	0	0
T14	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	216849	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	330	0	0
T7	218516	3991	0	0
T8	40660	48	0	0
T9	45984	93	0	0
T10	310267	226	0	0
T11	10644	174	0	0
T12	82221	129	0	0
T13	2166	12	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T7,T6
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T9
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T6
1	0	Not Covered
1	1	Covered	T7,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T6

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	208810	0	0
GntImpliesValid_A	444360173	208810	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	208810	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	5442190	0	0
ReadyAndValidImplyGrant_A	444360173	208810	0	0
ReqAndReadyImplyGrant_A	444360173	208810	0	0
ReqImpliesValid_A	444360173	996324	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	208810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	5442190	0	0
T2	2139	296	0	0
T3	313096	0	0	0
T6	241562	2545	0	0
T7	218516	12508	0	0
T8	40660	2895	0	0
T9	45984	2511	0	0
T10	310267	35977	0	0
T11	10644	685	0	0
T12	82221	2538	0	0
T13	2166	83	0	0
T14	0	524	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	996324	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	396	0	0
T7	218516	2648	0	0
T8	40660	50	0	0
T9	45984	288	0	0
T10	310267	1353	0	0
T11	10644	278	0	0
T12	82221	224	0	0
T13	2166	20	0	0
T14	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	208810	0	0
T2	2139	12	0	0
T3	313096	0	0	0
T6	241562	332	0	0
T7	218516	1886	0	0
T8	40660	50	0	0
T9	45984	107	0	0
T10	310267	230	0	0
T11	10644	183	0	0
T12	82221	146	0	0
T13	2166	13	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T7,T6
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T6
1	0	Not Covered
1	1	Covered	T7,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T6

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	217688	0	0
GntImpliesValid_A	444360173	217688	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	217688	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	5644485	0	0
ReadyAndValidImplyGrant_A	444360173	217688	0	0
ReqAndReadyImplyGrant_A	444360173	217688	0	0
ReqImpliesValid_A	444360173	1262735	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	217688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	5644485	0	0
T2	2139	33	0	0
T3	313096	0	0	0
T6	241562	2447	0	0
T7	218516	15231	0	0
T8	40660	959	0	0
T9	45984	2650	0	0
T10	310267	104574	0	0
T11	10644	659	0	0
T12	82221	3707	0	0
T13	2166	32	0	0
T14	0	223	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	1262735	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	672	0	0
T7	218516	2810	0	0
T8	40660	84	0	0
T9	45984	321	0	0
T10	310267	8826	0	0
T11	10644	284	0	0
T12	82221	134	0	0
T13	2166	11	0	0
T14	0	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217688	0	0
T2	2139	6	0	0
T3	313096	0	0	0
T6	241562	432	0	0
T7	218516	1946	0	0
T8	40660	52	0	0
T9	45984	94	0	0
T10	310267	222	0	0
T11	10644	207	0	0
T12	82221	132	0	0
T13	2166	7	0	0
T14	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	211657	0	0
GntImpliesValid_A	444360173	211657	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	211657	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3208171	0	0
ReadyAndValidImplyGrant_A	444360173	211657	0	0
ReqAndReadyImplyGrant_A	444360173	211657	0	0
ReqImpliesValid_A	444360173	560479	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	211657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3208171	0	0
T1	7903	1	0	0
T2	2139	8	0	0
T3	313096	1	0	0
T6	241562	2761	0	0
T7	218516	2467	0	0
T8	40660	510	0	0
T9	45984	602	0	0
T10	310267	70130	0	0
T11	10644	195	0	0
T12	82221	1052	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	560479	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	398	0	0
T7	218516	3452	0	0
T8	40660	59	0	0
T9	45984	114	0	0
T10	310267	3134	0	0
T11	10644	222	0	0
T12	82221	136	0	0
T13	2166	6	0	0
T14	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	211657	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	344	0	0
T7	218516	2957	0	0
T8	40660	59	0	0
T9	45984	82	0	0
T10	310267	194	0	0
T11	10644	208	0	0
T12	82221	131	0	0
T13	2166	6	0	0
T14	0	27	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T10
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T6,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	205563	0	0
GntImpliesValid_A	444360173	205563	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	205563	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3145954	0	0
ReadyAndValidImplyGrant_A	444360173	205563	0	0
ReqAndReadyImplyGrant_A	444360173	205563	0	0
ReqImpliesValid_A	444360173	523696	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	205563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3145954	0	0
T1	7903	1	0	0
T2	2139	14	0	0
T3	313096	1	0	0
T6	241562	3105	0	0
T7	218516	2404	0	0
T8	40660	381	0	0
T9	45984	685	0	0
T10	310267	70273	0	0
T11	10644	175	0	0
T12	82221	881	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	523696	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	539	0	0
T7	218516	3477	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	2645	0	0
T11	10644	186	0	0
T12	82221	119	0	0
T13	2166	9	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	205563	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	415	0	0
T7	218516	2938	0	0
T8	40660	57	0	0
T9	45984	84	0	0
T10	310267	207	0	0
T11	10644	180	0	0
T12	82221	119	0	0
T13	2166	8	0	0
T14	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	214440	0	0
GntImpliesValid_A	444360173	214440	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	214440	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3133813	0	0
ReadyAndValidImplyGrant_A	444360173	214440	0	0
ReqAndReadyImplyGrant_A	444360173	214440	0	0
ReqImpliesValid_A	444360173	526136	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	214440	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3133813	0	0
T1	7903	1	0	0
T2	2139	14	0	0
T3	313096	1724	0	0
T6	241562	2499	0	0
T7	218516	2818	0	0
T8	40660	460	0	0
T9	45984	592	0	0
T10	310267	69995	0	0
T11	10644	166	0	0
T12	82221	1141	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	526136	0	0
T2	2139	13	0	0
T3	313096	1101	0	0
T6	241562	361	0	0
T7	218516	3871	0	0
T8	40660	62	0	0
T9	45984	106	0	0
T10	310267	3980	0	0
T11	10644	183	0	0
T12	82221	167	0	0
T13	2166	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214440	0	0
T2	2139	13	0	0
T3	313096	501	0	0
T6	241562	323	0	0
T7	218516	3342	0	0
T8	40660	60	0	0
T9	45984	88	0	0
T10	310267	212	0	0
T11	10644	174	0	0
T12	82221	141	0	0
T13	2166	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	214985	0	0
GntImpliesValid_A	444360173	214985	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	214985	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3147020	0	0
ReadyAndValidImplyGrant_A	444360173	214985	0	0
ReqAndReadyImplyGrant_A	444360173	214985	0	0
ReqImpliesValid_A	444360173	578116	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	214985	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3147020	0	0
T1	7903	1	0	0
T2	2139	15	0	0
T3	313096	1	0	0
T6	241562	2153	0	0
T7	218516	2118	0	0
T8	40660	537	0	0
T9	45984	723	0	0
T10	310267	71795	0	0
T11	10644	186	0	0
T12	82221	761	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	578116	0	0
T2	2139	18	0	0
T3	313096	0	0	0
T6	241562	357	0	0
T7	218516	2647	0	0
T8	40660	67	0	0
T9	45984	120	0	0
T10	310267	5091	0	0
T11	10644	217	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	214985	0	0
T2	2139	16	0	0
T3	313096	0	0	0
T6	241562	306	0	0
T7	218516	2380	0	0
T8	40660	67	0	0
T9	45984	88	0	0
T10	310267	222	0	0
T11	10644	201	0	0
T12	82221	103	0	0
T13	2166	10	0	0
T14	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	226025	0	0
GntImpliesValid_A	444360173	226025	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	226025	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3180067	0	0
ReadyAndValidImplyGrant_A	444360173	226025	0	0
ReqAndReadyImplyGrant_A	444360173	226025	0	0
ReqImpliesValid_A	444360173	582477	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	226025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3180067	0	0
T1	7903	1	0	0
T2	2139	8	0	0
T3	313096	3466	0	0
T6	241562	5457	0	0
T7	218516	2264	0	0
T8	40660	354	0	0
T9	45984	755	0	0
T10	310267	68857	0	0
T11	10644	166	0	0
T12	82221	944	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	582477	0	0
T2	2139	7	0	0
T3	313096	2352	0	0
T6	241562	1504	0	0
T7	218516	2572	0	0
T8	40660	44	0	0
T9	45984	119	0	0
T10	310267	2503	0	0
T11	10644	191	0	0
T12	82221	150	0	0
T13	2166	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226025	0	0
T2	2139	7	0	0
T3	313096	1014	0	0
T6	241562	801	0	0
T7	218516	2416	0	0
T8	40660	44	0	0
T9	45984	103	0	0
T10	310267	218	0	0
T11	10644	178	0	0
T12	82221	135	0	0
T13	2166	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	218618	0	0
GntImpliesValid_A	444360173	218618	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	218618	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3204626	0	0
ReadyAndValidImplyGrant_A	444360173	218618	0	0
ReqAndReadyImplyGrant_A	444360173	218618	0	0
ReqImpliesValid_A	444360173	539401	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	218618	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3204626	0	0
T1	7903	1	0	0
T2	2139	6	0	0
T3	313096	3640	0	0
T6	241562	10926	0	0
T7	218516	1803	0	0
T8	40660	398	0	0
T9	45984	652	0	0
T10	310267	79904	0	0
T11	10644	168	0	0
T12	82221	857	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	539401	0	0
T2	2139	5	0	0
T3	313096	2292	0	0
T6	241562	5811	0	0
T7	218516	1872	0	0
T8	40660	53	0	0
T9	45984	107	0	0
T10	310267	4706	0	0
T11	10644	183	0	0
T12	82221	114	0	0
T13	2166	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218618	0	0
T2	2139	5	0	0
T3	313096	1076	0	0
T6	241562	1764	0	0
T7	218516	1835	0	0
T8	40660	53	0	0
T9	45984	87	0	0
T10	310267	223	0	0
T11	10644	175	0	0
T12	82221	114	0	0
T13	2166	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	224626	0	0
GntImpliesValid_A	444360173	224626	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	224626	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3283333	0	0
ReadyAndValidImplyGrant_A	444360173	224626	0	0
ReqAndReadyImplyGrant_A	444360173	224626	0	0
ReqImpliesValid_A	444360173	605893	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	224626	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3283333	0	0
T1	7903	1	0	0
T2	2139	13	0	0
T3	313096	1	0	0
T6	241562	6687	0	0
T7	218516	1836	0	0
T8	40660	448	0	0
T9	45984	577	0	0
T10	310267	76220	0	0
T11	10644	201	0	0
T12	82221	812	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	605893	0	0
T2	2139	14	0	0
T3	313096	0	0	0
T6	241562	2334	0	0
T7	218516	3773	0	0
T8	40660	59	0	0
T9	45984	97	0	0
T10	310267	5082	0	0
T11	10644	226	0	0
T12	82221	117	0	0
T13	2166	18	0	0
T14	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	224626	0	0
T2	2139	13	0	0
T3	313096	0	0	0
T6	241562	1174	0	0
T7	218516	2802	0	0
T8	40660	59	0	0
T9	45984	85	0	0
T10	310267	223	0	0
T11	10644	213	0	0
T12	82221	109	0	0
T13	2166	17	0	0
T14	0	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	217839	0	0
GntImpliesValid_A	444360173	217839	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	217839	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3185876	0	0
ReadyAndValidImplyGrant_A	444360173	217839	0	0
ReqAndReadyImplyGrant_A	444360173	217839	0	0
ReqImpliesValid_A	444360173	544448	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	217839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3185876	0	0
T1	7903	1	0	0
T2	2139	9	0	0
T3	313096	1437	0	0
T6	241562	5214	0	0
T7	218516	2736	0	0
T8	40660	564	0	0
T9	45984	676	0	0
T10	310267	74301	0	0
T11	10644	156	0	0
T12	82221	989	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	544448	0	0
T2	2139	8	0	0
T3	313096	1126	0	0
T6	241562	1518	0	0
T7	218516	4833	0	0
T8	40660	70	0	0
T9	45984	156	0	0
T10	310267	3807	0	0
T11	10644	187	0	0
T12	82221	141	0	0
T13	2166	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	217839	0	0
T2	2139	8	0	0
T3	313096	458	0	0
T6	241562	855	0	0
T7	218516	3782	0	0
T8	40660	70	0	0
T9	45984	94	0	0
T10	310267	225	0	0
T11	10644	171	0	0
T12	82221	127	0	0
T13	2166	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	241457	0	0
GntImpliesValid_A	444360173	241457	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	241457	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3244077	0	0
ReadyAndValidImplyGrant_A	444360173	241457	0	0
ReqAndReadyImplyGrant_A	444360173	241457	0	0
ReqImpliesValid_A	444360173	605156	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	241457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3244077	0	0
T1	7903	1	0	0
T2	2139	8	0	0
T3	313096	1	0	0
T6	241562	4314	0	0
T7	218516	2200	0	0
T8	40660	453	0	0
T9	45984	1216	0	0
T10	310267	64985	0	0
T11	10644	196	0	0
T12	82221	885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	605156	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	2686	0	0
T7	218516	3187	0	0
T8	40660	74	0	0
T9	45984	261	0	0
T10	310267	4110	0	0
T11	10644	219	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	241457	0	0
T2	2139	8	0	0
T3	313096	0	0	0
T6	241562	892	0	0
T7	218516	2691	0	0
T8	40660	63	0	0
T9	45984	166	0	0
T10	310267	220	0	0
T11	10644	207	0	0
T12	82221	114	0	0
T13	2166	16	0	0
T14	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T9
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	228944	0	0
GntImpliesValid_A	444360173	228944	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	228944	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3184901	0	0
ReadyAndValidImplyGrant_A	444360173	228944	0	0
ReqAndReadyImplyGrant_A	444360173	228944	0	0
ReqImpliesValid_A	444360173	567811	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	228944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3184901	0	0
T1	7903	1	0	0
T2	2139	10	0	0
T3	313096	1	0	0
T6	241562	2492	0	0
T7	218516	2172	0	0
T8	40660	455	0	0
T9	45984	793	0	0
T10	310267	60410	0	0
T11	10644	172	0	0
T12	82221	827	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	567811	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	417	0	0
T7	218516	4477	0	0
T8	40660	58	0	0
T9	45984	111	0	0
T10	310267	4993	0	0
T11	10644	199	0	0
T12	82221	115	0	0
T13	2166	12	0	0
T14	0	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	228944	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	334	0	0
T7	218516	3322	0	0
T8	40660	58	0	0
T9	45984	103	0	0
T10	310267	215	0	0
T11	10644	185	0	0
T12	82221	115	0	0
T13	2166	11	0	0
T14	0	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	213721	0	0
GntImpliesValid_A	444360173	213721	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	213721	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3174101	0	0
ReadyAndValidImplyGrant_A	444360173	213721	0	0
ReqAndReadyImplyGrant_A	444360173	213721	0	0
ReqImpliesValid_A	444360173	531677	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	213721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3174101	0	0
T1	7903	1	0	0
T2	2139	14	0	0
T3	313096	1360	0	0
T6	241562	3050	0	0
T7	218516	2662	0	0
T8	40660	353	0	0
T9	45984	645	0	0
T10	310267	58763	0	0
T11	10644	167	0	0
T12	82221	827	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	531677	0	0
T2	2139	17	0	0
T3	313096	1037	0	0
T6	241562	520	0	0
T7	218516	3001	0	0
T8	40660	52	0	0
T9	45984	119	0	0
T10	310267	2323	0	0
T11	10644	190	0	0
T12	82221	112	0	0
T13	2166	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	213721	0	0
T2	2139	15	0	0
T3	313096	443	0	0
T6	241562	386	0	0
T7	218516	2829	0	0
T8	40660	52	0	0
T9	45984	87	0	0
T10	310267	210	0	0
T11	10644	178	0	0
T12	82221	112	0	0
T13	2166	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T2,T7,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T6
1	1	Covered	T2,T7,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	218481	0	0
GntImpliesValid_A	444360173	218481	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	218481	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3189672	0	0
ReadyAndValidImplyGrant_A	444360173	218481	0	0
ReqAndReadyImplyGrant_A	444360173	218481	0	0
ReqImpliesValid_A	444360173	545357	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	218481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3189672	0	0
T1	7903	1	0	0
T2	2139	9	0	0
T3	313096	1	0	0
T6	241562	6360	0	0
T7	218516	2191	0	0
T8	40660	538	0	0
T9	45984	541	0	0
T10	310267	79908	0	0
T11	10644	149	0	0
T12	82221	770	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	545357	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	1776	0	0
T7	218516	3714	0	0
T8	40660	70	0	0
T9	45984	86	0	0
T10	310267	3789	0	0
T11	10644	168	0	0
T12	82221	120	0	0
T13	2166	12	0	0
T14	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	218481	0	0
T2	2139	9	0	0
T3	313096	0	0	0
T6	241562	907	0	0
T7	218516	2950	0	0
T8	40660	64	0	0
T9	45984	82	0	0
T10	310267	233	0	0
T11	10644	158	0	0
T12	82221	120	0	0
T13	2166	11	0	0
T14	0	27	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T6
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T3,T7,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	223807	0	0
GntImpliesValid_A	444360173	223807	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	223807	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3141846	0	0
ReadyAndValidImplyGrant_A	444360173	223807	0	0
ReqAndReadyImplyGrant_A	444360173	223807	0	0
ReqImpliesValid_A	444360173	562596	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	223807	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3141846	0	0
T1	7903	1	0	0
T2	2139	10	0	0
T3	313096	1387	0	0
T6	241562	6320	0	0
T7	218516	2604	0	0
T8	40660	420	0	0
T9	45984	682	0	0
T10	310267	72930	0	0
T11	10644	183	0	0
T12	82221	1176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	562596	0	0
T2	2139	9	0	0
T3	313096	1076	0	0
T6	241562	1890	0	0
T7	218516	3281	0	0
T8	40660	59	0	0
T9	45984	143	0	0
T10	310267	2603	0	0
T11	10644	212	0	0
T12	82221	158	0	0
T13	2166	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	223807	0	0
T2	2139	9	0	0
T3	313096	452	0	0
T6	241562	904	0	0
T7	218516	2940	0	0
T8	40660	59	0	0
T9	45984	96	0	0
T10	310267	228	0	0
T11	10644	197	0	0
T12	82221	143	0	0
T13	2166	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	226871	0	0
GntImpliesValid_A	444360173	226871	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	226871	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	3222932	0	0
ReadyAndValidImplyGrant_A	444360173	226871	0	0
ReqAndReadyImplyGrant_A	444360173	226871	0	0
ReqImpliesValid_A	444360173	591797	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	0	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	226871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	3222932	0	0
T1	7903	1419	0	0
T2	2139	11	0	0
T3	313096	1	0	0
T6	241562	2766	0	0
T7	218516	3473	0	0
T8	40660	360	0	0
T9	45984	740	0	0
T10	310267	68239	0	0
T11	10644	170	0	0
T12	82221	832	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	591797	0	0
T1	7903	4990	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	452	0	0
T7	218516	4710	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	4151	0	0
T11	10644	197	0	0
T12	82221	115	0	0
T13	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	226871	0	0
T1	7903	585	0	0
T2	2139	10	0	0
T3	313096	0	0	0
T6	241562	371	0	0
T7	218516	4089	0	0
T8	40660	51	0	0
T9	45984	96	0	0
T10	310267	203	0	0
T11	10644	183	0	0
T12	82221	107	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	884750	0	0
GntImpliesValid_A	444360173	884750	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	884750	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	12283783	0	0
ReadyAndValidImplyGrant_A	444360173	884750	0	0
ReqAndReadyImplyGrant_A	444360173	884750	0	0
ReqImpliesValid_A	444360173	2404458	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	19679	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	884750	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	12283783	0	0
T1	7903	449	0	0
T2	2139	1	0	0
T3	313096	2245	0	0
T6	241562	18724	0	0
T7	218516	5	0	0
T8	40660	1255	0	0
T9	45984	2482	0	0
T10	310267	302574	0	0
T11	10644	1	0	0
T12	82221	3351	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	2404458	0	0
T1	7903	88	0	0
T2	2139	33	0	0
T3	313096	864	0	0
T6	241562	6807	0	0
T7	218516	11291	0	0
T8	40660	198	0	0
T9	45984	609	0	0
T10	310267	41367	0	0
T11	10644	672	0	0
T12	82221	540	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	19679	0	900
T6	241562	3	0	1
T7	218516	326	0	1
T8	40660	0	0	1
T9	45984	0	0	1
T10	310267	0	0	1
T11	10644	10	0	1
T12	82221	0	0	1
T13	2166	0	0	1
T14	7873	1	0	1
T15	0	327	0	0
T16	0	381	0	0
T18	0	2	0	0
T20	0	12	0	0
T21	0	5	0	0
T22	0	36	0	0
T23	164694	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	884750	0	0
T1	7903	69	0	0
T2	2139	33	0	0
T3	313096	690	0	0
T6	241562	3002	0	0
T7	218516	11291	0	0
T8	40660	196	0	0
T9	45984	401	0	0
T10	310267	895	0	0
T11	10644	672	0	0
T12	82221	480	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	444360173	444243339	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	444360173	897270	0	0
GntImpliesValid_A	444360173	897270	0	0
GrantKnown_A	444360173	444243339	0	0
IdxKnown_A	444360173	444243339	0	0
IndexIsCorrect_A	444360173	897270	0	0
LockArbDecision_A	444360173	0	0	0
NoReadyValidNoGrant_A	444360173	372971903	0	0
ReadyAndValidImplyGrant_A	444360173	897270	0	0
ReqAndReadyImplyGrant_A	444360173	897270	0	0
ReqImpliesValid_A	444360173	14202083	0	0
ReqStaysHighUntilGranted0_M	444360173	0	0	0
RoundRobin_A	444360173	31946	0	900
ValidKnown_A	444360173	444243339	0	0
gen_data_port_assertion.DataFlow_A	444360173	897270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	372971903	0	0
T1	7903	6509	0	0
T2	2139	1	0	0
T3	313096	260702	0	0
T6	241562	203942	0	0
T7	218516	1	0	0
T8	40660	35600	0	0
T9	45984	39042	0	0
T10	310267	279350	0	0
T11	10644	1	0	0
T12	82221	70543	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	14202083	0	0
T1	7903	527	0	0
T2	2139	45	0	0
T3	313096	2542	0	0
T6	241562	17277	0	0
T7	218516	12810	0	0
T8	40660	1518	0	0
T9	45984	3149	0	0
T10	310267	303882	0	0
T11	10644	759	0	0
T12	82221	3254	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	31946	0	900
T6	241562	1	0	1
T7	218516	1680	0	1
T8	40660	0	0	1
T9	45984	1	0	1
T10	310267	0	0	1
T11	10644	12	0	1
T12	82221	0	0	1
T13	2166	0	0	1
T14	7873	0	0	1
T15	0	1533	0	0
T16	0	51	0	0
T17	0	9	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	10	0	0
T23	164694	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	444243339	0	0
T1	7903	7867	0	0
T2	2139	2097	0	0
T3	313096	313092	0	0
T6	241562	241037	0	0
T7	218516	217927	0	0
T8	40660	40604	0	0
T9	45984	45950	0	0
T10	310267	310266	0	0
T11	10644	10631	0	0
T12	82221	82159	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444360173	897270	0	0
T1	7903	67	0	0
T2	2139	45	0	0
T3	313096	564	0	0
T6	241562	2125	0	0
T7	218516	12810	0	0
T8	40660	204	0	0
T9	45984	393	0	0
T10	310267	858	0	0
T11	10644	759	0	0
T12	82221	435	0	0