Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1416310	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

224085

1

T1

22

T2

16

T3

72

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	557668	1			T1	49		T2	38		T3	336
values[0x0]	526223	1			T1	51		T2	33		T3	58
values[0x1]	556504	1			T1	56		T2	36		T3	365

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1094958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

545437

1

T1

56

T2

37

T3

291

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25956	1			T1	3		T3	10		T7	10
valid_sources[0x01]	25101	1			T1	1		T2	11		T3	7
valid_sources[0x02]	25697	1			T1	3		T3	9		T9	9
valid_sources[0x03]	25966	1			T1	1		T2	4		T3	17
valid_sources[0x04]	25609	1			T1	7		T2	2		T3	6
valid_sources[0x05]	26568	1			T3	13		T7	3		T8	10
valid_sources[0x06]	25273	1			T1	3		T3	13		T7	11
valid_sources[0x07]	25316	1			T1	2		T3	10		T7	8
valid_sources[0x08]	25452	1			T1	4		T3	11		T7	10
valid_sources[0x09]	24956	1			T1	1		T2	2		T3	8
valid_sources[0x0a]	25888	1			T1	2		T3	18		T7	12
valid_sources[0x0b]	25605	1			T1	5		T3	9		T7	15
valid_sources[0x0c]	25693	1			T1	7		T2	1		T3	14
valid_sources[0x0d]	25145	1			T1	1		T2	3		T3	20
valid_sources[0x0e]	25516	1			T2	3		T3	12		T7	3
valid_sources[0x0f]	24892	1			T1	4		T2	2		T3	12
valid_sources[0x10]	25304	1			T1	2		T2	1		T3	5
valid_sources[0x11]	25585	1			T1	11		T2	1		T3	20
valid_sources[0x12]	26075	1			T1	1		T3	9		T9	5
valid_sources[0x13]	25021	1			T1	3		T2	6		T3	12
valid_sources[0x14]	26595	1			T1	2		T3	15		T9	2
valid_sources[0x15]	25664	1			T3	8		T7	7		T10	65
valid_sources[0x16]	26147	1			T1	2		T3	6		T7	10
valid_sources[0x17]	25068	1			T1	6		T3	14		T7	16
valid_sources[0x18]	25980	1			T3	10		T7	8		T10	74
valid_sources[0x19]	26440	1			T3	13		T7	5		T10	69
valid_sources[0x1a]	25872	1			T1	1		T3	16		T7	7
valid_sources[0x1b]	25409	1			T3	10		T7	11		T8	16
valid_sources[0x1c]	26015	1			T1	1		T3	14		T9	2
valid_sources[0x1d]	26158	1			T1	6		T3	12		T7	15
valid_sources[0x1e]	25821	1			T1	4		T3	10		T7	11
valid_sources[0x1f]	24576	1			T1	3		T3	22		T7	8
valid_sources[0x20]	25651	1			T1	5		T3	11		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23534

1

T1

2

T2

1

T3

22

values[0x0]

all_enables

biggest_size

177122

1

T1

18

T2

13

T3

26

values[0x1]

all_enables

biggest_size

23429

1

T1

2

T2

2

T3

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1429896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

233454

1

T1

26

T2

20

T3

76

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569967	1			T1	48		T2	53		T3	330
values[0x0]	524780	1			T1	49		T2	56		T3	62
values[0x1]	568603	1			T1	58		T2	57		T3	312

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1097513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

565837

1

T1

66

T2

44

T3

274

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26187	1			T3	12		T9	16		T7	10
valid_sources[0x01]	25737	1			T1	2		T2	1		T3	10
valid_sources[0x02]	26155	1			T1	3		T3	16		T7	8
valid_sources[0x03]	26169	1			T3	10		T7	10		T10	47
valid_sources[0x04]	26837	1			T1	2		T2	9		T3	11
valid_sources[0x05]	26297	1			T1	3		T3	11		T9	6
valid_sources[0x06]	25470	1			T1	4		T2	8		T3	15
valid_sources[0x07]	26044	1			T1	1		T3	11		T7	6
valid_sources[0x08]	25541	1			T1	4		T2	3		T3	13
valid_sources[0x09]	25848	1			T3	8		T7	6		T8	16
valid_sources[0x0a]	26100	1			T1	7		T2	1		T3	12
valid_sources[0x0b]	25780	1			T1	5		T2	19		T3	5
valid_sources[0x0c]	25722	1			T2	10		T3	7		T7	13
valid_sources[0x0d]	26147	1			T1	9		T2	6		T3	10
valid_sources[0x0e]	26440	1			T2	4		T3	13		T9	2
valid_sources[0x0f]	25690	1			T1	1		T2	4		T3	12
valid_sources[0x10]	25650	1			T1	4		T3	17		T7	9
valid_sources[0x11]	26168	1			T1	1		T2	2		T3	9
valid_sources[0x12]	26317	1			T2	4		T3	7		T7	13
valid_sources[0x13]	25256	1			T1	3		T2	1		T3	8
valid_sources[0x14]	26454	1			T1	6		T2	8		T3	15
valid_sources[0x15]	25916	1			T1	2		T2	6		T3	11
valid_sources[0x16]	26261	1			T1	1		T3	14		T7	13
valid_sources[0x17]	25062	1			T3	12		T7	8		T10	66
valid_sources[0x18]	25539	1			T1	5		T3	9		T9	2
valid_sources[0x19]	26559	1			T2	3		T3	13		T9	9
valid_sources[0x1a]	26088	1			T1	1		T3	13		T7	7
valid_sources[0x1b]	26580	1			T1	4		T2	3		T3	15
valid_sources[0x1c]	25837	1			T1	6		T2	2		T3	14
valid_sources[0x1d]	25888	1			T3	10		T7	12		T8	4
valid_sources[0x1e]	26150	1			T1	3		T2	10		T3	13
valid_sources[0x1f]	25491	1			T2	3		T3	11		T9	3
valid_sources[0x20]	26060	1			T1	2		T3	6		T7	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24738

1

T1

2

T2

2

T3

24

values[0x0]

all_enables

biggest_size

184285

1

T1

23

T2

14

T3

27

values[0x1]

all_enables

biggest_size

24431

1

T1

1

T2

4

T3

25

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1430428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

226571

1

T1

24

T2

20

T3

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	563921	1			T1	51		T2	74		T3	341
values[0x0]	531501	1			T1	59		T2	54		T3	64
values[0x1]	561577	1			T1	70		T2	56		T3	308

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1104662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

552337

1

T1

58

T2

70

T3

292

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26618	1			T2	2		T3	6		T9	2
valid_sources[0x01]	25644	1			T1	19		T2	3		T3	15
valid_sources[0x02]	26043	1			T2	1		T3	15		T9	4
valid_sources[0x03]	26513	1			T2	2		T3	9		T9	3
valid_sources[0x04]	26100	1			T2	3		T3	14		T7	11
valid_sources[0x05]	24951	1			T2	2		T3	15		T9	1
valid_sources[0x06]	25196	1			T1	1		T3	9		T9	1
valid_sources[0x07]	25736	1			T3	10		T9	2		T7	14
valid_sources[0x08]	25357	1			T1	13		T2	1		T3	9
valid_sources[0x09]	25916	1			T2	6		T3	10		T9	4
valid_sources[0x0a]	26410	1			T3	11		T9	2		T7	10
valid_sources[0x0b]	25406	1			T2	3		T3	13		T9	3
valid_sources[0x0c]	25623	1			T2	5		T3	9		T9	2
valid_sources[0x0d]	25763	1			T2	2		T3	13		T9	2
valid_sources[0x0e]	26087	1			T2	8		T3	12		T9	4
valid_sources[0x0f]	25134	1			T2	2		T3	8		T9	2
valid_sources[0x10]	26155	1			T2	1		T3	13		T9	1
valid_sources[0x11]	26934	1			T1	5		T2	1		T3	13
valid_sources[0x12]	26100	1			T2	1		T3	8		T9	3
valid_sources[0x13]	25794	1			T3	11		T9	1		T7	13
valid_sources[0x14]	26962	1			T3	18		T7	5		T10	77
valid_sources[0x15]	25369	1			T2	4		T3	9		T9	2
valid_sources[0x16]	26009	1			T2	1		T3	9		T9	1
valid_sources[0x17]	26160	1			T1	48		T2	7		T3	10
valid_sources[0x18]	25339	1			T2	1		T3	4		T7	12
valid_sources[0x19]	25938	1			T2	8		T3	19		T9	2
valid_sources[0x1a]	25684	1			T2	1		T3	9		T9	1
valid_sources[0x1b]	25724	1			T2	6		T3	11		T9	2
valid_sources[0x1c]	25748	1			T2	5		T3	10		T9	3
valid_sources[0x1d]	26469	1			T1	15		T2	1		T3	13
valid_sources[0x1e]	25825	1			T2	4		T3	7		T7	11
valid_sources[0x1f]	25326	1			T2	5		T3	11		T9	3
valid_sources[0x20]	26394	1			T2	3		T3	8		T7	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23764

1

T1

1

T2

1

T3

31

values[0x0]

all_enables

biggest_size

179035

1

T1

21

T2

15

T3

27

values[0x1]

all_enables

biggest_size

23772

1

T1

2

T2

4

T3

22