Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7458732	0	0
GntImpliesValid_A	2147483647	7458732	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7458732	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	448371065	0	0
ReadyAndValidImplyGrant_A	2147483647	7458732	0	0
ReqAndReadyImplyGrant_A	2147483647	7458732	0	0
ReqImpliesValid_A	2147483647	32542139	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	47974	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7458732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65568	63288	0	0
T2	7337184	7336032	0	0
T3	2266896	2263512	0	0
T7	10601712	10599528	0	0
T8	504744	503808	0	0
T9	40680	39720	0	0
T10	13929456	13929336	0	0
T11	4958304	4957968	0	0
T12	7839288	7837968	0	0
T13	828000	827304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65568	63288	0	0
T2	7337184	7336032	0	0
T3	2266896	2263512	0	0
T7	10601712	10599528	0	0
T8	504744	503808	0	0
T9	40680	39720	0	0
T10	13929456	13929336	0	0
T11	4958304	4957968	0	0
T12	7839288	7837968	0	0
T13	828000	827304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65568	63288	0	0
T2	7337184	7336032	0	0
T3	2266896	2263512	0	0
T7	10601712	10599528	0	0
T8	504744	503808	0	0
T9	40680	39720	0	0
T10	13929456	13929336	0	0
T11	4958304	4957968	0	0
T12	7839288	7837968	0	0
T13	828000	827304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448371065	0	0
T1	65568	815	0	0
T2	7337184	256247	0	0
T3	2266896	45723	0	0
T7	10601712	576319	0	0
T8	504744	26980	0	0
T9	40680	469	0	0
T10	13929456	524503	0	0
T11	4958304	173012	0	0
T12	7839288	274067	0	0
T13	828000	54181	0	0
T14	0	202	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32542139	0	0
T1	65568	545	0	0
T2	7337184	812	0	0
T3	2266896	63679	0	0
T7	10601712	220231	0	0
T8	504744	2009	0	0
T9	40680	394	0	0
T10	13929456	36937	0	0
T11	4958304	547	0	0
T12	7839288	838	0	0
T13	828000	9138	0	0
T14	0	85	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47974	0	21600
T3	188908	48	0	2
T4	0	2	0	0
T7	883476	34	0	2
T8	42062	0	0	2
T9	3390	0	0	2
T10	1160788	30	0	2
T11	413192	0	0	2
T12	653274	0	0	2
T13	69000	1	0	2
T14	17162	0	0	2
T15	153316	71	0	2
T16	0	11	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	0	316	0	0
T20	0	7	0	0
T21	0	13	0	0
T22	0	1	0	0
T23	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	65568	63288	0	0
T2	7337184	7336032	0	0
T3	2266896	2263512	0	0
T7	10601712	10599528	0	0
T8	504744	503808	0	0
T9	40680	39720	0	0
T10	13929456	13929336	0	0
T11	4958304	4957968	0	0
T12	7839288	7837968	0	0
T13	828000	827304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7458732	0	0
T1	65568	491	0	0
T2	7337184	457	0	0
T3	2266896	40994	0	0
T7	10601712	40651	0	0
T8	504744	1197	0	0
T9	40680	343	0	0
T10	13929456	14092	0	0
T11	4958304	346	0	0
T12	7839288	469	0	0
T13	828000	4024	0	0
T14	0	74	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	818240	0	0
GntImpliesValid_A	421759339	818240	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	818240	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	11117558	0	0
ReadyAndValidImplyGrant_A	421759339	818240	0	0
ReqAndReadyImplyGrant_A	421759339	818240	0	0
ReqImpliesValid_A	421759339	2308792	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	818240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	11117558	0	0
T1	2732	48	0	0
T2	305716	202	0	0
T3	94454	3170	0	0
T7	441738	27474	0	0
T8	21031	1030	0	0
T9	1695	36	0	0
T10	580394	3918	0	0
T11	206596	185	0	0
T12	326637	217	0	0
T13	34500	3117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2308792	0	0
T1	2732	67	0	0
T2	305716	60	0	0
T3	94454	4918	0	0
T7	441738	11373	0	0
T8	21031	153	0	0
T9	1695	55	0	0
T10	580394	1323	0	0
T11	206596	47	0	0
T12	326637	103	0	0
T13	34500	852	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	818240	0	0
T1	2732	57	0	0
T2	305716	50	0	0
T3	94454	4043	0	0
T7	441738	4071	0	0
T8	21031	142	0	0
T9	1695	45	0	0
T10	580394	964	0	0
T11	206596	40	0	0
T12	326637	61	0	0
T13	34500	431	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	839881	0	0
GntImpliesValid_A	421759339	839881	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	839881	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	11138169	0	0
ReadyAndValidImplyGrant_A	421759339	839881	0	0
ReqAndReadyImplyGrant_A	421759339	839881	0	0
ReqImpliesValid_A	421759339	2324960	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	839881	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	11138169	0	0
T1	2732	41	0	0
T2	305716	207	0	0
T3	94454	3180	0	0
T7	441738	25922	0	0
T8	21031	1091	0	0
T9	1695	34	0	0
T10	580394	3742	0	0
T11	206596	254	0	0
T12	326637	185	0	0
T13	34500	3430	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2324960	0	0
T1	2732	64	0	0
T2	305716	70	0	0
T3	94454	6520	0	0
T7	441738	18734	0	0
T8	21031	153	0	0
T9	1695	49	0	0
T10	580394	1216	0	0
T11	206596	84	0	0
T12	326637	66	0	0
T13	34500	1020	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	839881	0	0
T1	2732	52	0	0
T2	305716	54	0	0
T3	94454	4849	0	0
T7	441738	4635	0	0
T8	21031	132	0	0
T9	1695	41	0	0
T10	580394	915	0	0
T11	206596	63	0	0
T12	326637	46	0	0
T13	34500	453	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	194559	0	0
GntImpliesValid_A	421759339	194559	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	194559	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2749092	0	0
ReadyAndValidImplyGrant_A	421759339	194559	0	0
ReqAndReadyImplyGrant_A	421759339	194559	0	0
ReqImpliesValid_A	421759339	544871	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	194559	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2749092	0	0
T1	2732	13	0	0
T2	305716	37	0	0
T3	94454	786	0	0
T7	441738	6631	0	0
T8	21031	236	0	0
T9	1695	7	0	0
T10	580394	1	0	0
T11	206596	32	0	0
T12	326637	62	0	0
T13	34500	855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	544871	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1304	0	0
T7	441738	7637	0	0
T8	21031	33	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	19	0	0
T12	326637	12	0	0
T13	34500	209	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194559	0	0
T1	2732	12	0	0
T2	305716	8	0	0
T3	94454	1044	0	0
T7	441738	1426	0	0
T8	21031	33	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	12	0	0
T13	34500	124	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	219503	0	0
GntImpliesValid_A	421759339	219503	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	219503	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2778925	0	0
ReadyAndValidImplyGrant_A	421759339	219503	0	0
ReqAndReadyImplyGrant_A	421759339	219503	0	0
ReqImpliesValid_A	421759339	568177	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	219503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2778925	0	0
T1	2732	14	0	0
T2	305716	38	0	0
T3	94454	1353	0	0
T7	441738	4218	0	0
T8	21031	270	0	0
T9	1695	9	0	0
T10	580394	1770	0	0
T11	206596	51	0	0
T12	326637	48	0	0
T13	34500	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	568177	0	0
T1	2732	13	0	0
T2	305716	12	0	0
T3	94454	1779	0	0
T7	441738	4780	0	0
T8	21031	41	0	0
T9	1695	8	0	0
T10	580394	1310	0	0
T11	206596	8	0	0
T12	326637	19	0	0
T13	34500	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	219503	0	0
T1	2732	13	0	0
T2	305716	10	0	0
T3	94454	1565	0	0
T7	441738	906	0	0
T8	21031	32	0	0
T9	1695	8	0	0
T10	580394	550	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	199430	0	0
GntImpliesValid_A	421759339	199430	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	199430	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	4563138	0	0
ReadyAndValidImplyGrant_A	421759339	199430	0	0
ReqAndReadyImplyGrant_A	421759339	199430	0	0
ReqImpliesValid_A	421759339	1202601	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	199430	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	4563138	0	0
T1	2732	57	0	0
T2	305716	142	0	0
T3	94454	9310	0	0
T7	441738	3731	0	0
T8	21031	484	0	0
T9	1695	82	0	0
T10	580394	2988	0	0
T11	206596	35	0	0
T12	326637	626	0	0
T13	34500	1188	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	1202601	0	0
T1	2732	17	0	0
T2	305716	26	0	0
T3	94454	9515	0	0
T7	441738	474	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	1754	0	0
T11	206596	8	0	0
T12	326637	38	0	0
T13	34500	192	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	199430	0	0
T1	2732	11	0	0
T2	305716	18	0	0
T3	94454	1642	0	0
T7	441738	334	0	0
T8	21031	33	0	0
T9	1695	9	0	0
T10	580394	523	0	0
T11	206596	8	0	0
T12	326637	13	0	0
T13	34500	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	214476	0	0
GntImpliesValid_A	421759339	214476	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	214476	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	4726915	0	0
ReadyAndValidImplyGrant_A	421759339	214476	0	0
ReqAndReadyImplyGrant_A	421759339	214476	0	0
ReqImpliesValid_A	421759339	1241700	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	214476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	4726915	0	0
T1	2732	221	0	0
T2	305716	75	0	0
T3	94454	4609	0	0
T7	441738	21283	0	0
T8	21031	380	0	0
T9	1695	31	0	0
T10	580394	0	0	0
T11	206596	36	0	0
T12	326637	189	0	0
T13	34500	1919	0	0
T14	0	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	1241700	0	0
T1	2732	15	0	0
T2	305716	18	0	0
T3	94454	2906	0	0
T7	441738	34838	0	0
T8	21031	39	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	12	0	0
T12	326637	16	0	0
T13	34500	202	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214476	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1079	0	0
T7	441738	1659	0	0
T8	21031	39	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	10	0	0
T12	326637	14	0	0
T13	34500	103	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	201385	0	0
GntImpliesValid_A	421759339	201385	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	201385	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	4962298	0	0
ReadyAndValidImplyGrant_A	421759339	201385	0	0
ReqAndReadyImplyGrant_A	421759339	201385	0	0
ReqImpliesValid_A	421759339	1245909	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	201385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	4962298	0	0
T1	2732	130	0	0
T2	305716	106	0	0
T3	94454	3826	0	0
T7	441738	4187	0	0
T8	21031	281	0	0
T9	1695	101	0	0
T10	580394	2912	0	0
T11	206596	13	0	0
T12	326637	59	0	0
T13	34500	623	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	1245909	0	0
T1	2732	35	0	0
T2	305716	25	0	0
T3	94454	837	0	0
T7	441738	2924	0	0
T8	21031	39	0	0
T9	1695	36	0	0
T10	580394	1922	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	201385	0	0
T1	2732	21	0	0
T2	305716	16	0	0
T3	94454	628	0	0
T7	441738	851	0	0
T8	21031	39	0	0
T9	1695	18	0	0
T10	580394	451	0	0
T11	206596	3	0	0
T12	326637	7	0	0
T13	34500	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	193228	0	0
GntImpliesValid_A	421759339	193228	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	193228	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	4186586	0	0
ReadyAndValidImplyGrant_A	421759339	193228	0	0
ReqAndReadyImplyGrant_A	421759339	193228	0	0
ReqImpliesValid_A	421759339	990527	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	193228	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	4186586	0	0
T1	2732	94	0	0
T2	305716	117	0	0
T3	94454	6254	0	0
T7	441738	5381	0	0
T8	21031	273	0	0
T9	1695	36	0	0
T10	580394	0	0	0
T11	206596	60	0	0
T12	326637	95	0	0
T13	34500	713	0	0
T14	0	118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	990527	0	0
T1	2732	23	0	0
T2	305716	10	0	0
T3	94454	6764	0	0
T7	441738	2632	0	0
T8	21031	37	0	0
T9	1695	13	0	0
T10	580394	0	0	0
T11	206596	19	0	0
T12	326637	45	0	0
T13	34500	151	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	193228	0	0
T1	2732	14	0	0
T2	305716	10	0	0
T3	94454	1076	0	0
T7	441738	917	0	0
T8	21031	37	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	15	0	0
T12	326637	10	0	0
T13	34500	112	0	0
T14	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	211179	0	0
GntImpliesValid_A	421759339	211179	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	211179	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2754124	0	0
ReadyAndValidImplyGrant_A	421759339	211179	0	0
ReqAndReadyImplyGrant_A	421759339	211179	0	0
ReqImpliesValid_A	421759339	538085	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	211179	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2754124	0	0
T1	2732	16	0	0
T2	305716	35	0	0
T3	94454	894	0	0
T7	441738	3995	0	0
T8	21031	229	0	0
T9	1695	12	0	0
T10	580394	1	0	0
T11	206596	29	0	0
T12	326637	46	0	0
T13	34500	912	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	538085	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1342	0	0
T7	441738	2668	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	150	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	211179	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	1117	0	0
T7	441738	868	0	0
T8	21031	30	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	6	0	0
T12	326637	15	0	0
T13	34500	123	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	208893	0	0
GntImpliesValid_A	421759339	208893	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	208893	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2766851	0	0
ReadyAndValidImplyGrant_A	421759339	208893	0	0
ReqAndReadyImplyGrant_A	421759339	208893	0	0
ReqImpliesValid_A	421759339	528736	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	208893	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2766851	0	0
T1	2732	16	0	0
T2	305716	40	0	0
T3	94454	1312	0	0
T7	441738	4313	0	0
T8	21031	313	0	0
T9	1695	8	0	0
T10	580394	1	0	0
T11	206596	28	0	0
T12	326637	63	0	0
T13	34500	876	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	528736	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1920	0	0
T7	441738	4944	0	0
T8	21031	36	0	0
T9	1695	9	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	155	0	0
T14	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208893	0	0
T1	2732	15	0	0
T2	305716	10	0	0
T3	94454	1615	0	0
T7	441738	915	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	17	0	0
T13	34500	109	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	202602	0	0
GntImpliesValid_A	421759339	202602	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	202602	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2767670	0	0
ReadyAndValidImplyGrant_A	421759339	202602	0	0
ReqAndReadyImplyGrant_A	421759339	202602	0	0
ReqImpliesValid_A	421759339	534330	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	202602	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2767670	0	0
T1	2732	8	0	0
T2	305716	49	0	0
T3	94454	618	0	0
T7	441738	9096	0	0
T8	21031	432	0	0
T9	1695	11	0	0
T10	580394	1335	0	0
T11	206596	26	0	0
T12	326637	59	0	0
T13	34500	798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	534330	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	638	0	0
T7	441738	11034	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	1146	0	0
T11	206596	12	0	0
T12	326637	21	0	0
T13	34500	214	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	202602	0	0
T1	2732	7	0	0
T2	305716	12	0	0
T3	94454	627	0	0
T7	441738	1948	0	0
T8	21031	52	0	0
T9	1695	10	0	0
T10	580394	428	0	0
T11	206596	6	0	0
T12	326637	12	0	0
T13	34500	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	216629	0	0
GntImpliesValid_A	421759339	216629	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	216629	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2777342	0	0
ReadyAndValidImplyGrant_A	421759339	216629	0	0
ReqAndReadyImplyGrant_A	421759339	216629	0	0
ReqImpliesValid_A	421759339	625410	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	216629	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2777342	0	0
T1	2732	20	0	0
T2	305716	48	0	0
T3	94454	785	0	0
T7	441738	5814	0	0
T8	21031	220	0	0
T9	1695	14	0	0
T10	580394	1715	0	0
T11	206596	57	0	0
T12	326637	32	0	0
T13	34500	660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	625410	0	0
T1	2732	21	0	0
T2	305716	26	0	0
T3	94454	1397	0	0
T7	441738	12383	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	1217	0	0
T11	206596	14	0	0
T12	326637	8	0	0
T13	34500	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216629	0	0
T1	2732	20	0	0
T2	305716	13	0	0
T3	94454	1090	0	0
T7	441738	1725	0	0
T8	21031	27	0	0
T9	1695	13	0	0
T10	580394	524	0	0
T11	206596	11	0	0
T12	326637	8	0	0
T13	34500	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	195678	0	0
GntImpliesValid_A	421759339	195678	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	195678	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2734050	0	0
ReadyAndValidImplyGrant_A	421759339	195678	0	0
ReqAndReadyImplyGrant_A	421759339	195678	0	0
ReqImpliesValid_A	421759339	501110	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	195678	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2734050	0	0
T1	2732	13	0	0
T2	305716	56	0	0
T3	94454	878	0	0
T7	441738	9654	0	0
T8	21031	285	0	0
T9	1695	10	0	0
T10	580394	1828	0	0
T11	206596	72	0	0
T12	326637	62	0	0
T13	34500	676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	501110	0	0
T1	2732	14	0	0
T2	305716	26	0	0
T3	94454	1208	0	0
T7	441738	8722	0	0
T8	21031	39	0	0
T9	1695	13	0	0
T10	580394	1253	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	195678	0	0
T1	2732	13	0	0
T2	305716	16	0	0
T3	94454	1042	0	0
T7	441738	1792	0	0
T8	21031	39	0	0
T9	1695	11	0	0
T10	580394	557	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	208938	0	0
GntImpliesValid_A	421759339	208938	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	208938	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2809740	0	0
ReadyAndValidImplyGrant_A	421759339	208938	0	0
ReqAndReadyImplyGrant_A	421759339	208938	0	0
ReqImpliesValid_A	421759339	594862	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	208938	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2809740	0	0
T1	2732	15	0	0
T2	305716	66	0	0
T3	94454	871	0	0
T7	441738	4673	0	0
T8	21031	185	0	0
T9	1695	10	0	0
T10	580394	3046	0	0
T11	206596	48	0	0
T12	326637	69	0	0
T13	34500	849	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	594862	0	0
T1	2732	14	0	0
T2	305716	31	0	0
T3	94454	1399	0	0
T7	441738	4570	0	0
T8	21031	25	0	0
T9	1695	11	0	0
T10	580394	2223	0	0
T11	206596	8	0	0
T12	326637	25	0	0
T13	34500	168	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208938	0	0
T1	2732	14	0	0
T2	305716	16	0	0
T3	94454	1134	0	0
T7	441738	921	0	0
T8	21031	25	0	0
T9	1695	10	0	0
T10	580394	945	0	0
T11	206596	8	0	0
T12	326637	16	0	0
T13	34500	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	194546	0	0
GntImpliesValid_A	421759339	194546	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	194546	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2750267	0	0
ReadyAndValidImplyGrant_A	421759339	194546	0	0
ReqAndReadyImplyGrant_A	421759339	194546	0	0
ReqImpliesValid_A	421759339	470700	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	194546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2750267	0	0
T1	2732	23	0	0
T2	305716	74	0	0
T3	94454	900	0	0
T7	441738	2883	0	0
T8	21031	331	0	0
T9	1695	10	0	0
T10	580394	1	0	0
T11	206596	15	0	0
T12	326637	51	0	0
T13	34500	1040	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	470700	0	0
T1	2732	22	0	0
T2	305716	23	0	0
T3	94454	1336	0	0
T7	441738	453	0	0
T8	21031	49	0	0
T9	1695	11	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	172	0	0
T14	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	194546	0	0
T1	2732	22	0	0
T2	305716	15	0	0
T3	94454	1117	0	0
T7	441738	385	0	0
T8	21031	49	0	0
T9	1695	10	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	14	0	0
T13	34500	128	0	0
T14	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	208011	0	0
GntImpliesValid_A	421759339	208011	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	208011	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2699218	0	0
ReadyAndValidImplyGrant_A	421759339	208011	0	0
ReqAndReadyImplyGrant_A	421759339	208011	0	0
ReqImpliesValid_A	421759339	612601	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	208011	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2699218	0	0
T1	2732	8	0	0
T2	305716	38	0	0
T3	94454	940	0	0
T7	441738	2879	0	0
T8	21031	233	0	0
T9	1695	9	0	0
T10	580394	1882	0	0
T11	206596	18	0	0
T12	326637	71	0	0
T13	34500	932	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	612601	0	0
T1	2732	7	0	0
T2	305716	10	0	0
T3	94454	1524	0	0
T7	441738	479	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	1301	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	208011	0	0
T1	2732	7	0	0
T2	305716	9	0	0
T3	94454	1231	0	0
T7	441738	371	0	0
T8	21031	36	0	0
T9	1695	8	0	0
T10	580394	560	0	0
T11	206596	5	0	0
T12	326637	16	0	0
T13	34500	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	216197	0	0
GntImpliesValid_A	421759339	216197	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	216197	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2814600	0	0
ReadyAndValidImplyGrant_A	421759339	216197	0	0
ReqAndReadyImplyGrant_A	421759339	216197	0	0
ReqImpliesValid_A	421759339	575935	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	216197	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2814600	0	0
T1	2732	11	0	0
T2	305716	49	0	0
T3	94454	1436	0	0
T7	441738	3880	0	0
T8	21031	321	0	0
T9	1695	8	0	0
T10	580394	1627	0	0
T11	206596	33	0	0
T12	326637	72	0	0
T13	34500	995	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	575935	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	2172	0	0
T7	441738	5449	0	0
T8	21031	36	0	0
T9	1695	7	0	0
T10	580394	1095	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	216197	0	0
T1	2732	10	0	0
T2	305716	9	0	0
T3	94454	1803	0	0
T7	441738	931	0	0
T8	21031	34	0	0
T9	1695	7	0	0
T10	580394	482	0	0
T11	206596	7	0	0
T12	326637	15	0	0
T13	34500	142	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	196359	0	0
GntImpliesValid_A	421759339	196359	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	196359	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2742869	0	0
ReadyAndValidImplyGrant_A	421759339	196359	0	0
ReqAndReadyImplyGrant_A	421759339	196359	0	0
ReqImpliesValid_A	421759339	518054	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	196359	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2742869	0	0
T1	2732	15	0	0
T2	305716	44	0	0
T3	94454	981	0	0
T7	441738	3973	0	0
T8	21031	262	0	0
T9	1695	8	0	0
T10	580394	1	0	0
T11	206596	9	0	0
T12	326637	29	0	0
T13	34500	893	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	518054	0	0
T1	2732	16	0	0
T2	305716	17	0	0
T3	94454	1197	0	0
T7	441738	5011	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	11	0	0
T13	34500	163	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	196359	0	0
T1	2732	15	0	0
T2	305716	9	0	0
T3	94454	1088	0	0
T7	441738	920	0	0
T8	21031	37	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	3	0	0
T12	326637	9	0	0
T13	34500	122	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	209070	0	0
GntImpliesValid_A	421759339	209070	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	209070	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2761079	0	0
ReadyAndValidImplyGrant_A	421759339	209070	0	0
ReqAndReadyImplyGrant_A	421759339	209070	0	0
ReqImpliesValid_A	421759339	539818	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	209070	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2761079	0	0
T1	2732	16	0	0
T2	305716	37	0	0
T3	94454	992	0	0
T7	441738	6762	0	0
T8	21031	280	0	0
T9	1695	6	0	0
T10	580394	1	0	0
T11	206596	31	0	0
T12	326637	55	0	0
T13	34500	798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	539818	0	0
T1	2732	15	0	0
T2	305716	14	0	0
T3	94454	2342	0	0
T7	441738	3384	0	0
T8	21031	33	0	0
T9	1695	7	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	148	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	209070	0	0
T1	2732	15	0	0
T2	305716	11	0	0
T3	94454	1666	0	0
T7	441738	1349	0	0
T8	21031	33	0	0
T9	1695	6	0	0
T10	580394	0	0	0
T11	206596	9	0	0
T12	326637	13	0	0
T13	34500	110	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	214949	0	0
GntImpliesValid_A	421759339	214949	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	214949	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2757253	0	0
ReadyAndValidImplyGrant_A	421759339	214949	0	0
ReqAndReadyImplyGrant_A	421759339	214949	0	0
ReqImpliesValid_A	421759339	576680	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	214949	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2757253	0	0
T1	2732	12	0	0
T2	305716	26	0	0
T3	94454	1460	0	0
T7	441738	12009	0	0
T8	21031	240	0	0
T9	1695	7	0	0
T10	580394	3438	0	0
T11	206596	8	0	0
T12	326637	49	0	0
T13	34500	871	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	576680	0	0
T1	2732	11	0	0
T2	305716	17	0	0
T3	94454	3644	0	0
T7	441738	12453	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	2375	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	153	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	214949	0	0
T1	2732	11	0	0
T2	305716	8	0	0
T3	94454	2551	0	0
T7	441738	2379	0	0
T8	21031	31	0	0
T9	1695	6	0	0
T10	580394	1047	0	0
T11	206596	2	0	0
T12	326637	11	0	0
T13	34500	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	217811	0	0
GntImpliesValid_A	421759339	217811	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	217811	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2758423	0	0
ReadyAndValidImplyGrant_A	421759339	217811	0	0
ReqAndReadyImplyGrant_A	421759339	217811	0	0
ReqImpliesValid_A	421759339	599080	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	217811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2758423	0	0
T1	2732	15	0	0
T2	305716	36	0	0
T3	94454	593	0	0
T7	441738	6063	0	0
T8	21031	208	0	0
T9	1695	8	0	0
T10	580394	1279	0	0
T11	206596	64	0	0
T12	326637	50	0	0
T13	34500	786	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	599080	0	0
T1	2732	14	0	0
T2	305716	24	0	0
T3	94454	617	0	0
T7	441738	7841	0	0
T8	21031	35	0	0
T9	1695	7	0	0
T10	580394	1048	0	0
T11	206596	15	0	0
T12	326637	14	0	0
T13	34500	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	217811	0	0
T1	2732	14	0	0
T2	305716	12	0	0
T3	94454	604	0	0
T7	441738	1307	0	0
T8	21031	29	0	0
T9	1695	7	0	0
T10	580394	416	0	0
T11	206596	13	0	0
T12	326637	12	0	0
T13	34500	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	200100	0	0
GntImpliesValid_A	421759339	200100	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	200100	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	2752843	0	0
ReadyAndValidImplyGrant_A	421759339	200100	0	0
ReqAndReadyImplyGrant_A	421759339	200100	0	0
ReqImpliesValid_A	421759339	533826	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	0	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	200100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2752843	0	0
T1	2732	7	0	0
T2	305716	60	0	0
T3	94454	572	0	0
T7	441738	2966	0	0
T8	21031	250	0	0
T9	1695	10	0	0
T10	580394	5209	0	0
T11	206596	31	0	0
T12	326637	40	0	0
T13	34500	916	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	533826	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	604	0	0
T7	441738	457	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	3580	0	0
T11	206596	6	0	0
T12	326637	16	0	0
T13	34500	152	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	200100	0	0
T1	2732	6	0	0
T2	305716	11	0	0
T3	94454	587	0	0
T7	441738	389	0	0
T8	21031	34	0	0
T9	1695	9	0	0
T10	580394	1581	0	0
T11	206596	6	0	0
T12	326637	14	0	0
T13	34500	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	850802	0	0
GntImpliesValid_A	421759339	850802	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	850802	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	10496834	0	0
ReadyAndValidImplyGrant_A	421759339	850802	0	0
ReqAndReadyImplyGrant_A	421759339	850802	0	0
ReqImpliesValid_A	421759339	2310249	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	18114	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	850802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	10496834	0	0
T1	2732	1	0	0
T2	305716	231	0	0
T3	94454	2	0	0
T7	441738	28181	0	0
T8	21031	801	0	0
T9	1695	1	0	0
T10	580394	5221	0	0
T11	206596	167	0	0
T12	326637	151	0	0
T13	34500	2391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	2310249	0	0
T1	2732	44	0	0
T2	305716	89	0	0
T3	94454	3889	0	0
T7	441738	21568	0	0
T8	21031	132	0	0
T9	1695	45	0	0
T10	580394	3080	0	0
T11	206596	56	0	0
T12	326637	67	0	0
T13	34500	647	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	18114	0	900
T3	94454	20	0	1
T4	0	1	0	0
T7	441738	22	0	1
T8	21031	0	0	1
T9	1695	0	0	1
T10	580394	11	0	1
T11	206596	0	0	1
T12	326637	0	0	1
T13	34500	0	0	1
T14	8581	0	0	1
T15	76658	71	0	1
T16	0	11	0	0
T17	0	1	0	0
T18	0	5	0	0
T19	0	316	0	0
T20	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	850802	0	0
T1	2732	44	0	0
T2	305716	58	0	0
T3	94454	3889	0	0
T7	441738	5493	0	0
T8	21031	116	0	0
T9	1695	45	0	0
T10	580394	1760	0	0
T11	206596	47	0	0
T12	326637	55	0	0
T13	34500	417	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421759339	421636184	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	421759339	826266	0	0
GntImpliesValid_A	421759339	826266	0	0
GrantKnown_A	421759339	421636184	0	0
IdxKnown_A	421759339	421636184	0	0
IndexIsCorrect_A	421759339	826266	0	0
LockArbDecision_A	421759339	0	0	0
NoReadyValidNoGrant_A	421759339	353005221	0	0
ReadyAndValidImplyGrant_A	421759339	826266	0	0
ReqAndReadyImplyGrant_A	421759339	826266	0	0
ReqImpliesValid_A	421759339	12055126	0	0
ReqStaysHighUntilGranted0_M	421759339	0	0	0
RoundRobin_A	421759339	29860	0	900
ValidKnown_A	421759339	421636184	0	0
gen_data_port_assertion.DataFlow_A	421759339	826266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	353005221	0	0
T1	2732	1	0	0
T2	305716	254434	0	0
T3	94454	1	0	0
T7	441738	370351	0	0
T8	21031	18345	0	0
T9	1695	1	0	0
T10	580394	482587	0	0
T11	206596	171710	0	0
T12	326637	271687	0	0
T13	34500	27147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	12055126	0	0
T1	2732	68	0	0
T2	305716	250	0	0
T3	94454	3907	0	0
T7	441738	35423	0	0
T8	21031	849	0	0
T9	1695	30	0	0
T10	580394	11094	0	0
T11	206596	177	0	0
T12	326637	255	0	0
T13	34500	3278	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	29860	0	900
T3	94454	28	0	1
T4	0	1	0	0
T7	441738	12	0	1
T8	21031	0	0	1
T9	1695	0	0	1
T10	580394	19	0	1
T11	206596	0	0	1
T12	326637	0	0	1
T13	34500	1	0	1
T14	8581	0	0	1
T15	76658	0	0	1
T18	0	7	0	0
T20	0	2	0	0
T21	0	13	0	0
T22	0	1	0	0
T23	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	421636184	0	0
T1	2732	2637	0	0
T2	305716	305668	0	0
T3	94454	94313	0	0
T7	441738	441647	0	0
T8	21031	20992	0	0
T9	1695	1655	0	0
T10	580394	580389	0	0
T11	206596	206582	0	0
T12	326637	326582	0	0
T13	34500	34471	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421759339	826266	0	0
T1	2732	68	0	0
T2	305716	57	0	0
T3	94454	3907	0	0
T7	441738	4159	0	0
T8	21031	102	0	0
T9	1695	30	0	0
T10	580394	2389	0	0
T11	206596	39	0	0
T12	326637	52	0	0
T13	34500	424	0	0