Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1617305 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 258054 1 T1 150 T2 185 T3 3


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 635027 1 T1 337 T2 431 T3 11
values[0x0] 604924 1 T1 340 T2 424 T3 2
values[0x1] 635408 1 T1 332 T2 428 T3 13


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1251359 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 624000 1 T1 318 T2 422 T3 9


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30183 1 T1 7 T2 28 T4 8
valid_sources[0x01] 29067 1 T1 8 T2 20 T3 1
valid_sources[0x02] 30015 1 T1 27 T2 44 T3 2
valid_sources[0x03] 29554 1 T1 2 T2 9 T4 5
valid_sources[0x04] 29500 1 T1 32 T2 75 T3 1
valid_sources[0x05] 28992 1 T1 3 T2 13 T7 7
valid_sources[0x06] 30110 1 T1 37 T2 56 T7 4
valid_sources[0x07] 29292 1 T1 20 T7 1 T4 7
valid_sources[0x08] 29323 1 T1 5 T3 2 T4 8
valid_sources[0x09] 30018 1 T1 30 T2 13 T3 1
valid_sources[0x0a] 28148 1 T1 5 T2 23 T3 1
valid_sources[0x0b] 30601 1 T1 16 T4 14 T8 325
valid_sources[0x0c] 28577 1 T1 17 T2 8 T7 4
valid_sources[0x0d] 28991 1 T1 3 T2 8 T3 1
valid_sources[0x0e] 29781 1 T1 43 T2 21 T4 9
valid_sources[0x0f] 29791 1 T1 11 T2 5 T7 3
valid_sources[0x10] 29712 1 T1 11 T2 12 T7 3
valid_sources[0x11] 28072 1 T1 45 T2 25 T7 1
valid_sources[0x12] 28936 1 T1 20 T2 5 T3 1
valid_sources[0x13] 28824 1 T1 3 T2 45 T7 4
valid_sources[0x14] 30286 1 T1 24 T2 12 T7 4
valid_sources[0x15] 28894 1 T1 20 T2 20 T7 2
valid_sources[0x16] 29858 1 T1 20 T2 32 T7 3
valid_sources[0x17] 27897 1 T1 20 T3 1 T7 5
valid_sources[0x18] 28879 1 T1 21 T2 8 T7 3
valid_sources[0x19] 29604 1 T1 3 T2 45 T3 1
valid_sources[0x1a] 28805 1 T1 33 T2 30 T4 10
valid_sources[0x1b] 29010 1 T1 13 T2 14 T3 1
valid_sources[0x1c] 28601 1 T1 5 T3 2 T7 1
valid_sources[0x1d] 29101 1 T1 40 T2 15 T7 1
valid_sources[0x1e] 28834 1 T1 9 T2 18 T4 5
valid_sources[0x1f] 29444 1 T1 7 T2 18 T7 1
valid_sources[0x20] 30326 1 T1 17 T2 7 T7 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27048 1 T1 15 T2 13 T7 2
values[0x0] all_enables biggest_size 204068 1 T1 122 T2 150 T3 1
values[0x1] all_enables biggest_size 26938 1 T1 13 T2 22 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1634386 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266650 1 T1 127 T2 166 T3 1


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 648543 1 T1 354 T2 451 T3 6
values[0x0] 602962 1 T1 288 T2 407 T3 1
values[0x1] 649531 1 T1 307 T2 435 T3 7


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1255771 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 645265 1 T1 325 T2 415 T3 4


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30059 1 T1 67 T2 23 T3 1
valid_sources[0x01] 30329 1 T1 8 T2 21 T4 6
valid_sources[0x02] 29525 1 T1 21 T2 50 T3 1
valid_sources[0x03] 29334 1 T1 4 T2 16 T3 1
valid_sources[0x04] 30222 1 T1 2 T2 53 T7 8
valid_sources[0x05] 28591 1 T1 6 T2 11 T4 7
valid_sources[0x06] 29132 1 T1 19 T2 54 T7 1
valid_sources[0x07] 29851 1 T1 13 T7 5 T4 2
valid_sources[0x08] 30179 1 T1 2 T4 13 T8 465
valid_sources[0x09] 29765 1 T1 9 T2 13 T4 4
valid_sources[0x0a] 30274 1 T1 12 T2 28 T7 6
valid_sources[0x0b] 30043 1 T1 16 T7 1 T4 4
valid_sources[0x0c] 28791 1 T1 11 T2 9 T7 7
valid_sources[0x0d] 30040 1 T1 30 T2 14 T7 7
valid_sources[0x0e] 29966 1 T1 9 T2 33 T4 4
valid_sources[0x0f] 29816 1 T1 34 T2 20 T3 1
valid_sources[0x10] 29478 1 T1 21 T2 14 T4 14
valid_sources[0x11] 29236 1 T1 29 T2 23 T7 1
valid_sources[0x12] 30013 1 T1 1 T2 8 T7 6
valid_sources[0x13] 29728 1 T1 7 T2 46 T4 2
valid_sources[0x14] 30015 1 T1 1 T2 9 T3 1
valid_sources[0x15] 29713 1 T1 26 T2 36 T7 3
valid_sources[0x16] 30516 1 T1 19 T2 17 T4 6
valid_sources[0x17] 29367 1 T1 13 T4 3 T8 422
valid_sources[0x18] 30213 1 T1 17 T2 19 T3 2
valid_sources[0x19] 29960 1 T1 11 T2 54 T7 2
valid_sources[0x1a] 29750 1 T1 18 T2 34 T7 6
valid_sources[0x1b] 29937 1 T1 1 T2 9 T7 1
valid_sources[0x1c] 29464 1 T1 4 T7 13 T4 2
valid_sources[0x1d] 29285 1 T1 1 T2 12 T4 10
valid_sources[0x1e] 29166 1 T1 3 T2 18 T7 3
valid_sources[0x1f] 30193 1 T1 8 T2 7 T4 11
valid_sources[0x20] 29286 1 T1 17 T2 6 T4 15


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27571 1 T1 20 T2 18 T7 1
values[0x0] all_enables biggest_size 211219 1 T1 102 T2 129 T3 1
values[0x1] all_enables biggest_size 27860 1 T1 5 T2 19 T7 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1632319 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 259240 1 T1 139 T2 190 T7 11


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 642340 1 T1 350 T2 431 T3 13
values[0x0] 609839 1 T1 285 T2 451 T3 1
values[0x1] 639380 1 T1 332 T2 429 T3 8


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1263371 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 628188 1 T1 330 T2 457 T3 9


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29647 1 T1 12 T2 35 T4 9
valid_sources[0x01] 29414 1 T1 12 T2 29 T4 6
valid_sources[0x02] 29617 1 T1 10 T2 40 T7 1
valid_sources[0x03] 28961 1 T1 19 T2 12 T4 14
valid_sources[0x04] 29693 1 T1 23 T2 65 T7 3
valid_sources[0x05] 28884 1 T1 12 T2 20 T4 5
valid_sources[0x06] 29300 1 T1 15 T2 53 T7 3
valid_sources[0x07] 29535 1 T1 17 T4 6 T8 374
valid_sources[0x08] 30048 1 T1 18 T4 5 T8 381
valid_sources[0x09] 29164 1 T1 16 T2 7 T3 1
valid_sources[0x0a] 30105 1 T1 18 T2 31 T4 10
valid_sources[0x0b] 29758 1 T1 10 T4 10 T8 363
valid_sources[0x0c] 29329 1 T1 16 T2 14 T3 1
valid_sources[0x0d] 29517 1 T1 14 T2 18 T7 7
valid_sources[0x0e] 29890 1 T1 13 T2 28 T7 6
valid_sources[0x0f] 29779 1 T1 17 T2 8 T4 5
valid_sources[0x10] 29669 1 T1 10 T2 5 T3 2
valid_sources[0x11] 28820 1 T1 19 T2 29 T7 4
valid_sources[0x12] 29608 1 T1 15 T2 7 T4 8
valid_sources[0x13] 29451 1 T1 14 T2 35 T3 1
valid_sources[0x14] 30182 1 T1 13 T2 11 T7 5
valid_sources[0x15] 28868 1 T1 13 T2 16 T3 1
valid_sources[0x16] 30226 1 T1 8 T2 27 T3 1
valid_sources[0x17] 29578 1 T1 18 T4 7 T8 349
valid_sources[0x18] 30138 1 T1 15 T2 18 T4 5
valid_sources[0x19] 29556 1 T1 20 T2 39 T7 2
valid_sources[0x1a] 29052 1 T1 11 T2 34 T7 1
valid_sources[0x1b] 29753 1 T1 11 T2 18 T4 5
valid_sources[0x1c] 29880 1 T1 19 T7 2 T4 10
valid_sources[0x1d] 29957 1 T1 15 T2 12 T4 6
valid_sources[0x1e] 29379 1 T1 16 T2 17 T4 9
valid_sources[0x1f] 29778 1 T1 13 T2 11 T4 5
valid_sources[0x20] 29191 1 T1 17 T2 9 T7 5


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26964 1 T1 16 T2 15 T4 6
values[0x0] all_enables biggest_size 205121 1 T1 103 T2 157 T7 10
values[0x1] all_enables biggest_size 27155 1 T1 20 T2 18 T7 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%