Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7777153	0	0
GntImpliesValid_A	2147483647	7777153	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7777153	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	449661389	0	0
ReadyAndValidImplyGrant_A	2147483647	7777153	0	0
ReqAndReadyImplyGrant_A	2147483647	7777153	0	0
ReqImpliesValid_A	2147483647	34293821	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	58079	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7777153	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	105840	105648	0	0
T2	1675008	1672896	0	0
T3	253200	251688	0	0
T4	12946128	12944904	0	0
T7	5962440	5961912	0	0
T8	2654496	2633064	0	0
T9	2033688	2029608	0	0
T10	1485288	1484400	0	0
T11	10388616	10388568	0	0
T12	3825864	3825792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	105840	105648	0	0
T2	1675008	1672896	0	0
T3	253200	251688	0	0
T4	12946128	12944904	0	0
T7	5962440	5961912	0	0
T8	2654496	2633064	0	0
T9	2033688	2029608	0	0
T10	1485288	1484400	0	0
T11	10388616	10388568	0	0
T12	3825864	3825792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	105840	105648	0	0
T2	1675008	1672896	0	0
T3	253200	251688	0	0
T4	12946128	12944904	0	0
T7	5962440	5961912	0	0
T8	2654496	2633064	0	0
T9	2033688	2029608	0	0
T10	1485288	1484400	0	0
T11	10388616	10388568	0	0
T12	3825864	3825792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	449661389	0	0
T1	105840	2809	0	0
T2	1675008	89841	0	0
T3	253200	14475	0	0
T4	12946128	455231	0	0
T7	5962440	208151	0	0
T8	2654496	59355	0	0
T9	2033688	44818	0	0
T10	1485288	94370	0	0
T11	10388616	389927	0	0
T12	3825864	162714	0	0
T13	0	5799	0	0
T14	0	13053	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34293821	0	0
T1	105840	3311	0	0
T2	1675008	7077	0	0
T3	253200	1428	0	0
T4	12946128	3923	0	0
T7	5962440	655	0	0
T8	2654496	80114	0	0
T9	2033688	57587	0	0
T10	1485288	13652	0	0
T11	10388616	24860	0	0
T12	3825864	12173	0	0
T13	0	2918	0	0
T14	0	6750	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58079	0	21600
T1	8820	20	0	2
T2	139584	0	0	2
T3	21100	0	0	2
T4	1078844	0	0	2
T7	496870	0	0	2
T8	221208	880	0	2
T9	169474	401	0	2
T10	123774	1	0	2
T11	865718	8	0	2
T12	318822	0	0	2
T15	0	9	0	0
T16	0	5	0	0
T17	0	15	0	0
T18	0	3	0	0
T19	0	155	0	0
T20	0	489	0	0
T21	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	105840	105648	0	0
T2	1675008	1672896	0	0
T3	253200	251688	0	0
T4	12946128	12944904	0	0
T7	5962440	5961912	0	0
T8	2654496	2633064	0	0
T9	2033688	2029608	0	0
T10	1485288	1484400	0	0
T11	10388616	10388568	0	0
T12	3825864	3825792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7777153	0	0
T1	105840	2925	0	0
T2	1675008	3877	0	0
T3	253200	721	0	0
T4	12946128	1527	0	0
T7	5962440	388	0	0
T8	2654496	66944	0	0
T9	2033688	43000	0	0
T10	1485288	5596	0	0
T11	10388616	10070	0	0
T12	3825864	7537	0	0
T13	0	2169	0	0
T14	0	149	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	871097	0	0
GntImpliesValid_A	410249814	871097	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	871097	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	12324391	0	0
ReadyAndValidImplyGrant_A	410249814	871097	0	0
ReqAndReadyImplyGrant_A	410249814	871097	0	0
ReqImpliesValid_A	410249814	2548620	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	871097	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	12324391	0	0
T1	4410	223	0	0
T2	69792	2987	0	0
T3	10550	636	0	0
T4	539422	528	0	0
T7	248435	178	0	0
T8	110604	5812	0	0
T9	84737	3274	0	0
T10	61887	4859	0	0
T11	432859	7559	0	0
T12	159411	3310	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	2548620	0	0
T1	4410	364	0	0
T2	69792	435	0	0
T3	10550	168	0	0
T4	539422	176	0	0
T7	248435	65	0	0
T8	110604	9205	0	0
T9	84737	7463	0	0
T10	61887	1149	0	0
T11	432859	4388	0	0
T12	159411	1102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	871097	0	0
T1	4410	293	0	0
T2	69792	390	0	0
T3	10550	83	0	0
T4	539422	125	0	0
T7	248435	43	0	0
T8	110604	7499	0	0
T9	84737	5367	0	0
T10	61887	631	0	0
T11	432859	2113	0	0
T12	159411	820	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	866511	0	0
GntImpliesValid_A	410249814	866511	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	866511	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	12328002	0	0
ReadyAndValidImplyGrant_A	410249814	866511	0	0
ReqAndReadyImplyGrant_A	410249814	866511	0	0
ReqImpliesValid_A	410249814	2498872	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	866511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	12328002	0	0
T1	4410	262	0	0
T2	69792	3293	0	0
T3	10550	529	0	0
T4	539422	643	0	0
T7	248435	166	0	0
T8	110604	5527	0	0
T9	84737	3556	0	0
T10	61887	4812	0	0
T11	432859	2533	0	0
T12	159411	3402	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	2498872	0	0
T1	4410	459	0	0
T2	69792	532	0	0
T3	10550	109	0	0
T4	539422	230	0	0
T7	248435	55	0	0
T8	110604	8011	0	0
T9	84737	6963	0	0
T10	61887	1168	0	0
T11	432859	864	0	0
T12	159411	1105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	866511	0	0
T1	4410	360	0	0
T2	69792	438	0	0
T3	10550	74	0	0
T4	539422	157	0	0
T7	248435	41	0	0
T8	110604	6759	0	0
T9	84737	5258	0	0
T10	61887	654	0	0
T11	432859	627	0	0
T12	159411	825	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	221988	0	0
GntImpliesValid_A	410249814	221988	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	221988	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3098993	0	0
ReadyAndValidImplyGrant_A	410249814	221988	0	0
ReqAndReadyImplyGrant_A	410249814	221988	0	0
ReqImpliesValid_A	410249814	615869	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	221988	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3098993	0	0
T1	4410	80	0	0
T2	69792	836	0	0
T3	10550	138	0	0
T4	539422	1	0	0
T7	248435	25	0	0
T8	110604	1573	0	0
T9	84737	631	0	0
T10	61887	1118	0	0
T11	432859	1	0	0
T12	159411	935	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	615869	0	0
T1	4410	85	0	0
T2	69792	113	0	0
T3	10550	54	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1745	0	0
T9	84737	640	0	0
T10	61887	252	0	0
T11	432859	0	0	0
T12	159411	266	0	0
T13	0	138	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	221988	0	0
T1	4410	82	0	0
T2	69792	113	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	1649	0	0
T9	84737	634	0	0
T10	61887	144	0	0
T11	432859	0	0	0
T12	159411	230	0	0
T13	0	114	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	217158	0	0
GntImpliesValid_A	410249814	217158	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	217158	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3073704	0	0
ReadyAndValidImplyGrant_A	410249814	217158	0	0
ReqAndReadyImplyGrant_A	410249814	217158	0	0
ReqImpliesValid_A	410249814	542968	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	217158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3073704	0	0
T1	4410	96	0	0
T2	69792	870	0	0
T3	10550	196	0	0
T4	539422	1	0	0
T7	248435	61	0	0
T8	110604	2382	0	0
T9	84737	612	0	0
T10	61887	1177	0	0
T11	432859	1575	0	0
T12	159411	1083	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	542968	0	0
T1	4410	103	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	18	0	0
T8	110604	4180	0	0
T9	84737	635	0	0
T10	61887	198	0	0
T11	432859	1262	0	0
T12	159411	302	0	0
T13	0	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217158	0	0
T1	4410	99	0	0
T2	69792	110	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3271	0	0
T9	84737	622	0	0
T10	61887	151	0	0
T11	432859	507	0	0
T12	159411	246	0	0
T13	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	211810	0	0
GntImpliesValid_A	410249814	211810	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	211810	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	5155894	0	0
ReadyAndValidImplyGrant_A	410249814	211810	0	0
ReqAndReadyImplyGrant_A	410249814	211810	0	0
ReqImpliesValid_A	410249814	1179417	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	211810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	5155894	0	0
T1	4410	300	0	0
T2	69792	1959	0	0
T3	10550	224	0	0
T4	539422	0	0	0
T7	248435	65	0	0
T8	110604	5235	0	0
T9	84737	3741	0	0
T10	61887	4529	0	0
T11	432859	0	0	0
T12	159411	1135	0	0
T13	0	1668	0	0
T14	0	5907	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	1179417	0	0
T1	4410	137	0	0
T2	69792	115	0	0
T3	10550	30	0	0
T4	539422	0	0	0
T7	248435	20	0	0
T8	110604	3121	0	0
T9	84737	736	0	0
T10	61887	522	0	0
T11	432859	0	0	0
T12	159411	274	0	0
T13	0	230	0	0
T14	0	1989	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	211810	0	0
T1	4410	98	0	0
T2	69792	102	0	0
T3	10550	23	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1601	0	0
T9	84737	598	0	0
T10	61887	150	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	118	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	209291	0	0
GntImpliesValid_A	410249814	209291	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	209291	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	4827916	0	0
ReadyAndValidImplyGrant_A	410249814	209291	0	0
ReqAndReadyImplyGrant_A	410249814	209291	0	0
ReqImpliesValid_A	410249814	994693	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	209291	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	4827916	0	0
T1	4410	254	0	0
T2	69792	1471	0	0
T3	10550	381	0	0
T4	539422	0	0	0
T7	248435	50	0	0
T8	110604	5069	0	0
T9	84737	11379	0	0
T10	61887	1852	0	0
T11	432859	0	0	0
T12	159411	1201	0	0
T13	0	809	0	0
T14	0	2263	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	994693	0	0
T1	4410	103	0	0
T2	69792	96	0	0
T3	10550	58	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3336	0	0
T9	84737	4852	0	0
T10	61887	305	0	0
T11	432859	0	0	0
T12	159411	268	0	0
T13	0	152	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209291	0	0
T1	4410	76	0	0
T2	69792	96	0	0
T3	10550	31	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1709	0	0
T9	84737	1583	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	216	0	0
T13	0	115	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	213734	0	0
GntImpliesValid_A	410249814	213734	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	213734	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	4942323	0	0
ReadyAndValidImplyGrant_A	410249814	213734	0	0
ReqAndReadyImplyGrant_A	410249814	213734	0	0
ReqImpliesValid_A	410249814	1090286	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	213734	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	4942323	0	0
T1	4410	287	0	0
T2	69792	1541	0	0
T3	10550	292	0	0
T4	539422	0	0	0
T7	248435	43	0	0
T8	110604	5598	0	0
T9	84737	3979	0	0
T10	61887	2908	0	0
T11	432859	0	0	0
T12	159411	1210	0	0
T13	0	3322	0	0
T14	0	4883	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	1090286	0	0
T1	4410	120	0	0
T2	69792	103	0	0
T3	10550	48	0	0
T4	539422	0	0	0
T7	248435	17	0	0
T8	110604	2350	0	0
T9	84737	823	0	0
T10	61887	396	0	0
T11	432859	0	0	0
T12	159411	295	0	0
T13	0	391	0	0
T14	0	725	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213734	0	0
T1	4410	91	0	0
T2	69792	103	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	1283	0	0
T9	84737	630	0	0
T10	61887	173	0	0
T11	432859	0	0	0
T12	159411	203	0	0
T13	0	128	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	207662	0	0
GntImpliesValid_A	410249814	207662	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	207662	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	4693341	0	0
ReadyAndValidImplyGrant_A	410249814	207662	0	0
ReqAndReadyImplyGrant_A	410249814	207662	0	0
ReqImpliesValid_A	410249814	1088417	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	207662	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	4693341	0	0
T1	4410	254	0	0
T2	69792	1556	0	0
T3	10550	335	0	0
T4	539422	2827	0	0
T7	248435	66	0	0
T8	110604	6194	0	0
T9	84737	3369	0	0
T10	61887	2092	0	0
T11	432859	2023	0	0
T12	159411	2716	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	1088417	0	0
T1	4410	115	0	0
T2	69792	128	0	0
T3	10550	15	0	0
T4	539422	1557	0	0
T7	248435	13	0	0
T8	110604	2788	0	0
T9	84737	4219	0	0
T10	61887	279	0	0
T11	432859	1150	0	0
T12	159411	416	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	207662	0	0
T1	4410	83	0	0
T2	69792	94	0	0
T3	10550	15	0	0
T4	539422	455	0	0
T7	248435	13	0	0
T8	110604	1508	0	0
T9	84737	1128	0	0
T10	61887	149	0	0
T11	432859	577	0	0
T12	159411	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	212274	0	0
GntImpliesValid_A	410249814	212274	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	212274	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3138425	0	0
ReadyAndValidImplyGrant_A	410249814	212274	0	0
ReqAndReadyImplyGrant_A	410249814	212274	0	0
ReqImpliesValid_A	410249814	567116	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	212274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3138425	0	0
T1	4410	74	0	0
T2	69792	875	0	0
T3	10550	174	0	0
T4	539422	1	0	0
T7	248435	34	0	0
T8	110604	1553	0	0
T9	84737	870	0	0
T10	61887	1122	0	0
T11	432859	1	0	0
T12	159411	810	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	567116	0	0
T1	4410	91	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	2021	0	0
T9	84737	1367	0	0
T10	61887	244	0	0
T11	432859	0	0	0
T12	159411	231	0	0
T13	0	155	0	0
T14	0	1725	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212274	0	0
T1	4410	82	0	0
T2	69792	118	0	0
T3	10550	20	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1777	0	0
T9	84737	1117	0	0
T10	61887	152	0	0
T11	432859	0	0	0
T12	159411	184	0	0
T13	0	116	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	210915	0	0
GntImpliesValid_A	410249814	210915	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	210915	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3053835	0	0
ReadyAndValidImplyGrant_A	410249814	210915	0	0
ReqAndReadyImplyGrant_A	410249814	210915	0	0
ReqImpliesValid_A	410249814	565465	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	210915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3053835	0	0
T1	4410	69	0	0
T2	69792	887	0	0
T3	10550	91	0	0
T4	539422	1	0	0
T7	248435	30	0	0
T8	110604	1376	0	0
T9	84737	1403	0	0
T10	61887	1264	0	0
T11	432859	1	0	0
T12	159411	999	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	565465	0	0
T1	4410	80	0	0
T2	69792	122	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1898	0	0
T9	84737	1856	0	0
T10	61887	233	0	0
T11	432859	0	0	0
T12	159411	281	0	0
T13	0	142	0	0
T14	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210915	0	0
T1	4410	74	0	0
T2	69792	114	0	0
T3	10550	13	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1627	0	0
T9	84737	1628	0	0
T10	61887	182	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	122	0	0
T14	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	214648	0	0
GntImpliesValid_A	410249814	214648	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	214648	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3051499	0	0
ReadyAndValidImplyGrant_A	410249814	214648	0	0
ReqAndReadyImplyGrant_A	410249814	214648	0	0
ReqImpliesValid_A	410249814	583009	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	214648	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3051499	0	0
T1	4410	68	0	0
T2	69792	827	0	0
T3	10550	187	0	0
T4	539422	1	0	0
T7	248435	76	0	0
T8	110604	1410	0	0
T9	84737	571	0	0
T10	61887	1232	0	0
T11	432859	2852	0	0
T12	159411	803	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	583009	0	0
T1	4410	83	0	0
T2	69792	116	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	22	0	0
T8	110604	1868	0	0
T9	84737	582	0	0
T10	61887	255	0	0
T11	432859	2237	0	0
T12	159411	244	0	0
T13	0	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214648	0	0
T1	4410	75	0	0
T2	69792	116	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	19	0	0
T8	110604	1629	0	0
T9	84737	575	0	0
T10	61887	175	0	0
T11	432859	896	0	0
T12	159411	201	0	0
T13	0	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	213131	0	0
GntImpliesValid_A	410249814	213131	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	213131	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3023944	0	0
ReadyAndValidImplyGrant_A	410249814	213131	0	0
ReqAndReadyImplyGrant_A	410249814	213131	0	0
ReqImpliesValid_A	410249814	552286	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	213131	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3023944	0	0
T1	4410	77	0	0
T2	69792	801	0	0
T3	10550	146	0	0
T4	539422	1	0	0
T7	248435	59	0	0
T8	110604	1463	0	0
T9	84737	1333	0	0
T10	61887	1179	0	0
T11	432859	1	0	0
T12	159411	973	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	552286	0	0
T1	4410	90	0	0
T2	69792	104	0	0
T3	10550	40	0	0
T4	539422	0	0	0
T7	248435	20	0	0
T8	110604	1649	0	0
T9	84737	2724	0	0
T10	61887	187	0	0
T11	432859	0	0	0
T12	159411	286	0	0
T13	0	153	0	0
T14	0	41	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	213131	0	0
T1	4410	83	0	0
T2	69792	104	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1546	0	0
T9	84737	2027	0	0
T10	61887	156	0	0
T11	432859	0	0	0
T12	159411	220	0	0
T13	0	127	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	219193	0	0
GntImpliesValid_A	410249814	219193	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	219193	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3039230	0	0
ReadyAndValidImplyGrant_A	410249814	219193	0	0
ReqAndReadyImplyGrant_A	410249814	219193	0	0
ReqImpliesValid_A	410249814	577484	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	219193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3039230	0	0
T1	4410	76	0	0
T2	69792	766	0	0
T3	10550	150	0	0
T4	539422	1	0	0
T7	248435	58	0	0
T8	110604	2316	0	0
T9	84737	590	0	0
T10	61887	1019	0	0
T11	432859	3222	0	0
T12	159411	789	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	577484	0	0
T1	4410	89	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	3802	0	0
T9	84737	599	0	0
T10	61887	219	0	0
T11	432859	2320	0	0
T12	159411	229	0	0
T13	0	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219193	0	0
T1	4410	82	0	0
T2	69792	105	0	0
T3	10550	18	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	3050	0	0
T9	84737	593	0	0
T10	61887	132	0	0
T11	432859	980	0	0
T12	159411	187	0	0
T13	0	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	212323	0	0
GntImpliesValid_A	410249814	212323	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	212323	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3103532	0	0
ReadyAndValidImplyGrant_A	410249814	212323	0	0
ReqAndReadyImplyGrant_A	410249814	212323	0	0
ReqImpliesValid_A	410249814	532931	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	212323	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3103532	0	0
T1	4410	82	0	0
T2	69792	749	0	0
T3	10550	134	0	0
T4	539422	1	0	0
T7	248435	38	0	0
T8	110604	1869	0	0
T9	84737	1898	0	0
T10	61887	1159	0	0
T11	432859	1	0	0
T12	159411	956	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	532931	0	0
T1	4410	89	0	0
T2	69792	100	0	0
T3	10550	26	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2384	0	0
T9	84737	3647	0	0
T10	61887	254	0	0
T11	432859	0	0	0
T12	159411	304	0	0
T13	0	131	0	0
T14	0	293	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	212323	0	0
T1	4410	85	0	0
T2	69792	97	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	7	0	0
T8	110604	2117	0	0
T9	84737	2771	0	0
T10	61887	157	0	0
T11	432859	0	0	0
T12	159411	237	0	0
T13	0	120	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	210469	0	0
GntImpliesValid_A	410249814	210469	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	210469	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3097776	0	0
ReadyAndValidImplyGrant_A	410249814	210469	0	0
ReqAndReadyImplyGrant_A	410249814	210469	0	0
ReqImpliesValid_A	410249814	569621	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	210469	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3097776	0	0
T1	4410	59	0	0
T2	69792	796	0	0
T3	10550	121	0	0
T4	539422	1815	0	0
T7	248435	45	0	0
T8	110604	1094	0	0
T9	84737	1065	0	0
T10	61887	1032	0	0
T11	432859	1978	0	0
T12	159411	869	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	569621	0	0
T1	4410	70	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	1211	0	0
T7	248435	8	0	0
T8	110604	1128	0	0
T9	84737	1284	0	0
T10	61887	224	0	0
T11	432859	1213	0	0
T12	159411	284	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	210469	0	0
T1	4410	64	0	0
T2	69792	106	0	0
T3	10550	15	0	0
T4	539422	535	0	0
T7	248435	8	0	0
T8	110604	1101	0	0
T9	84737	1173	0	0
T10	61887	139	0	0
T11	432859	564	0	0
T12	159411	226	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	209660	0	0
GntImpliesValid_A	410249814	209660	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	209660	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3082797	0	0
ReadyAndValidImplyGrant_A	410249814	209660	0	0
ReqAndReadyImplyGrant_A	410249814	209660	0	0
ReqImpliesValid_A	410249814	522933	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	209660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3082797	0	0
T1	4410	76	0	0
T2	69792	779	0	0
T3	10550	181	0	0
T4	539422	1	0	0
T7	248435	41	0	0
T8	110604	1715	0	0
T9	84737	1670	0	0
T10	61887	1000	0	0
T11	432859	1	0	0
T12	159411	855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	522933	0	0
T1	4410	83	0	0
T2	69792	106	0	0
T3	10550	26	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2557	0	0
T9	84737	2545	0	0
T10	61887	199	0	0
T11	432859	0	0	0
T12	159411	263	0	0
T13	0	144	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	209660	0	0
T1	4410	79	0	0
T2	69792	106	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	2126	0	0
T9	84737	2106	0	0
T10	61887	141	0	0
T11	432859	0	0	0
T12	159411	196	0	0
T13	0	123	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	235305	0	0
GntImpliesValid_A	410249814	235305	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	235305	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3180867	0	0
ReadyAndValidImplyGrant_A	410249814	235305	0	0
ReqAndReadyImplyGrant_A	410249814	235305	0	0
ReqImpliesValid_A	410249814	562887	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	235305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3180867	0	0
T1	4410	74	0	0
T2	69792	949	0	0
T3	10550	152	0	0
T4	539422	1	0	0
T7	248435	71	0	0
T8	110604	1484	0	0
T9	84737	835	0	0
T10	61887	1207	0	0
T11	432859	1	0	0
T12	159411	909	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	562887	0	0
T1	4410	79	0	0
T2	69792	141	0	0
T3	10550	36	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1962	0	0
T9	84737	1630	0	0
T10	61887	211	0	0
T11	432859	0	0	0
T12	159411	255	0	0
T13	0	118	0	0
T14	0	1159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	235305	0	0
T1	4410	76	0	0
T2	69792	128	0	0
T3	10550	28	0	0
T4	539422	0	0	0
T7	248435	13	0	0
T8	110604	1713	0	0
T9	84737	1231	0	0
T10	61887	159	0	0
T11	432859	0	0	0
T12	159411	222	0	0
T13	0	107	0	0
T14	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	219397	0	0
GntImpliesValid_A	410249814	219397	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	219397	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3102195	0	0
ReadyAndValidImplyGrant_A	410249814	219397	0	0
ReqAndReadyImplyGrant_A	410249814	219397	0	0
ReqImpliesValid_A	410249814	551192	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	219397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3102195	0	0
T1	4410	93	0	0
T2	69792	742	0	0
T3	10550	215	0	0
T4	539422	1	0	0
T7	248435	30	0	0
T8	110604	1130	0	0
T9	84737	620	0	0
T10	61887	1047	0	0
T11	432859	1545	0	0
T12	159411	897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	551192	0	0
T1	4410	100	0	0
T2	69792	93	0	0
T3	10550	38	0	0
T4	539422	0	0	0
T7	248435	6	0	0
T8	110604	1152	0	0
T9	84737	633	0	0
T10	61887	197	0	0
T11	432859	1167	0	0
T12	159411	235	0	0
T13	0	127	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	219397	0	0
T1	4410	96	0	0
T2	69792	93	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	5	0	0
T8	110604	1131	0	0
T9	84737	625	0	0
T10	61887	146	0	0
T11	432859	476	0	0
T12	159411	215	0	0
T13	0	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	217941	0	0
GntImpliesValid_A	410249814	217941	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	217941	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3099211	0	0
ReadyAndValidImplyGrant_A	410249814	217941	0	0
ReqAndReadyImplyGrant_A	410249814	217941	0	0
ReqImpliesValid_A	410249814	571136	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	217941	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3099211	0	0
T1	4410	92	0	0
T2	69792	911	0	0
T3	10550	112	0	0
T4	539422	1	0	0
T7	248435	54	0	0
T8	110604	1855	0	0
T9	84737	1154	0	0
T10	61887	1107	0	0
T11	432859	1403	0	0
T12	159411	1061	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	571136	0	0
T1	4410	95	0	0
T2	69792	113	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	17	0	0
T8	110604	2213	0	0
T9	84737	2133	0	0
T10	61887	188	0	0
T11	432859	1159	0	0
T12	159411	294	0	0
T13	0	195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	217941	0	0
T1	4410	93	0	0
T2	69792	111	0	0
T3	10550	15	0	0
T4	539422	0	0	0
T7	248435	15	0	0
T8	110604	2024	0	0
T9	84737	1642	0	0
T10	61887	155	0	0
T11	432859	440	0	0
T12	159411	240	0	0
T13	0	157	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	218156	0	0
GntImpliesValid_A	410249814	218156	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	218156	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3080706	0	0
ReadyAndValidImplyGrant_A	410249814	218156	0	0
ReqAndReadyImplyGrant_A	410249814	218156	0	0
ReqImpliesValid_A	410249814	601870	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	218156	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3080706	0	0
T1	4410	76	0	0
T2	69792	798	0	0
T3	10550	185	0	0
T4	539422	1	0	0
T7	248435	21	0	0
T8	110604	1926	0	0
T9	84737	630	0	0
T10	61887	984	0	0
T11	432859	1	0	0
T12	159411	996	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	601870	0	0
T1	4410	83	0	0
T2	69792	116	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	17	0	0
T8	110604	3204	0	0
T9	84737	635	0	0
T10	61887	213	0	0
T11	432859	0	0	0
T12	159411	272	0	0
T13	0	116	0	0
T14	0	772	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	218156	0	0
T1	4410	79	0	0
T2	69792	97	0	0
T3	10550	25	0	0
T4	539422	0	0	0
T7	248435	9	0	0
T8	110604	2555	0	0
T9	84737	631	0	0
T10	61887	138	0	0
T11	432859	0	0	0
T12	159411	234	0	0
T13	0	110	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	214783	0	0
GntImpliesValid_A	410249814	214783	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	214783	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3100219	0	0
ReadyAndValidImplyGrant_A	410249814	214783	0	0
ReqAndReadyImplyGrant_A	410249814	214783	0	0
ReqImpliesValid_A	410249814	566281	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	214783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3100219	0	0
T1	4410	65	0	0
T2	69792	855	0	0
T3	10550	164	0	0
T4	539422	1	0	0
T7	248435	47	0	0
T8	110604	1330	0	0
T9	84737	888	0	0
T10	61887	1100	0	0
T11	432859	1452	0	0
T12	159411	834	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	566281	0	0
T1	4410	76	0	0
T2	69792	135	0	0
T3	10550	22	0	0
T4	539422	0	0	0
T7	248435	16	0	0
T8	110604	1441	0	0
T9	84737	1319	0	0
T10	61887	211	0	0
T11	432859	1147	0	0
T12	159411	237	0	0
T13	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	214783	0	0
T1	4410	70	0	0
T2	69792	112	0	0
T3	10550	21	0	0
T4	539422	0	0	0
T7	248435	14	0	0
T8	110604	1376	0	0
T9	84737	1102	0	0
T10	61887	153	0	0
T11	432859	467	0	0
T12	159411	198	0	0
T13	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	222684	0	0
GntImpliesValid_A	410249814	222684	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	222684	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	3064831	0	0
ReadyAndValidImplyGrant_A	410249814	222684	0	0
ReqAndReadyImplyGrant_A	410249814	222684	0	0
ReqImpliesValid_A	410249814	582477	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	0	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	222684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	3064831	0	0
T1	4410	70	0	0
T2	69792	908	0	0
T3	10550	181	0	0
T4	539422	1	0	0
T7	248435	46	0	0
T8	110604	1423	0	0
T9	84737	746	0	0
T10	61887	1126	0	0
T11	432859	1652	0	0
T12	159411	806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	582477	0	0
T1	4410	93	0	0
T2	69792	129	0	0
T3	10550	32	0	0
T4	539422	0	0	0
T7	248435	12	0	0
T8	110604	1815	0	0
T9	84737	1429	0	0
T10	61887	192	0	0
T11	432859	1171	0	0
T12	159411	222	0	0
T13	0	164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	222684	0	0
T1	4410	81	0	0
T2	69792	115	0	0
T3	10550	24	0	0
T4	539422	0	0	0
T7	248435	10	0	0
T8	110604	1609	0	0
T9	84737	1086	0	0
T10	61887	145	0	0
T11	432859	503	0	0
T12	159411	201	0	0
T13	0	129	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	863367	0	0
GntImpliesValid_A	410249814	863367	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	863367	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	11749568	0	0
ReadyAndValidImplyGrant_A	410249814	863367	0	0
ReqAndReadyImplyGrant_A	410249814	863367	0	0
ReqImpliesValid_A	410249814	2306911	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	21417	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	863367	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	11749568	0	0
T1	4410	1	0	0
T2	69792	3183	0	0
T3	10550	403	0	0
T4	539422	396	0	0
T7	248435	140	0	0
T8	110604	20	0	0
T9	84737	3	0	0
T10	61887	3979	0	0
T11	432859	2074	0	0
T12	159411	2686	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	2306911	0	0
T1	4410	294	0	0
T2	69792	532	0	0
T3	10550	108	0	0
T4	539422	193	0	0
T7	248435	61	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	1028	0	0
T11	432859	838	0	0
T12	159411	1131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	21417	0	900
T1	4410	11	0	1
T2	69792	0	0	1
T3	10550	0	0	1
T4	539422	0	0	1
T7	248435	0	0	1
T8	110604	363	0	1
T9	84737	373	0	1
T10	61887	0	0	1
T11	432859	0	0	1
T12	159411	0	0	1
T15	0	4	0	0
T16	0	4	0	0
T17	0	5	0	0
T18	0	1	0	0
T19	0	20	0	0
T20	0	489	0	0
T21	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863367	0	0
T1	4410	294	0	0
T2	69792	460	0	0
T3	10550	74	0	0
T4	539422	141	0	0
T7	248435	46	0	0
T8	110604	8242	0	0
T9	84737	5184	0	0
T10	61887	612	0	0
T11	432859	649	0	0
T12	159411	786	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410249814	410136773	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	410249814	863656	0	0
GntImpliesValid_A	410249814	863656	0	0
GrantKnown_A	410249814	410136773	0	0
IdxKnown_A	410249814	410136773	0	0
IndexIsCorrect_A	410249814	863656	0	0
LockArbDecision_A	410249814	0	0	0
NoReadyValidNoGrant_A	410249814	344248190	0	0
ReadyAndValidImplyGrant_A	410249814	863656	0	0
ReqAndReadyImplyGrant_A	410249814	863656	0	0
ReqImpliesValid_A	410249814	13521080	0	0
ReqStaysHighUntilGranted0_M	410249814	0	0	0
RoundRobin_A	410249814	36662	0	900
ValidKnown_A	410249814	410136773	0	0
gen_data_port_assertion.DataFlow_A	410249814	863656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	344248190	0	0
T1	4410	1	0	0
T2	69792	60502	0	0
T3	10550	9148	0	0
T4	539422	449007	0	0
T7	248435	206707	0	0
T8	110604	1	0	0
T9	84737	1	0	0
T10	61887	51466	0	0
T11	432859	360051	0	0
T12	159411	132479	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	13521080	0	0
T1	4410	330	0	0
T2	69792	3309	0	0
T3	10550	460	0	0
T4	539422	556	0	0
T7	248435	209	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	5328	0	0
T11	432859	5944	0	0
T12	159411	3377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	36662	0	900
T1	4410	9	0	1
T2	69792	0	0	1
T3	10550	0	0	1
T4	539422	0	0	1
T7	248435	0	0	1
T8	110604	517	0	1
T9	84737	28	0	1
T10	61887	1	0	1
T11	432859	8	0	1
T12	159411	0	0	1
T15	0	5	0	0
T16	0	1	0	0
T17	0	10	0	0
T18	0	2	0	0
T19	0	135	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	410136773	0	0
T1	4410	4402	0	0
T2	69792	69704	0	0
T3	10550	10487	0	0
T4	539422	539371	0	0
T7	248435	248413	0	0
T8	110604	109711	0	0
T9	84737	84567	0	0
T10	61887	61850	0	0
T11	432859	432857	0	0
T12	159411	159408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410249814	863656	0	0
T1	4410	330	0	0
T2	69792	449	0	0
T3	10550	59	0	0
T4	539422	114	0	0
T7	248435	48	0	0
T8	110604	8042	0	0
T9	84737	3689	0	0
T10	61887	645	0	0
T11	432859	1271	0	0
T12	159411	770	0	0