Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2407145	1			T1	2466		T2	514		T3	490
values[2]	175084	1			T1	69		T2	18		T3	40
values[3]	42581	1			T7	1		T10	2		T12	1
values[4]	27472	1			T7	1		T6	141		T20	1
values[5]	19730	1			T6	139		T25	16		T186	366
values[6]	15037	1			T6	111		T25	23		T186	244
values[7]	12199	1			T6	91		T25	27		T186	198
values[8]	10409	1			T6	96		T25	43		T186	157
values[9]	8868	1			T6	76		T25	27		T186	172
values[10]	7626	1			T6	64		T25	12		T186	171
values[11]	6700	1			T6	67		T25	23		T186	151
values[12]	6060	1			T6	62		T25	25		T186	98
values[13]	5625	1			T6	62		T25	26		T186	58
values[14]	5069	1			T6	71		T25	22		T186	45
values[15]	4502	1			T6	56		T25	29		T186	34
values[16]	4138	1			T6	41		T25	31		T186	25
values[17]	4045	1			T6	29		T25	13		T186	25
values[18]	3848	1			T6	14		T25	8		T186	39
values[19]	3492	1			T6	10		T25	10		T186	38
values[20]	3240	1			T6	6		T25	14		T186	24
values[21]	3190	1			T6	3		T25	10		T186	20
values[22]	3034	1			T6	6		T25	10		T186	13
values[23]	2827	1			T6	2		T25	7		T186	16
values[24]	2806	1			T6	9		T25	4		T186	15
values[25]	2632	1			T6	2		T25	16		T186	27
values[26]	2564	1			T6	6		T25	16		T186	23
values[27]	2341	1			T6	7		T25	8		T186	15
values[28]	2258	1			T6	9		T25	12		T186	17
values[29]	2141	1			T6	8		T25	7		T186	14
values[30]	2015	1			T6	6		T25	3		T186	17
values[31]	1998	1			T6	2		T25	4		T186	16
values[32]	2075	1			T6	16		T25	5		T186	18
values[33]	1970	1			T6	15		T25	6		T186	26
values[34]	1999	1			T6	8		T25	8		T186	14
values[35]	1827	1			T6	8		T25	4		T186	21
values[36]	1785	1			T6	1		T25	1		T186	16
values[37]	1754	1			T6	1		T186	19		T63	10
values[38]	1674	1			T6	1		T186	30		T63	11
values[39]	1637	1			T6	1		T186	15		T63	10
values[40]	1668	1			T6	1		T186	13		T63	10
values[41]	1671	1			T6	2		T186	12		T63	10
values[42]	1676	1			T6	1		T186	16		T63	10
values[43]	1589	1			T6	4		T186	11		T63	10
values[44]	1599	1			T6	3		T186	16		T63	10
values[45]	1485	1			T6	5		T186	20		T63	10
values[46]	1489	1			T6	5		T186	12		T63	10
values[47]	1455	1			T6	1		T186	15		T63	10
values[48]	1438	1			T6	1		T186	11		T63	10
values[49]	1423	1			T6	1		T186	7		T63	10
values[50]	1402	1			T6	1		T186	10		T63	10
values[51]	1435	1			T6	4		T186	11		T63	10
values[52]	1425	1			T6	3		T186	6		T63	10
values[53]	1415	1			T6	1		T186	14		T63	10
values[54]	1356	1			T6	3		T186	9		T63	10
values[55]	1361	1			T6	8		T186	12		T63	10
values[56]	1342	1			T6	3		T186	12		T63	10
values[57]	1372	1			T6	2		T186	13		T63	10
values[58]	1321	1			T6	1		T186	12		T63	10
values[59]	1391	1			T6	1		T186	12		T63	10
values[60]	1377	1			T6	1		T186	12		T63	10
values[61]	1664	1			T6	4		T186	17		T63	10
values[62]	2813	1			T6	5		T186	37		T63	10
values[63]	8083	1			T6	37		T186	155		T63	11
values[64]	120570	1			T6	72		T186	207		T63	1795

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2477169	1			T1	2429		T2	515		T3	478
values[2]	421865	1			T1	145		T2	49		T3	123
values[3]	42859	1			T2	5		T3	4		T9	95
values[4]	9099	1			T9	10		T8	1		T12	5
values[5]	4228	1			T12	4		T14	1		T6	58
values[6]	2857	1			T6	57		T20	9		T36	5
values[7]	2286	1			T6	38		T20	1		T36	1
values[8]	1886	1			T6	17		T186	16		T63	1
values[9]	1745	1			T6	2		T186	15		T63	1
values[10]	1705	1			T186	18		T63	1		T99	2
values[11]	1611	1			T186	7		T63	1		T99	3
values[12]	1439	1			T186	5		T63	1		T99	2
values[13]	1298	1			T186	8		T63	1		T99	2
values[14]	1209	1			T186	2		T63	1		T99	2
values[15]	1100	1			T186	4		T63	1		T99	2
values[16]	967	1			T186	3		T63	1		T99	2
values[17]	984	1			T186	4		T63	1		T99	2
values[18]	964	1			T186	5		T63	1		T99	2
values[19]	910	1			T186	8		T63	1		T99	2
values[20]	850	1			T186	5		T63	1		T99	2
values[21]	804	1			T186	5		T63	1		T99	2
values[22]	737	1			T186	8		T63	1		T99	2
values[23]	752	1			T186	6		T63	1		T99	2
values[24]	676	1			T186	8		T63	1		T99	2
values[25]	688	1			T186	2		T63	1		T99	2
values[26]	691	1			T186	1		T63	2		T99	2
values[27]	639	1			T186	1		T63	1		T99	2
values[28]	602	1			T186	3		T63	1		T99	2
values[29]	615	1			T186	3		T63	1		T99	2
values[30]	668	1			T186	4		T63	1		T99	2
values[31]	634	1			T186	6		T63	1		T99	1
values[32]	610	1			T186	3		T63	1		T99	1
values[33]	605	1			T186	3		T63	1		T99	2
values[34]	557	1			T186	1		T63	1		T99	3
values[35]	575	1			T186	2		T63	1		T99	2
values[36]	541	1			T186	1		T63	1		T99	2
values[37]	552	1			T186	3		T63	1		T99	2
values[38]	535	1			T186	2		T63	1		T99	2
values[39]	500	1			T186	1		T63	1		T99	2
values[40]	489	1			T186	1		T63	1		T99	2
values[41]	492	1			T186	3		T63	1		T99	2
values[42]	478	1			T186	1		T63	1		T99	2
values[43]	503	1			T186	2		T63	1		T99	2
values[44]	482	1			T63	1		T99	2		T79	1
values[45]	461	1			T63	1		T99	2		T79	1
values[46]	431	1			T63	1		T99	2		T79	1
values[47]	413	1			T63	1		T99	2		T79	1
values[48]	397	1			T63	1		T99	2		T79	1
values[49]	405	1			T63	1		T99	2		T79	1
values[50]	413	1			T63	1		T99	2		T79	1
values[51]	433	1			T63	1		T99	2		T79	1
values[52]	406	1			T63	1		T99	2		T79	1
values[53]	379	1			T63	1		T99	2		T79	1
values[54]	393	1			T63	1		T99	2		T79	1
values[55]	398	1			T63	1		T99	2		T79	1
values[56]	413	1			T63	1		T99	2		T79	1
values[57]	421	1			T63	1		T99	2		T79	1
values[58]	408	1			T63	1		T99	2		T79	1
values[59]	376	1			T63	1		T99	2		T79	1
values[60]	351	1			T63	1		T99	2		T79	1
values[61]	375	1			T63	1		T99	2		T79	1
values[62]	630	1			T63	1		T99	2		T79	1
values[63]	2320	1			T63	1		T99	5		T79	1
values[64]	27788	1			T63	166		T99	149		T79	195

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	308173	1			T1	23		T2	36		T3	5
values[2]	1709490	1			T1	2430		T2	209		T3	455
values[3]	523918	1			T1	68		T2	356		T3	39
values[4]	53760	1			T2	3		T7	7		T8	1
values[5]	35503	1			T6	567		T20	8		T37	1
values[6]	27320	1			T6	320		T20	1		T25	25
values[7]	22083	1			T6	268		T25	13		T186	415
values[8]	18591	1			T6	199		T25	14		T186	283
values[9]	15949	1			T6	173		T25	17		T186	266
values[10]	13563	1			T6	118		T25	16		T186	290
values[11]	11592	1			T6	93		T25	27		T186	242
values[12]	10218	1			T6	89		T25	15		T186	200
values[13]	8720	1			T6	54		T25	26		T186	160
values[14]	7820	1			T6	63		T25	19		T186	133
values[15]	6984	1			T6	43		T25	10		T186	91
values[16]	6227	1			T6	28		T25	19		T186	57
values[17]	5467	1			T6	25		T25	13		T186	32
values[18]	4873	1			T6	34		T25	7		T186	38
values[19]	4413	1			T6	25		T25	10		T186	26
values[20]	4132	1			T6	28		T25	9		T186	14
values[21]	3785	1			T6	29		T25	4		T186	12
values[22]	3535	1			T6	26		T25	7		T186	9
values[23]	3327	1			T6	35		T25	14		T186	14
values[24]	3177	1			T6	39		T25	15		T186	15
values[25]	2842	1			T6	17		T25	7		T186	21
values[26]	2645	1			T6	12		T25	18		T186	30
values[27]	2505	1			T6	7		T25	9		T186	19
values[28]	2394	1			T6	4		T25	2		T186	23
values[29]	2203	1			T6	1		T186	22		T63	10
values[30]	2170	1			T6	1		T186	14		T63	11
values[31]	2131	1			T6	3		T186	13		T63	10
values[32]	2100	1			T6	3		T186	11		T63	10
values[33]	1886	1			T6	2		T186	14		T63	10
values[34]	1826	1			T6	1		T186	12		T63	10
values[35]	1875	1			T6	1		T186	23		T63	10
values[36]	1833	1			T6	1		T186	29		T63	11
values[37]	1765	1			T6	1		T186	12		T63	10
values[38]	1721	1			T6	2		T186	16		T63	10
values[39]	1739	1			T6	7		T186	19		T63	10
values[40]	1743	1			T6	1		T186	25		T63	10
values[41]	1617	1			T6	2		T186	20		T63	10
values[42]	1647	1			T6	1		T186	16		T63	10
values[43]	1632	1			T6	1		T186	15		T63	10
values[44]	1593	1			T6	2		T186	11		T63	10
values[45]	1586	1			T6	2		T186	22		T63	10
values[46]	1532	1			T6	6		T186	15		T63	10
values[47]	1509	1			T6	5		T186	23		T63	10
values[48]	1516	1			T6	5		T186	16		T63	10
values[49]	1488	1			T6	1		T186	18		T63	10
values[50]	1405	1			T6	1		T186	16		T63	10
values[51]	1408	1			T6	1		T186	19		T63	10
values[52]	1413	1			T6	2		T186	9		T63	10
values[53]	1385	1			T6	1		T186	9		T63	10
values[54]	1356	1			T6	1		T186	17		T63	10
values[55]	1391	1			T6	1		T186	17		T63	10
values[56]	1361	1			T6	1		T186	12		T63	10
values[57]	1329	1			T6	1		T186	9		T63	10
values[58]	1315	1			T6	1		T186	9		T63	10
values[59]	1308	1			T6	1		T186	17		T63	10
values[60]	1302	1			T6	2		T186	12		T63	10
values[61]	1427	1			T6	6		T186	16		T63	10
values[62]	2287	1			T6	12		T186	45		T63	11
values[63]	7298	1			T6	28		T186	154		T63	35
values[64]	120754	1			T6	62		T186	309		T63	1873