Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1589745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253057

1

T1

13

T2

2

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624361	1			T1	57		T2	13		T3	11
values[0x0]	592417	1			T1	9		T2	3		T3	2
values[0x1]	626024	1			T1	51		T2	6		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1228675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

614127

1

T1

29

T2

7

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29073	1			T1	3		T3	2		T9	15
valid_sources[0x01]	29110	1			T1	4		T2	1		T9	20
valid_sources[0x02]	29207	1			T1	3		T3	1		T9	10
valid_sources[0x03]	28318	1			T1	2		T2	1		T3	2
valid_sources[0x04]	27903	1			T9	18		T7	3		T4	3
valid_sources[0x05]	29176	1			T1	1		T2	3		T9	21
valid_sources[0x06]	28993	1			T1	3		T2	3		T9	16
valid_sources[0x07]	28158	1			T1	5		T9	18		T8	1
valid_sources[0x08]	29228	1			T1	1		T9	18		T4	1
valid_sources[0x09]	28317	1			T1	2		T2	2		T9	16
valid_sources[0x0a]	28885	1			T1	4		T3	1		T9	25
valid_sources[0x0b]	28883	1			T1	2		T9	12		T8	24
valid_sources[0x0c]	28159	1			T1	2		T9	26		T4	3
valid_sources[0x0d]	28977	1			T1	2		T9	23		T4	6
valid_sources[0x0e]	28810	1			T1	4		T9	11		T7	1
valid_sources[0x0f]	28570	1			T1	2		T2	1		T9	17
valid_sources[0x10]	29322	1			T1	3		T9	30		T4	2
valid_sources[0x11]	29421	1			T1	1		T9	21		T7	1
valid_sources[0x12]	29287	1			T2	1		T9	13		T4	1
valid_sources[0x13]	28270	1			T1	2		T9	21		T8	6
valid_sources[0x14]	29450	1			T1	2		T3	1		T9	15
valid_sources[0x15]	28825	1			T1	1		T2	1		T3	1
valid_sources[0x16]	30103	1			T1	1		T9	18		T7	5
valid_sources[0x17]	28843	1			T1	1		T9	25		T8	8
valid_sources[0x18]	29288	1			T1	2		T9	21		T7	3
valid_sources[0x19]	28811	1			T1	3		T9	23		T10	3
valid_sources[0x1a]	28238	1			T1	1		T3	1		T9	17
valid_sources[0x1b]	29128	1			T3	1		T9	20		T4	1
valid_sources[0x1c]	28536	1			T1	2		T9	17		T4	2
valid_sources[0x1d]	28906	1			T1	2		T2	1		T9	18
valid_sources[0x1e]	28734	1			T3	1		T9	18		T7	3
valid_sources[0x1f]	29716	1			T1	1		T9	17		T7	1
valid_sources[0x20]	28776	1			T1	1		T2	2		T9	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26543

1

T1

4

T2

2

T9

34

values[0x0]

all_enables

biggest_size

200093

1

T1

6

T3

1

T9

58

values[0x1]

all_enables

biggest_size

26421

1

T1

3

T3

2

T9

40

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1598520	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260123

1

T1

14

T9

116

T7

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	636140	1			T1	59		T2	8		T3	13
values[0x0]	586517	1			T1	8		T2	3		T3	2
values[0x1]	635986	1			T1	63		T2	14		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1226550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632093

1

T1

52

T2

9

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28833	1			T1	2		T9	13		T7	3
valid_sources[0x01]	28332	1			T1	2		T9	15		T7	7
valid_sources[0x02]	29478	1			T1	2		T3	2		T9	22
valid_sources[0x03]	29369	1			T1	4		T2	1		T9	20
valid_sources[0x04]	29113	1			T1	1		T9	16		T7	2
valid_sources[0x05]	29349	1			T1	3		T3	1		T9	15
valid_sources[0x06]	28743	1			T3	1		T9	16		T7	1
valid_sources[0x07]	28486	1			T1	4		T3	1		T9	13
valid_sources[0x08]	29068	1			T1	1		T3	1		T9	22
valid_sources[0x09]	28422	1			T1	2		T9	16		T7	2
valid_sources[0x0a]	28506	1			T2	1		T9	11		T7	1
valid_sources[0x0b]	29811	1			T1	3		T2	1		T9	30
valid_sources[0x0c]	28260	1			T1	2		T9	14		T7	2
valid_sources[0x0d]	28739	1			T9	18		T8	5		T4	2
valid_sources[0x0e]	28699	1			T1	1		T3	2		T9	25
valid_sources[0x0f]	29465	1			T1	3		T9	22		T7	3
valid_sources[0x10]	29288	1			T9	15		T7	3		T8	1
valid_sources[0x11]	28776	1			T1	5		T2	1		T9	13
valid_sources[0x12]	29627	1			T1	2		T9	14		T7	2
valid_sources[0x13]	28864	1			T1	3		T9	14		T7	1
valid_sources[0x14]	29609	1			T1	1		T9	12		T8	5
valid_sources[0x15]	29604	1			T3	1		T9	14		T7	3
valid_sources[0x16]	28444	1			T1	3		T2	1		T9	22
valid_sources[0x17]	29440	1			T1	1		T9	29		T8	6
valid_sources[0x18]	29547	1			T1	4		T9	16		T7	4
valid_sources[0x19]	29051	1			T1	2		T9	26		T7	4
valid_sources[0x1a]	28393	1			T1	8		T3	1		T9	12
valid_sources[0x1b]	29281	1			T1	1		T2	1		T3	1
valid_sources[0x1c]	29227	1			T1	2		T3	1		T9	10
valid_sources[0x1d]	29496	1			T1	1		T2	1		T3	1
valid_sources[0x1e]	28771	1			T1	1		T9	15		T7	2
valid_sources[0x1f]	29329	1			T1	2		T2	1		T3	1
valid_sources[0x20]	28457	1			T1	3		T9	16		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27107

1

T1

5

T9

33

T8

4

values[0x0]

all_enables

biggest_size

205719

1

T1

5

T9

47

T7

9

values[0x1]

all_enables

biggest_size

27297

1

T1

4

T9

36

T8

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1600504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254842

1

T1

10

T2

4

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628725	1			T1	42		T2	19		T3	14
values[0x0]	596876	1			T1	11		T2	2		T9	96
values[0x1]	629745	1			T1	62		T2	10		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

618411

1

T1

42

T2

11

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28670	1			T1	2		T9	21		T7	4
valid_sources[0x01]	28930	1			T2	1		T9	11		T8	7
valid_sources[0x02]	29050	1			T1	2		T9	28		T7	6
valid_sources[0x03]	29657	1			T1	2		T2	2		T9	23
valid_sources[0x04]	29033	1			T1	2		T9	10		T7	1
valid_sources[0x05]	29675	1			T9	13		T7	3		T4	6
valid_sources[0x06]	29268	1			T1	9		T3	1		T9	12
valid_sources[0x07]	29290	1			T1	4		T2	2		T9	9
valid_sources[0x08]	29951	1			T1	4		T3	1		T9	18
valid_sources[0x09]	29634	1			T1	1		T9	20		T8	7
valid_sources[0x0a]	28533	1			T9	17		T8	2		T4	2
valid_sources[0x0b]	29285	1			T9	22		T8	1		T4	1
valid_sources[0x0c]	28510	1			T3	2		T9	16		T7	1
valid_sources[0x0d]	28424	1			T9	28		T8	2		T4	4
valid_sources[0x0e]	28437	1			T1	2		T2	1		T3	1
valid_sources[0x0f]	29517	1			T1	12		T2	1		T3	1
valid_sources[0x10]	28845	1			T2	1		T9	19		T8	2
valid_sources[0x11]	29157	1			T9	19		T7	4		T4	4
valid_sources[0x12]	29026	1			T1	1		T9	18		T7	1
valid_sources[0x13]	28492	1			T2	1		T9	29		T8	5
valid_sources[0x14]	29510	1			T9	18		T8	2		T4	1
valid_sources[0x15]	30219	1			T1	3		T9	14		T7	1
valid_sources[0x16]	28491	1			T1	3		T9	12		T7	2
valid_sources[0x17]	29268	1			T2	1		T9	24		T7	3
valid_sources[0x18]	28241	1			T2	2		T3	1		T9	18
valid_sources[0x19]	28811	1			T1	1		T3	1		T9	39
valid_sources[0x1a]	28863	1			T9	18		T8	11		T4	5
valid_sources[0x1b]	30025	1			T1	4		T2	3		T3	1
valid_sources[0x1c]	29323	1			T1	3		T2	1		T9	19
valid_sources[0x1d]	28645	1			T1	3		T3	2		T9	13
valid_sources[0x1e]	29773	1			T1	3		T3	1		T9	10
valid_sources[0x1f]	28508	1			T2	1		T9	14		T8	2
valid_sources[0x20]	29166	1			T9	16		T7	4		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26815

1

T1

3

T2

1

T3

2

values[0x0]

all_enables

biggest_size

201317

1

T1

3

T2

2

T9

49

values[0x1]

all_enables

biggest_size

26710

1

T1

4

T2

1

T3

1