Unified Coverage Report :: Group :: xbar_env_pkg::max_delay_cg_obj::max_delay_cg

Group : xbar_env_pkg::max_delay_cg_obj::max_delay_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

27 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
aes	100.00	1	100	1	64	64
csrng	100.00	1	100	1	64	64
edn0	100.00	1	100	1	64	64
edn1	100.00	1	100	1	64	64
entropy_src	100.00	1	100	1	64	64
flash_ctrl__core	100.00	1	100	1	64	64
flash_ctrl__mem	100.00	1	100	1	64	64
flash_ctrl__prim	100.00	1	100	1	64	64
hmac	100.00	1	100	1	64	64
keymgr	100.00	1	100	1	64	64
kmac	100.00	1	100	1	64	64
otbn	100.00	1	100	1	64	64
peri	100.00	1	100	1	64	64
rom_ctrl__regs	100.00	1	100	1	64	64
rom_ctrl__rom	100.00	1	100	1	64	64
rv_core_ibex__cfg	100.00	1	100	1	64	64
rv_core_ibex__cored	100.00	1	100	1	64	64
rv_core_ibex__corei	100.00	1	100	1	64	64
rv_dm__mem	100.00	1	100	1	64	64
rv_dm__regs	100.00	1	100	1	64	64
rv_dm__sba	100.00	1	100	1	64	64
rv_plic	100.00	1	100	1	64	64
spi_host0	100.00	1	100	1	64	64
spi_host1	100.00	1	100	1	64	64
sram_ctrl_main__ram	100.00	1	100	1	64	64
sram_ctrl_main__regs	100.00	1	100	1	64	64
usbdev	100.00	1	100	1	64	64

---

Group Instance : aes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance aes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance aes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : csrng

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance csrng

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : edn0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance edn0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : edn1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance edn1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : entropy_src

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance entropy_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance entropy_src

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : flash_ctrl__core

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance flash_ctrl__core

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance flash_ctrl__core

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : flash_ctrl__mem

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance flash_ctrl__mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance flash_ctrl__mem

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : flash_ctrl__prim

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance flash_ctrl__prim

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance flash_ctrl__prim

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : hmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance hmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance hmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : keymgr

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance keymgr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance keymgr

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : kmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance kmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance kmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : otbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance otbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance otbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : peri

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance peri

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance peri

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rom_ctrl__regs

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl__regs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rom_ctrl__regs

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rom_ctrl__rom

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rom_ctrl__rom

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rom_ctrl__rom

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_core_ibex__cfg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_core_ibex__cfg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_core_ibex__cfg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_core_ibex__cored

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_core_ibex__cored

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_core_ibex__cored

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_core_ibex__corei

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_core_ibex__corei

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_core_ibex__corei

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_dm__mem

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_dm__mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_dm__mem

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_dm__regs

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_dm__regs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_dm__regs

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_dm__sba

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_dm__sba

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_dm__sba

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : rv_plic

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance rv_plic

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance rv_plic

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : spi_host0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance spi_host0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance spi_host0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : spi_host1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance spi_host1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance spi_host1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sram_ctrl_main__ram

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sram_ctrl_main__ram

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sram_ctrl_main__ram

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : sram_ctrl_main__regs

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sram_ctrl_main__regs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance sram_ctrl_main__regs

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

---

Group Instance : usbdev

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance usbdev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance usbdev

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_dly	3	0	3	100.00	100	1	1	0
cp_rsp_dly	3	0	3	100.00	100	1	1	0

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	250	1			T7	1		T8	1		T12	1
small_delay	345	1			T2	1		T10	1		T19	1
zero	305	1			T1	1		T3	1		T9	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	100	1			T8	1		T67	1		T95	1
small_delay	495	1			T2	1		T7	1		T10	1
zero	305	1			T1	1		T3	1		T9	1