Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8151697	0	0
GntImpliesValid_A	2147483647	8151697	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8151697	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	462814618	0	0
ReadyAndValidImplyGrant_A	2147483647	8151697	0	0
ReqAndReadyImplyGrant_A	2147483647	8151697	0	0
ReqImpliesValid_A	2147483647	35883061	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50595	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8151697	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	254640	253200	0	0
T2	285648	274944	0	0
T3	84072	82752	0	0
T4	54072	52128	0	0
T7	4695312	4694352	0	0
T8	10385592	10385208	0	0
T9	2764200	2762808	0	0
T10	1972656	1971288	0	0
T11	349968	348672	0	0
T12	3864264	3864024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	254640	253200	0	0
T2	285648	274944	0	0
T3	84072	82752	0	0
T4	54072	52128	0	0
T7	4695312	4694352	0	0
T8	10385592	10385208	0	0
T9	2764200	2762808	0	0
T10	1972656	1971288	0	0
T11	349968	348672	0	0
T12	3864264	3864024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	254640	253200	0	0
T2	285648	274944	0	0
T3	84072	82752	0	0
T4	54072	52128	0	0
T7	4695312	4694352	0	0
T8	10385592	10385208	0	0
T9	2764200	2762808	0	0
T10	1972656	1971288	0	0
T11	349968	348672	0	0
T12	3864264	3864024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	462814618	0	0
T1	254640	5545	0	0
T2	285648	17488	0	0
T3	84072	2516	0	0
T4	54072	591	0	0
T7	4695312	164286	0	0
T8	10385592	541401	0	0
T9	2764200	64928	0	0
T10	1972656	128896	0	0
T11	349968	10143	0	0
T12	3864264	135669	0	0
T13	0	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35883061	0	0
T1	254640	4485	0	0
T2	285648	2597	0	0
T3	84072	1966	0	0
T4	54072	432	0	0
T7	4695312	486	0	0
T8	10385592	22257	0	0
T9	2764200	92029	0	0
T10	1972656	17132	0	0
T11	349968	9053	0	0
T12	3864264	877	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50595	0	21600
T1	21220	11	0	2
T2	23804	2	0	2
T3	7006	7	0	2
T4	4506	0	0	2
T5	0	20	0	0
T7	391276	0	0	2
T8	865466	0	0	2
T9	230350	413	0	2
T10	164388	3	0	2
T11	29164	28	0	2
T12	322022	0	0	2
T13	0	11	0	0
T14	0	2	0	0
T15	0	19	0	0
T16	0	7	0	0
T17	0	29	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	254640	253200	0	0
T2	285648	274944	0	0
T3	84072	82752	0	0
T4	54072	52128	0	0
T7	4695312	4694352	0	0
T8	10385592	10385208	0	0
T9	2764200	2762808	0	0
T10	1972656	1971288	0	0
T11	349968	348672	0	0
T12	3864264	3864024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151697	0	0
T1	254640	3880	0	0
T2	285648	1241	0	0
T3	84072	1634	0	0
T4	54072	392	0	0
T7	4695312	314	0	0
T8	10385592	456	0	0
T9	2764200	73103	0	0
T10	1972656	8255	0	0
T11	349968	7586	0	0
T12	3864264	482	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	907093	0	0
GntImpliesValid_A	422695094	907093	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	907093	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	12437474	0	0
ReadyAndValidImplyGrant_A	422695094	907093	0	0
ReqAndReadyImplyGrant_A	422695094	907093	0	0
ReqImpliesValid_A	422695094	2685601	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	907093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	12437474	0	0
T1	10610	378	0	0
T2	11902	955	0	0
T3	3503	128	0	0
T4	2253	41	0	0
T7	195638	171	0	0
T8	432733	20204	0	0
T9	115175	5705	0	0
T10	82194	6712	0	0
T11	14582	613	0	0
T12	161011	214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	2685601	0	0
T1	10610	511	0	0
T2	11902	243	0	0
T3	3503	239	0	0
T4	2253	56	0	0
T7	195638	66	0	0
T8	432733	793	0	0
T9	115175	10391	0	0
T10	82194	1455	0	0
T11	14582	1038	0	0
T12	161011	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	907093	0	0
T1	10610	444	0	0
T2	11902	141	0	0
T3	3503	183	0	0
T4	2253	48	0	0
T7	195638	44	0	0
T8	432733	65	0	0
T9	115175	8046	0	0
T10	82194	918	0	0
T11	14582	825	0	0
T12	161011	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	916581	0	0
GntImpliesValid_A	422695094	916581	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	916581	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	12461537	0	0
ReadyAndValidImplyGrant_A	422695094	916581	0	0
ReqAndReadyImplyGrant_A	422695094	916581	0	0
ReqImpliesValid_A	422695094	2636801	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	916581	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	12461537	0	0
T1	10610	357	0	0
T2	11902	854	0	0
T3	3503	144	0	0
T4	2253	34	0	0
T7	195638	155	0	0
T8	432733	11797	0	0
T9	115175	5763	0	0
T10	82194	6884	0	0
T11	14582	592	0	0
T12	161011	201	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	2636801	0	0
T1	10610	474	0	0
T2	11902	189	0	0
T3	3503	249	0	0
T4	2253	41	0	0
T7	195638	34	0	0
T8	432733	374	0	0
T9	115175	9693	0	0
T10	82194	1486	0	0
T11	14582	1011	0	0
T12	161011	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	916581	0	0
T1	10610	415	0	0
T2	11902	125	0	0
T3	3503	196	0	0
T4	2253	37	0	0
T7	195638	32	0	0
T8	432733	43	0	0
T9	115175	7726	0	0
T10	82194	909	0	0
T11	14582	801	0	0
T12	161011	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	224818	0	0
GntImpliesValid_A	422695094	224818	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	224818	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3040780	0	0
ReadyAndValidImplyGrant_A	422695094	224818	0	0
ReqAndReadyImplyGrant_A	422695094	224818	0	0
ReqImpliesValid_A	422695094	584146	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	224818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3040780	0	0
T1	10610	108	0	0
T2	11902	196	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	33	0	0
T8	432733	3450	0	0
T9	115175	1907	0	0
T10	82194	1827	0	0
T11	14582	215	0	0
T12	161011	21	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	584146	0	0
T1	10610	115	0	0
T2	11902	28	0	0
T3	3503	49	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	10	0	0
T9	115175	2517	0	0
T10	82194	364	0	0
T11	14582	234	0	0
T12	161011	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224818	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	45	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	10	0	0
T9	115175	2210	0	0
T10	82194	249	0	0
T11	14582	224	0	0
T12	161011	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	229319	0	0
GntImpliesValid_A	422695094	229319	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	229319	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3220075	0	0
ReadyAndValidImplyGrant_A	422695094	229319	0	0
ReqAndReadyImplyGrant_A	422695094	229319	0	0
ReqImpliesValid_A	422695094	634617	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	229319	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3220075	0	0
T1	10610	114	0	0
T2	11902	465	0	0
T3	3503	38	0	0
T4	2253	7	0	0
T7	195638	54	0	0
T8	432733	2782	0	0
T9	115175	1605	0	0
T10	82194	1750	0	0
T11	14582	230	0	0
T12	161011	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	634617	0	0
T1	10610	121	0	0
T2	11902	93	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	134	0	0
T9	115175	2763	0	0
T10	82194	321	0	0
T11	14582	245	0	0
T12	161011	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229319	0	0
T1	10610	117	0	0
T2	11902	68	0	0
T3	3503	37	0	0
T4	2253	6	0	0
T7	195638	12	0	0
T8	432733	9	0	0
T9	115175	2182	0	0
T10	82194	227	0	0
T11	14582	237	0	0
T12	161011	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	224090	0	0
GntImpliesValid_A	422695094	224090	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	224090	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	5596905	0	0
ReadyAndValidImplyGrant_A	422695094	224090	0	0
ReqAndReadyImplyGrant_A	422695094	224090	0	0
ReqImpliesValid_A	422695094	1201832	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	224090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	5596905	0	0
T1	10610	1498	0	0
T2	11902	275	0	0
T3	3503	587	0	0
T4	2253	35	0	0
T7	195638	66	0	0
T8	432733	707	0	0
T9	115175	7552	0	0
T10	82194	3238	0	0
T11	14582	1224	0	0
T12	161011	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	1201832	0	0
T1	10610	399	0	0
T2	11902	46	0	0
T3	3503	107	0	0
T4	2253	13	0	0
T7	195638	16	0	0
T8	432733	11	0	0
T9	115175	3691	0	0
T10	82194	382	0	0
T11	14582	376	0	0
T12	161011	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224090	0	0
T1	10610	112	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	10	0	0
T8	432733	11	0	0
T9	115175	2224	0	0
T10	82194	238	0	0
T11	14582	222	0	0
T12	161011	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	215671	0	0
GntImpliesValid_A	422695094	215671	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	215671	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	5476480	0	0
ReadyAndValidImplyGrant_A	422695094	215671	0	0
ReqAndReadyImplyGrant_A	422695094	215671	0	0
ReqImpliesValid_A	422695094	1165022	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	215671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	5476480	0	0
T1	10610	508	0	0
T2	11902	292	0	0
T3	3503	186	0	0
T4	2253	132	0	0
T7	195638	87	0	0
T8	432733	1173	0	0
T9	115175	6012	0	0
T10	82194	3402	0	0
T11	14582	1798	0	0
T12	161011	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	1165022	0	0
T1	10610	115	0	0
T2	11902	38	0	0
T3	3503	52	0	0
T4	2253	13	0	0
T7	195638	29	0	0
T8	432733	122	0	0
T9	115175	8650	0	0
T10	82194	370	0	0
T11	14582	543	0	0
T12	161011	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	215671	0	0
T1	10610	103	0	0
T2	11902	25	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	9	0	0
T8	432733	15	0	0
T9	115175	3264	0	0
T10	82194	207	0	0
T11	14582	220	0	0
T12	161011	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	221186	0	0
GntImpliesValid_A	422695094	221186	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	221186	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	5212864	0	0
ReadyAndValidImplyGrant_A	422695094	221186	0	0
ReqAndReadyImplyGrant_A	422695094	221186	0	0
ReqImpliesValid_A	422695094	1312673	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	221186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	5212864	0	0
T1	10610	417	0	0
T2	11902	362	0	0
T3	3503	589	0	0
T4	2253	95	0	0
T7	195638	44	0	0
T8	432733	575	0	0
T9	115175	4475	0	0
T10	82194	3255	0	0
T11	14582	1670	0	0
T12	161011	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	1312673	0	0
T1	10610	156	0	0
T2	11902	56	0	0
T3	3503	132	0	0
T4	2253	20	0	0
T7	195638	12	0	0
T8	432733	31	0	0
T9	115175	1495	0	0
T10	82194	345	0	0
T11	14582	468	0	0
T12	161011	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221186	0	0
T1	10610	93	0	0
T2	11902	35	0	0
T3	3503	49	0	0
T4	2253	8	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	1333	0	0
T10	82194	218	0	0
T11	14582	211	0	0
T12	161011	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	216033	0	0
GntImpliesValid_A	422695094	216033	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	216033	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	4994440	0	0
ReadyAndValidImplyGrant_A	422695094	216033	0	0
ReqAndReadyImplyGrant_A	422695094	216033	0	0
ReqImpliesValid_A	422695094	1090419	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	216033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	4994440	0	0
T1	10610	701	0	0
T2	11902	276	0	0
T3	3503	208	0	0
T4	2253	67	0	0
T7	195638	112	0	0
T8	432733	5085	0	0
T9	115175	8686	0	0
T10	82194	2804	0	0
T11	14582	926	0	0
T12	161011	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	1090419	0	0
T1	10610	153	0	0
T2	11902	53	0	0
T3	3503	62	0	0
T4	2253	17	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1690	0	0
T10	82194	312	0	0
T11	14582	291	0	0
T12	161011	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	216033	0	0
T1	10610	108	0	0
T2	11902	30	0	0
T3	3503	42	0	0
T4	2253	13	0	0
T7	195638	13	0	0
T8	432733	10	0	0
T9	115175	1304	0	0
T10	82194	238	0	0
T11	14582	187	0	0
T12	161011	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	229173	0	0
GntImpliesValid_A	422695094	229173	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	229173	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3151110	0	0
ReadyAndValidImplyGrant_A	422695094	229173	0	0
ReqAndReadyImplyGrant_A	422695094	229173	0	0
ReqImpliesValid_A	422695094	632784	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	229173	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3151110	0	0
T1	10610	114	0	0
T2	11902	274	0	0
T3	3503	41	0	0
T4	2253	14	0	0
T7	195638	28	0	0
T8	432733	3974	0	0
T9	115175	1656	0	0
T10	82194	1697	0	0
T11	14582	213	0	0
T12	161011	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	632784	0	0
T1	10610	117	0	0
T2	11902	39	0	0
T3	3503	48	0	0
T4	2253	13	0	0
T7	195638	8	0	0
T8	432733	11	0	0
T9	115175	4890	0	0
T10	82194	275	0	0
T11	14582	236	0	0
T12	161011	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	229173	0	0
T1	10610	115	0	0
T2	11902	35	0	0
T3	3503	44	0	0
T4	2253	13	0	0
T7	195638	7	0	0
T8	432733	11	0	0
T9	115175	3271	0	0
T10	82194	234	0	0
T11	14582	224	0	0
T12	161011	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	226976	0	0
GntImpliesValid_A	422695094	226976	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	226976	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3130716	0	0
ReadyAndValidImplyGrant_A	422695094	226976	0	0
ReqAndReadyImplyGrant_A	422695094	226976	0	0
ReqImpliesValid_A	422695094	596775	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	226976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3130716	0	0
T1	10610	71	0	0
T2	11902	352	0	0
T3	3503	45	0	0
T4	2253	14	0	0
T7	195638	50	0	0
T8	432733	3090	0	0
T9	115175	1644	0	0
T10	82194	1675	0	0
T11	14582	204	0	0
T12	161011	51	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	596775	0	0
T1	10610	70	0	0
T2	11902	51	0	0
T3	3503	48	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	763	0	0
T9	115175	2118	0	0
T10	82194	271	0	0
T11	14582	229	0	0
T12	161011	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226976	0	0
T1	10610	70	0	0
T2	11902	43	0	0
T3	3503	46	0	0
T4	2253	13	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	1879	0	0
T10	82194	228	0	0
T11	14582	216	0	0
T12	161011	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	234497	0	0
GntImpliesValid_A	422695094	234497	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	234497	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3072275	0	0
ReadyAndValidImplyGrant_A	422695094	234497	0	0
ReqAndReadyImplyGrant_A	422695094	234497	0	0
ReqImpliesValid_A	422695094	599082	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	234497	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3072275	0	0
T1	10610	99	0	0
T2	11902	302	0	0
T3	3503	42	0	0
T4	2253	10	0	0
T7	195638	31	0	0
T8	432733	4236	0	0
T9	115175	2499	0	0
T10	82194	1534	0	0
T11	14582	189	0	0
T12	161011	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	599082	0	0
T1	10610	104	0	0
T2	11902	69	0	0
T3	3503	45	0	0
T4	2253	11	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	4125	0	0
T10	82194	265	0	0
T11	14582	204	0	0
T12	161011	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	234497	0	0
T1	10610	101	0	0
T2	11902	44	0	0
T3	3503	43	0	0
T4	2253	10	0	0
T7	195638	9	0	0
T8	432733	13	0	0
T9	115175	3310	0	0
T10	82194	228	0	0
T11	14582	196	0	0
T12	161011	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	223956	0	0
GntImpliesValid_A	422695094	223956	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	223956	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3087439	0	0
ReadyAndValidImplyGrant_A	422695094	223956	0	0
ReqAndReadyImplyGrant_A	422695094	223956	0	0
ReqImpliesValid_A	422695094	599146	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	223956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3087439	0	0
T1	10610	109	0	0
T2	11902	202	0	0
T3	3503	30	0	0
T4	2253	8	0	0
T7	195638	32	0	0
T8	432733	2670	0	0
T9	115175	1287	0	0
T10	82194	1952	0	0
T11	14582	206	0	0
T12	161011	30	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	599146	0	0
T1	10610	114	0	0
T2	11902	32	0	0
T3	3503	35	0	0
T4	2253	9	0	0
T7	195638	5	0	0
T8	432733	40	0	0
T9	115175	1365	0	0
T10	82194	325	0	0
T11	14582	241	0	0
T12	161011	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223956	0	0
T1	10610	111	0	0
T2	11902	28	0	0
T3	3503	32	0	0
T4	2253	8	0	0
T7	195638	5	0	0
T8	432733	9	0	0
T9	115175	1324	0	0
T10	82194	254	0	0
T11	14582	223	0	0
T12	161011	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	219285	0	0
GntImpliesValid_A	422695094	219285	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	219285	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3150311	0	0
ReadyAndValidImplyGrant_A	422695094	219285	0	0
ReqAndReadyImplyGrant_A	422695094	219285	0	0
ReqImpliesValid_A	422695094	559365	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	219285	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3150311	0	0
T1	10610	107	0	0
T2	11902	282	0	0
T3	3503	38	0	0
T4	2253	15	0	0
T7	195638	26	0	0
T8	432733	3431	0	0
T9	115175	1992	0	0
T10	82194	1700	0	0
T11	14582	189	0	0
T12	161011	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	559365	0	0
T1	10610	116	0	0
T2	11902	40	0	0
T3	3503	39	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2534	0	0
T10	82194	253	0	0
T11	14582	202	0	0
T12	161011	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	219285	0	0
T1	10610	111	0	0
T2	11902	33	0	0
T3	3503	38	0	0
T4	2253	14	0	0
T7	195638	10	0	0
T8	432733	13	0	0
T9	115175	2261	0	0
T10	82194	217	0	0
T11	14582	195	0	0
T12	161011	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	231104	0	0
GntImpliesValid_A	422695094	231104	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	231104	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3170907	0	0
ReadyAndValidImplyGrant_A	422695094	231104	0	0
ReqAndReadyImplyGrant_A	422695094	231104	0	0
ReqImpliesValid_A	422695094	655505	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	231104	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3170907	0	0
T1	10610	93	0	0
T2	11902	267	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	38	0	0
T8	432733	5508	0	0
T9	115175	1271	0	0
T10	82194	1932	0	0
T11	14582	215	0	0
T12	161011	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	655505	0	0
T1	10610	98	0	0
T2	11902	68	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	10	0	0
T8	432733	405	0	0
T9	115175	2109	0	0
T10	82194	256	0	0
T11	14582	234	0	0
T12	161011	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	231104	0	0
T1	10610	95	0	0
T2	11902	40	0	0
T3	3503	44	0	0
T4	2253	9	0	0
T7	195638	7	0	0
T8	432733	17	0	0
T9	115175	1688	0	0
T10	82194	251	0	0
T11	14582	224	0	0
T12	161011	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	218248	0	0
GntImpliesValid_A	422695094	218248	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	218248	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3113930	0	0
ReadyAndValidImplyGrant_A	422695094	218248	0	0
ReqAndReadyImplyGrant_A	422695094	218248	0	0
ReqImpliesValid_A	422695094	580357	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	218248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3113930	0	0
T1	10610	91	0	0
T2	11902	227	0	0
T3	3503	48	0	0
T4	2253	16	0	0
T7	195638	47	0	0
T8	432733	3232	0	0
T9	115175	1539	0	0
T10	82194	1683	0	0
T11	14582	218	0	0
T12	161011	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	580357	0	0
T1	10610	94	0	0
T2	11902	47	0	0
T3	3503	57	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	325	0	0
T9	115175	2173	0	0
T10	82194	271	0	0
T11	14582	233	0	0
T12	161011	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	218248	0	0
T1	10610	92	0	0
T2	11902	31	0	0
T3	3503	52	0	0
T4	2253	15	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	1854	0	0
T10	82194	220	0	0
T11	14582	225	0	0
T12	161011	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	230659	0	0
GntImpliesValid_A	422695094	230659	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	230659	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3110245	0	0
ReadyAndValidImplyGrant_A	422695094	230659	0	0
ReqAndReadyImplyGrant_A	422695094	230659	0	0
ReqImpliesValid_A	422695094	604439	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	230659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3110245	0	0
T1	10610	113	0	0
T2	11902	124	0	0
T3	3503	50	0	0
T4	2253	10	0	0
T7	195638	21	0	0
T8	432733	3997	0	0
T9	115175	2231	0	0
T10	82194	1507	0	0
T11	14582	204	0	0
T12	161011	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	604439	0	0
T1	10610	120	0	0
T2	11902	23	0	0
T3	3503	61	0	0
T4	2253	11	0	0
T7	195638	4	0	0
T8	432733	579	0	0
T9	115175	3397	0	0
T10	82194	232	0	0
T11	14582	245	0	0
T12	161011	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230659	0	0
T1	10610	116	0	0
T2	11902	22	0	0
T3	3503	55	0	0
T4	2253	10	0	0
T7	195638	4	0	0
T8	432733	16	0	0
T9	115175	2812	0	0
T10	82194	209	0	0
T11	14582	224	0	0
T12	161011	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	243797	0	0
GntImpliesValid_A	422695094	243797	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	243797	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3180496	0	0
ReadyAndValidImplyGrant_A	422695094	243797	0	0
ReqAndReadyImplyGrant_A	422695094	243797	0	0
ReqImpliesValid_A	422695094	644483	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	243797	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3180496	0	0
T1	10610	156	0	0
T2	11902	240	0	0
T3	3503	44	0	0
T4	2253	7	0	0
T7	195638	29	0	0
T8	432733	5716	0	0
T9	115175	1321	0	0
T10	82194	2184	0	0
T11	14582	204	0	0
T12	161011	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	644483	0	0
T1	10610	181	0	0
T2	11902	40	0	0
T3	3503	49	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1373	0	0
T10	82194	384	0	0
T11	14582	231	0	0
T12	161011	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	243797	0	0
T1	10610	168	0	0
T2	11902	34	0	0
T3	3503	46	0	0
T4	2253	6	0	0
T7	195638	7	0	0
T8	432733	12	0	0
T9	115175	1345	0	0
T10	82194	294	0	0
T11	14582	217	0	0
T12	161011	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	230792	0	0
GntImpliesValid_A	422695094	230792	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	230792	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3114416	0	0
ReadyAndValidImplyGrant_A	422695094	230792	0	0
ReqAndReadyImplyGrant_A	422695094	230792	0	0
ReqImpliesValid_A	422695094	606440	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	230792	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3114416	0	0
T1	10610	97	0	0
T2	11902	357	0	0
T3	3503	40	0	0
T4	2253	9	0	0
T7	195638	18	0	0
T8	432733	5686	0	0
T9	115175	1246	0	0
T10	82194	1665	0	0
T11	14582	210	0	0
T12	161011	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	606440	0	0
T1	10610	116	0	0
T2	11902	47	0	0
T3	3503	47	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1296	0	0
T10	82194	257	0	0
T11	14582	253	0	0
T12	161011	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	230792	0	0
T1	10610	106	0	0
T2	11902	39	0	0
T3	3503	43	0	0
T4	2253	8	0	0
T7	195638	4	0	0
T8	432733	15	0	0
T9	115175	1269	0	0
T10	82194	235	0	0
T11	14582	231	0	0
T12	161011	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	223641	0	0
GntImpliesValid_A	422695094	223641	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	223641	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3153480	0	0
ReadyAndValidImplyGrant_A	422695094	223641	0	0
ReqAndReadyImplyGrant_A	422695094	223641	0	0
ReqImpliesValid_A	422695094	622555	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	223641	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3153480	0	0
T1	10610	101	0	0
T2	11902	391	0	0
T3	3503	48	0	0
T4	2253	12	0	0
T7	195638	63	0	0
T8	432733	3606	0	0
T9	115175	1787	0	0
T10	82194	1662	0	0
T11	14582	225	0	0
T12	161011	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	622555	0	0
T1	10610	118	0	0
T2	11902	59	0	0
T3	3503	59	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2715	0	0
T10	82194	260	0	0
T11	14582	254	0	0
T12	161011	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	223641	0	0
T1	10610	109	0	0
T2	11902	43	0	0
T3	3503	53	0	0
T4	2253	11	0	0
T7	195638	10	0	0
T8	432733	6	0	0
T9	115175	2249	0	0
T10	82194	210	0	0
T11	14582	239	0	0
T12	161011	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	226229	0	0
GntImpliesValid_A	422695094	226229	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	226229	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3126201	0	0
ReadyAndValidImplyGrant_A	422695094	226229	0	0
ReqAndReadyImplyGrant_A	422695094	226229	0	0
ReqImpliesValid_A	422695094	592814	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	226229	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3126201	0	0
T1	10610	112	0	0
T2	11902	250	0	0
T3	3503	44	0	0
T4	2253	11	0	0
T7	195638	22	0	0
T8	432733	5485	0	0
T9	115175	1219	0	0
T10	82194	1868	0	0
T11	14582	191	0	0
T12	161011	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	592814	0	0
T1	10610	121	0	0
T2	11902	29	0	0
T3	3503	47	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	406	0	0
T9	115175	1277	0	0
T10	82194	296	0	0
T11	14582	214	0	0
T12	161011	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	226229	0	0
T1	10610	116	0	0
T2	11902	27	0	0
T3	3503	45	0	0
T4	2253	10	0	0
T7	195638	6	0	0
T8	432733	17	0	0
T9	115175	1246	0	0
T10	82194	247	0	0
T11	14582	202	0	0
T12	161011	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	221123	0	0
GntImpliesValid_A	422695094	221123	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	221123	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3099964	0	0
ReadyAndValidImplyGrant_A	422695094	221123	0	0
ReqAndReadyImplyGrant_A	422695094	221123	0	0
ReqImpliesValid_A	422695094	585428	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	221123	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3099964	0	0
T1	10610	101	0	0
T2	11902	223	0	0
T3	3503	37	0	0
T4	2253	14	0	0
T7	195638	39	0	0
T8	432733	4807	0	0
T9	115175	1925	0	0
T10	82194	1663	0	0
T11	14582	214	0	0
T12	161011	83	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	585428	0	0
T1	10610	104	0	0
T2	11902	52	0	0
T3	3503	40	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	3625	0	0
T10	82194	289	0	0
T11	14582	247	0	0
T12	161011	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	221123	0	0
T1	10610	102	0	0
T2	11902	34	0	0
T3	3503	38	0	0
T4	2253	13	0	0
T7	195638	11	0	0
T8	432733	12	0	0
T9	115175	2773	0	0
T10	82194	227	0	0
T11	14582	230	0	0
T12	161011	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	224522	0	0
GntImpliesValid_A	422695094	224522	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	224522	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	3139420	0	0
ReadyAndValidImplyGrant_A	422695094	224522	0	0
ReqAndReadyImplyGrant_A	422695094	224522	0	0
ReqImpliesValid_A	422695094	595510	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	0	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	224522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	3139420	0	0
T1	10610	98	0	0
T2	11902	193	0	0
T3	3503	41	0	0
T4	2253	17	0	0
T7	195638	57	0	0
T8	432733	2289	0	0
T9	115175	1601	0	0
T10	82194	1643	0	0
T11	14582	191	0	0
T12	161011	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	595510	0	0
T1	10610	103	0	0
T2	11902	26	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	16	0	0
T8	432733	8	0	0
T9	115175	2815	0	0
T10	82194	274	0	0
T11	14582	212	0	0
T12	161011	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	224522	0	0
T1	10610	100	0	0
T2	11902	24	0	0
T3	3503	40	0	0
T4	2253	16	0	0
T7	195638	11	0	0
T8	432733	8	0	0
T9	115175	2206	0	0
T10	82194	225	0	0
T11	14582	201	0	0
T12	161011	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	904732	0	0
GntImpliesValid_A	422695094	904732	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	904732	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	11803748	0	0
ReadyAndValidImplyGrant_A	422695094	904732	0	0
ReqAndReadyImplyGrant_A	422695094	904732	0	0
ReqImpliesValid_A	422695094	2419673	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	18400	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	904732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	11803748	0	0
T1	10610	1	0	0
T2	11902	957	0	0
T3	3503	1	0	0
T4	2253	1	0	0
T7	195638	103	0	0
T8	432733	22025	0	0
T9	115175	4	0	0
T10	82194	5816	0	0
T11	14582	1	0	0
T12	161011	232	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	2419673	0	0
T1	10610	438	0	0
T2	11902	214	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	45	0	0
T8	432733	2145	0	0
T9	115175	7450	0	0
T10	82194	1417	0	0
T11	14582	814	0	0
T12	161011	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	18400	0	900
T1	10610	7	0	1
T2	11902	1	0	1
T3	3503	1	0	1
T4	2253	0	0	1
T5	0	8	0	0
T7	195638	0	0	1
T8	432733	0	0	1
T9	115175	105	0	1
T10	82194	0	0	1
T11	14582	10	0	1
T12	161011	0	0	1
T13	0	7	0	0
T15	0	8	0	0
T16	0	7	0	0
T17	0	29	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	904732	0	0
T1	10610	438	0	0
T2	11902	131	0	0
T3	3503	150	0	0
T4	2253	53	0	0
T7	195638	38	0	0
T8	432733	58	0	0
T9	115175	7450	0	0
T10	82194	892	0	0
T11	14582	814	0	0
T12	161011	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422695094	422564540	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422695094	908172	0	0
GntImpliesValid_A	422695094	908172	0	0
GrantKnown_A	422695094	422564540	0	0
IdxKnown_A	422695094	422564540	0	0
IndexIsCorrect_A	422695094	908172	0	0
LockArbDecision_A	422695094	0	0	0
NoReadyValidNoGrant_A	422695094	354769405	0	0
ReadyAndValidImplyGrant_A	422695094	908172	0	0
ReqAndReadyImplyGrant_A	422695094	908172	0	0
ReqImpliesValid_A	422695094	13677594	0	0
ReqStaysHighUntilGranted0_M	422695094	0	0	0
RoundRobin_A	422695094	32195	0	900
ValidKnown_A	422695094	422564540	0	0
gen_data_port_assertion.DataFlow_A	422695094	908172	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	354769405	0	0
T1	10610	1	0	0
T2	11902	9172	0	0
T3	3503	1	0	0
T4	2253	0	0	0
T7	195638	162960	0	0
T8	432733	415876	0	0
T9	115175	1	0	0
T10	82194	68843	0	0
T11	14582	1	0	0
T12	161011	133934	0	0
T13	0	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	13677594	0	0
T1	10610	427	0	0
T2	11902	1015	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	128	0	0
T8	432733	16019	0	0
T9	115175	7877	0	0
T10	82194	6772	0	0
T11	14582	798	0	0
T12	161011	291	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	32195	0	900
T1	10610	4	0	1
T2	11902	1	0	1
T3	3503	6	0	1
T4	2253	0	0	1
T5	0	12	0	0
T7	195638	0	0	1
T8	432733	0	0	1
T9	115175	308	0	1
T10	82194	3	0	1
T11	14582	18	0	1
T12	161011	0	0	1
T13	0	4	0	0
T14	0	2	0	0
T15	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	422564540	0	0
T1	10610	10550	0	0
T2	11902	11456	0	0
T3	3503	3448	0	0
T4	2253	2172	0	0
T7	195638	195598	0	0
T8	432733	432717	0	0
T9	115175	115117	0	0
T10	82194	82137	0	0
T11	14582	14528	0	0
T12	161011	161001	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422695094	908172	0	0
T1	10610	427	0	0
T2	11902	138	0	0
T3	3503	229	0	0
T4	2253	39	0	0
T7	195638	30	0	0
T8	432733	50	0	0
T9	115175	7877	0	0
T10	82194	880	0	0
T11	14582	798	0	0
T12	161011	61	0	0