Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1475483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235408

1

T1

12

T2

18

T3

234

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	580344	1			T1	41		T2	41		T3	602
values[0x0]	549553	1			T1	31		T2	47		T3	570
values[0x1]	580994	1			T1	43		T2	39		T3	567

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1140127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

570764

1

T1

37

T2

43

T3

580

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26267	1			T1	1		T2	2		T3	30
valid_sources[0x01]	27200	1			T2	2		T3	30		T8	52
valid_sources[0x02]	26539	1			T1	3		T2	3		T3	27
valid_sources[0x03]	27120	1			T1	1		T2	1		T3	30
valid_sources[0x04]	26326	1			T1	3		T3	26		T8	60
valid_sources[0x05]	27115	1			T3	30		T8	52		T9	1
valid_sources[0x06]	26637	1			T1	1		T3	30		T8	38
valid_sources[0x07]	26681	1			T1	2		T2	1		T3	28
valid_sources[0x08]	26312	1			T1	2		T2	2		T3	20
valid_sources[0x09]	26504	1			T1	1		T2	2		T3	37
valid_sources[0x0a]	26385	1			T1	2		T2	3		T3	27
valid_sources[0x0b]	27399	1			T2	2		T3	31		T8	61
valid_sources[0x0c]	26315	1			T1	2		T2	1		T3	26
valid_sources[0x0d]	26877	1			T3	32		T8	55		T7	26
valid_sources[0x0e]	27010	1			T1	1		T3	26		T8	59
valid_sources[0x0f]	26498	1			T3	26		T8	50		T9	2
valid_sources[0x10]	27354	1			T1	1		T2	2		T3	25
valid_sources[0x11]	27152	1			T1	3		T3	30		T8	49
valid_sources[0x12]	26947	1			T2	2		T3	24		T8	57
valid_sources[0x13]	26174	1			T1	3		T2	2		T3	20
valid_sources[0x14]	26249	1			T1	3		T3	28		T8	45
valid_sources[0x15]	26697	1			T1	2		T2	3		T3	37
valid_sources[0x16]	27183	1			T1	3		T2	1		T3	30
valid_sources[0x17]	26731	1			T1	5		T3	24		T8	46
valid_sources[0x18]	26979	1			T1	2		T2	2		T3	26
valid_sources[0x19]	27412	1			T2	12		T3	22		T8	39
valid_sources[0x1a]	26952	1			T1	2		T2	4		T3	26
valid_sources[0x1b]	26543	1			T1	1		T3	29		T8	46
valid_sources[0x1c]	27154	1			T1	1		T3	24		T8	57
valid_sources[0x1d]	26716	1			T1	4		T2	2		T3	22
valid_sources[0x1e]	26229	1			T1	4		T2	8		T3	29
valid_sources[0x1f]	25771	1			T1	2		T2	5		T3	32
valid_sources[0x20]	26734	1			T1	2		T2	5		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24792

1

T1

1

T3

25

T8

52

values[0x0]

all_enables

biggest_size

185907

1

T1

10

T2

16

T3

192

values[0x1]

all_enables

biggest_size

24709

1

T1

1

T2

2

T3

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1496074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243634

1

T1

19

T2

22

T3

236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	595039	1			T1	53		T2	38		T3	562
values[0x0]	549553	1			T1	39		T2	38		T3	571
values[0x1]	595116	1			T1	43		T2	33		T3	597

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1148575	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591133

1

T1

46

T2

47

T3

558

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27412	1			T1	2		T3	33		T8	43
valid_sources[0x01]	27379	1			T1	9		T2	8		T3	16
valid_sources[0x02]	27184	1			T1	2		T3	34		T8	51
valid_sources[0x03]	27487	1			T1	2		T3	11		T8	42
valid_sources[0x04]	26964	1			T1	1		T3	49		T8	32
valid_sources[0x05]	27408	1			T1	5		T2	1		T3	27
valid_sources[0x06]	27708	1			T1	5		T3	35		T8	48
valid_sources[0x07]	28040	1			T3	54		T8	46		T7	15
valid_sources[0x08]	27043	1			T1	10		T2	1		T3	22
valid_sources[0x09]	27109	1			T3	30		T8	50		T7	6
valid_sources[0x0a]	27526	1			T1	1		T3	34		T8	52
valid_sources[0x0b]	27513	1			T1	2		T3	40		T8	37
valid_sources[0x0c]	27369	1			T3	15		T8	40		T9	1
valid_sources[0x0d]	26743	1			T1	4		T3	21		T8	51
valid_sources[0x0e]	27231	1			T2	3		T3	16		T8	40
valid_sources[0x0f]	27227	1			T2	2		T3	13		T8	47
valid_sources[0x10]	27029	1			T1	3		T2	2		T3	40
valid_sources[0x11]	26820	1			T1	1		T2	5		T3	19
valid_sources[0x12]	27491	1			T2	5		T3	38		T8	58
valid_sources[0x13]	27076	1			T3	13		T8	43		T9	6
valid_sources[0x14]	26960	1			T1	4		T2	3		T3	15
valid_sources[0x15]	26513	1			T2	5		T3	17		T8	48
valid_sources[0x16]	26955	1			T1	6		T2	1		T3	27
valid_sources[0x17]	26880	1			T1	8		T2	2		T3	24
valid_sources[0x18]	27484	1			T2	2		T3	41		T8	42
valid_sources[0x19]	27373	1			T1	1		T2	2		T3	8
valid_sources[0x1a]	27452	1			T1	4		T3	27		T8	41
valid_sources[0x1b]	26965	1			T1	1		T2	1		T3	32
valid_sources[0x1c]	27002	1			T2	5		T3	10		T8	47
valid_sources[0x1d]	27508	1			T1	1		T2	1		T3	53
valid_sources[0x1e]	27158	1			T2	5		T3	42		T8	51
valid_sources[0x1f]	26376	1			T1	1		T3	35		T8	50
valid_sources[0x20]	27048	1			T1	3		T2	2		T3	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25349

1

T1

6

T2

2

T3

17

values[0x0]

all_enables

biggest_size

192989

1

T1

11

T2

17

T3

195

values[0x1]

all_enables

biggest_size

25296

1

T1

2

T2

3

T3

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1492693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

237676

1

T1

25

T2

12

T3

209

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586975	1			T1	54		T2	27		T3	605
values[0x0]	555996	1			T1	59		T2	35		T3	568
values[0x1]	587398	1			T1	59		T2	27		T3	633

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1153784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

576585

1

T1

61

T2

24

T3

563

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26401	1			T2	2		T3	27		T8	57
valid_sources[0x01]	27828	1			T2	1		T3	31		T8	51
valid_sources[0x02]	27012	1			T1	5		T3	23		T8	48
valid_sources[0x03]	26896	1			T1	5		T2	3		T3	33
valid_sources[0x04]	26840	1			T2	1		T3	28		T8	52
valid_sources[0x05]	26876	1			T2	2		T3	23		T8	44
valid_sources[0x06]	27065	1			T1	5		T2	2		T3	24
valid_sources[0x07]	27265	1			T1	2		T3	29		T8	46
valid_sources[0x08]	26757	1			T3	20		T8	46		T7	4
valid_sources[0x09]	26688	1			T3	26		T8	50		T7	3
valid_sources[0x0a]	26789	1			T2	2		T3	25		T8	50
valid_sources[0x0b]	27362	1			T1	2		T2	3		T3	31
valid_sources[0x0c]	27671	1			T1	5		T2	1		T3	24
valid_sources[0x0d]	27201	1			T2	1		T3	22		T8	45
valid_sources[0x0e]	27196	1			T3	23		T8	48		T7	9
valid_sources[0x0f]	27091	1			T2	2		T3	32		T8	44
valid_sources[0x10]	26588	1			T1	5		T2	2		T3	28
valid_sources[0x11]	26766	1			T3	26		T8	60		T7	3
valid_sources[0x12]	27469	1			T1	10		T2	2		T3	28
valid_sources[0x13]	27158	1			T3	26		T8	50		T7	3
valid_sources[0x14]	26973	1			T1	3		T2	5		T3	29
valid_sources[0x15]	26683	1			T3	29		T8	50		T7	1
valid_sources[0x16]	27113	1			T1	6		T3	25		T8	67
valid_sources[0x17]	27430	1			T1	1		T2	6		T3	34
valid_sources[0x18]	27699	1			T2	1		T3	35		T8	48
valid_sources[0x19]	27192	1			T3	28		T8	43		T7	6
valid_sources[0x1a]	27210	1			T2	1		T3	21		T8	47
valid_sources[0x1b]	27506	1			T2	1		T3	38		T8	45
valid_sources[0x1c]	27639	1			T2	1		T3	35		T8	50
valid_sources[0x1d]	27401	1			T2	2		T3	34		T8	34
valid_sources[0x1e]	26432	1			T1	1		T3	19		T8	63
valid_sources[0x1f]	26882	1			T3	19		T8	50		T7	3
valid_sources[0x20]	26512	1			T1	13		T3	26		T8	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24929

1

T1

3

T2

1

T3

16

values[0x0]

all_enables

biggest_size

187600

1

T1

19

T2

10

T3

171

values[0x1]

all_enables

biggest_size

25147

1

T1

3

T2

1

T3

22