Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync ( parameter Width=110,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=112,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )

Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[1].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[2].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_27.gen_dfifo[3].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[2].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_28.gen_host_fifo[2].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[2].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_29.gen_host_fifo[2].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.u_devicefifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.u_devicefifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[2].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_30.gen_host_fifo[2].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[2].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_31.gen_host_fifo[2].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[1].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[2].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[3].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[4].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[5].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[6].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[7].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[8].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[9].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[10].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[11].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[12].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[13].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[14].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[15].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[16].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[17].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[18].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[19].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[20].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[21].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[22].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_32.gen_dfifo[23].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_33.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_33.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_34.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_34.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_34.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_34.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.u_devicefifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.u_devicefifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_36.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.u_devicefifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.u_devicefifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_38.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.u_devicefifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.u_devicefifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_40.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.u_devicefifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.u_devicefifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_42.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_43.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_43.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_44.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_44.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_45.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_45.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_46.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_46.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_47.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_47.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_48.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_48.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_49.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_49.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_50.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_50.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_51.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_51.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_52.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_52.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_53.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_53.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_54.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_54.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_55.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_55.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_56.gen_host_fifo[0].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_56.gen_host_fifo[1].u_hostfifo.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_sm1_56.gen_host_fifo[1].u_hostfifo.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[1].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[2].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[2].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[3].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[3].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[4].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[4].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[5].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[6].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[7].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[8].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[9].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[10].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[11].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[12].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[12].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[13].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[13].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[14].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[14].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[15].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[15].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[16].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[16].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[17].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[17].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[18].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[18].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[19].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[20].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[21].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[22].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_s1n_57.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Line Coverage for Module self-instances :

SCORE	LINE
96.88	100.00

tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

Line Coverage for Module : prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_28.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_29.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_31.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_33.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_34.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_43.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_44.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_45.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_46.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_47.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_48.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_49.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_50.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_51.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_52.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_53.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_54.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_55.u_devicefifo.rspfifo

SCORE	LINE
93.75	100.00

tb.dut.u_sm1_56.u_devicefifo.rspfifo

SCORE	LINE
95.31	100.00

tb.dut.u_s1n_57.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Line Coverage for Module self-instances :

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_29.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_31.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_33.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_34.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_43.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_44.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_45.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_46.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_47.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_48.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_49.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_50.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_51.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_52.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_53.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_54.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_55.u_devicefifo.reqfifo

SCORE	LINE
95.31	100.00

tb.dut.u_sm1_56.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

Line Coverage for Module : prim_fifo_sync ( parameter Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.u_s1n_57.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

Cond Coverage for Module : prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.u_sm1_28.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_29.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_31.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_33.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_34.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_43.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_44.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_45.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_46.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_47.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_48.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_49.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_50.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_51.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_52.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_53.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_54.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_55.u_devicefifo.rspfifo

SCORE	COND
93.75	75.00

tb.dut.u_sm1_56.u_devicefifo.rspfifo

SCORE	COND
95.31	81.25

tb.dut.u_s1n_57.fifo_h.rspfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (65'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Cond Coverage for Module self-instances :

SCORE	COND
96.88	87.50

tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	24	21	87.50
Logical	24	21	87.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Cond Coverage for Module self-instances :

SCORE	COND
95.31	81.25

tb.dut.u_sm1_29.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_31.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_33.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_34.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_43.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_44.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_45.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_46.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_47.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_48.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_49.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_50.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_51.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_52.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_53.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_54.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_55.u_devicefifo.reqfifo

SCORE	COND
95.31	81.25

tb.dut.u_sm1_56.u_devicefifo.reqfifo

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (108'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.u_s1n_57.fifo_h.reqfifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (112'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Branch Coverage for Module self-instances :

SCORE	BRANCH
96.88	100.00

tb.dut.u_sm1_28.u_devicefifo.reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	2	2	100.00
IF	111	1	1	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Excluded	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )

Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_28.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_29.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_31.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_33.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_34.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_43.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_44.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_45.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_46.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_47.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_48.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_49.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_50.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_51.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_52.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_53.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_54.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_55.u_devicefifo.rspfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_sm1_56.u_devicefifo.rspfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_s1n_57.fifo_h.rspfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_29.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_31.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_33.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_34.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_43.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_44.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_45.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_46.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_47.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_48.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_49.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_50.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_51.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_52.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_53.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_54.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_55.u_devicefifo.reqfifo

SCORE	BRANCH
95.31	100.00

tb.dut.u_sm1_56.u_devicefifo.reqfifo

SCORE	BRANCH
93.75	100.00

tb.dut.u_s1n_57.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	1	1	100.00



	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Excluded	T1,T2,T3

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	1346131454	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	445771339	0	0
gen_passthru_fifo.paramCheckPass	199800	199800	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	1346131454
T1	97243920	495083
T2	65175382	631406
T3	56347030	4587207
T7	146546818	951556
T8	106636358	7617588
T9	75996768	459425
T10	115541214	650113
T11	75509448	568821
T12	771066	6414
T13	297632	3302
T14	0	112373
T15	0	1042
T16	0	334

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	97243920	97240514
T2	65175382	65159138
T3	56347030	56344934
T7	146546818	146524810
T8	106636358	106635834
T9	75996768	75979476
T10	115541214	115534664
T11	75509448	75487178
T12	771066	758752
T13	297632	281388

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	97243920	97240514
T2	65175382	65159138
T3	56347030	56344934
T7	146546818	146524810
T8	106636358	106635834
T9	75996768	75979476
T10	115541214	115534664
T11	75509448	75487178
T12	771066	758752
T13	297632	281388

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	97243920	97240514
T2	65175382	65159138
T3	56347030	56344934
T7	146546818	146524810
T8	106636358	106635834
T9	75996768	75979476
T10	115541214	115534664
T11	75509448	75487178
T12	771066	758752
T13	297632	281388

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	2147483647	445771339
T1	14846400	264332
T2	9950440	167734
T3	8602600	1431202
T7	22373560	418321
T8	16280360	1999357
T9	11602560	134458
T10	17639880	335702
T11	11528160	196453
T12	117720	1853
T13	45440	1016
T14	0	25904
T15	0	246

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	199800	199800
T1	222	222
T2	222	222
T3	222	222
T7	222	222
T8	222	222
T9	222	222
T10	222	222
T11	222	222
T12	222	222
T13	222	222