Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7369465	0	0
GntImpliesValid_A	2147483647	7369465	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7369465	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	433817766	0	0
ReadyAndValidImplyGrant_A	2147483647	7369465	0	0
ReqAndReadyImplyGrant_A	2147483647	7369465	0	0
ReqImpliesValid_A	2147483647	32647987	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42362	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7369465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8907840	8907528	0	0
T2	5970264	5968776	0	0
T3	5161560	5161368	0	0
T7	13424136	13422120	0	0
T8	9768216	9768168	0	0
T9	6961536	6959952	0	0
T10	10583928	10583328	0	0
T11	6916896	6914856	0	0
T12	70632	69504	0	0
T13	27264	25776	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8907840	8907528	0	0
T2	5970264	5968776	0	0
T3	5161560	5161368	0	0
T7	13424136	13422120	0	0
T8	9768216	9768168	0	0
T9	6961536	6959952	0	0
T10	10583928	10583328	0	0
T11	6916896	6914856	0	0
T12	70632	69504	0	0
T13	27264	25776	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8907840	8907528	0	0
T2	5970264	5968776	0	0
T3	5161560	5161368	0	0
T7	13424136	13422120	0	0
T8	9768216	9768168	0	0
T9	6961536	6959952	0	0
T10	10583928	10583328	0	0
T11	6916896	6914856	0	0
T12	70632	69504	0	0
T13	27264	25776	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	433817766	0	0
T1	8907840	486160	0	0
T2	5970264	208651	0	0
T3	5161560	198107	0	0
T7	13424136	696297	0	0
T8	9768216	365507	0	0
T9	6961536	243616	0	0
T10	10583928	557652	0	0
T11	6916896	242030	0	0
T12	70632	909	0	0
T13	27264	402	0	0
T14	0	505	0	0
T15	0	104	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32647987	0	0
T1	8907840	15929	0	0
T2	5970264	468	0	0
T3	5161560	12758	0	0
T7	13424136	32096	0	0
T8	9768216	22521	0	0
T9	6961536	812	0	0
T10	10583928	30033	0	0
T11	6916896	649	0	0
T12	70632	650	0	0
T13	27264	268	0	0
T14	0	263	0	0
T15	0	170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42362	0	21600
T7	559339	0	0	1
T8	407009	9	0	1
T9	290064	0	0	1
T10	440997	0	0	1
T11	288204	0	0	1
T12	2943	0	0	1
T13	1136	1	0	1
T14	243561	0	0	1
T15	2072	0	0	1
T16	9978	6	0	2
T17	16056	1	0	1
T18	61345	4	0	1
T19	4527	3	0	1
T20	3758	7	0	1
T21	9520	14	0	1
T22	14557	39	0	1
T23	0	2	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	68	0	0
T27	0	17	0	0
T28	1915	0	0	1
T29	20541	0	0	1
T30	305286	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8907840	8907528	0	0
T2	5970264	5968776	0	0
T3	5161560	5161368	0	0
T7	13424136	13422120	0	0
T8	9768216	9768168	0	0
T9	6961536	6959952	0	0
T10	10583928	10583328	0	0
T11	6916896	6914856	0	0
T12	70632	69504	0	0
T13	27264	25776	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7369465	0	0
T1	8907840	421	0	0
T2	5970264	325	0	0
T3	5161560	5275	0	0
T7	13424136	476	0	0
T8	9768216	9049	0	0
T9	6961536	476	0	0
T10	10583928	476	0	0
T11	6916896	413	0	0
T12	70632	558	0	0
T13	27264	240	0	0
T14	0	184	0	0
T15	0	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	816240	0	0
GntImpliesValid_A	400926921	816240	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	816240	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	11412548	0	0
ReadyAndValidImplyGrant_A	400926921	816240	0	0
ReqAndReadyImplyGrant_A	400926921	816240	0	0
ReqImpliesValid_A	400926921	2341528	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	816240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	11412548	0	0
T1	371160	20671	0	0
T2	248761	135	0	0
T3	215065	4020	0	0
T7	559339	18967	0	0
T8	407009	7241	0	0
T9	290064	250	0	0
T10	440997	21115	0	0
T11	288204	217	0	0
T12	2943	46	0	0
T13	1136	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2341528	0	0
T1	371160	1333	0	0
T2	248761	32	0	0
T3	215065	2299	0	0
T7	559339	3245	0	0
T8	407009	4479	0	0
T9	290064	63	0	0
T10	440997	1202	0	0
T11	288204	70	0	0
T12	2943	75	0	0
T13	1136	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	816240	0	0
T1	371160	57	0	0
T2	248761	32	0	0
T3	215065	1106	0	0
T7	559339	61	0	0
T8	407009	2103	0	0
T9	290064	54	0	0
T10	440997	56	0	0
T11	288204	51	0	0
T12	2943	60	0	0
T13	1136	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	825694	0	0
GntImpliesValid_A	400926921	825694	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	825694	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	11413852	0	0
ReadyAndValidImplyGrant_A	400926921	825694	0	0
ReqAndReadyImplyGrant_A	400926921	825694	0	0
ReqImpliesValid_A	400926921	2370841	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	825694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	11413852	0	0
T1	371160	18567	0	0
T2	248761	134	0	0
T3	215065	1643	0	0
T7	559339	19746	0	0
T8	407009	2092	0	0
T9	290064	202	0	0
T10	440997	19208	0	0
T11	288204	192	0	0
T12	2943	50	0	0
T13	1136	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2370841	0	0
T1	371160	521	0	0
T2	248761	40	0	0
T3	215065	616	0	0
T7	559339	1526	0	0
T8	407009	677	0	0
T9	290064	82	0	0
T10	440997	3348	0	0
T11	288204	50	0	0
T12	2943	77	0	0
T13	1136	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	825694	0	0
T1	371160	46	0	0
T2	248761	36	0	0
T3	215065	409	0	0
T7	559339	61	0	0
T8	407009	516	0	0
T9	290064	48	0	0
T10	440997	57	0	0
T11	288204	46	0	0
T12	2943	63	0	0
T13	1136	27	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T15
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T12,T15

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T11,T12,T15
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	204506	0	0
GntImpliesValid_A	400926921	204506	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	204506	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2894380	0	0
ReadyAndValidImplyGrant_A	400926921	204506	0	0
ReqAndReadyImplyGrant_A	400926921	204506	0	0
ReqImpliesValid_A	400926921	560759	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	204506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2894380	0	0
T1	371160	4253	0	0
T2	248761	13	0	0
T3	215065	1	0	0
T7	559339	4099	0	0
T8	407009	1	0	0
T9	290064	52	0	0
T10	440997	5390	0	0
T11	288204	66	0	0
T12	2943	13	0	0
T13	1136	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	560759	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	24	0	0
T12	2943	16	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	204506	0	0
T1	371160	13	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	13	0	0
T10	440997	19	0	0
T11	288204	15	0	0
T12	2943	14	0	0
T13	1136	5	0	0
T14	0	9	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	216473	0	0
GntImpliesValid_A	400926921	216473	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	216473	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2858190	0	0
ReadyAndValidImplyGrant_A	400926921	216473	0	0
ReqAndReadyImplyGrant_A	400926921	216473	0	0
ReqImpliesValid_A	400926921	609342	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	216473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2858190	0	0
T1	371160	2865	0	0
T2	248761	41	0	0
T3	215065	3332	0	0
T7	559339	2162	0	0
T8	407009	1	0	0
T9	290064	74	0	0
T10	440997	2632	0	0
T11	288204	66	0	0
T12	2943	10	0	0
T13	1136	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	609342	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	2278	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	25	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	12	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	216473	0	0
T1	371160	10	0	0
T2	248761	9	0	0
T3	215065	964	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	17	0	0
T10	440997	12	0	0
T11	288204	11	0	0
T12	2943	9	0	0
T13	1136	11	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T13
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	194891	0	0
GntImpliesValid_A	400926921	194891	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	194891	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	4534747	0	0
ReadyAndValidImplyGrant_A	400926921	194891	0	0
ReqAndReadyImplyGrant_A	400926921	194891	0	0
ReqImpliesValid_A	400926921	1065840	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	194891	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	4534747	0	0
T1	371160	1332	0	0
T2	248761	74	0	0
T3	215065	3649	0	0
T7	559339	4196	0	0
T8	407009	0	0	0
T9	290064	181	0	0
T10	440997	3579	0	0
T11	288204	272	0	0
T12	2943	58	0	0
T13	1136	29	0	0
T14	0	152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	1065840	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	1901	0	0
T7	559339	630	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	12	0	0
T14	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194891	0	0
T1	371160	14	0	0
T2	248761	4	0	0
T3	215065	480	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	12	0	0
T11	288204	15	0	0
T12	2943	10	0	0
T13	1136	5	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T12
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T7,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T7,T9,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	198584	0	0
GntImpliesValid_A	400926921	198584	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	198584	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	4272929	0	0
ReadyAndValidImplyGrant_A	400926921	198584	0	0
ReqAndReadyImplyGrant_A	400926921	198584	0	0
ReqImpliesValid_A	400926921	1020936	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	198584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	4272929	0	0
T1	371160	599	0	0
T2	248761	139	0	0
T3	215065	0	0	0
T7	559339	2487	0	0
T8	407009	0	0	0
T9	290064	164	0	0
T10	440997	1727	0	0
T11	288204	105	0	0
T12	2943	86	0	0
T13	1136	54	0	0
T14	0	70	0	0
T15	0	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	1020936	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	131	0	0
T8	407009	0	0	0
T9	290064	29	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	18	0	0
T13	1136	5	0	0
T14	0	23	0	0
T15	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198584	0	0
T1	371160	7	0	0
T2	248761	16	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	13	0	0
T11	288204	13	0	0
T12	2943	12	0	0
T13	1136	5	0	0
T14	0	12	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T11
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Not Covered
1	1	Covered	T8,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T8,T9,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	202884	0	0
GntImpliesValid_A	400926921	202884	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	202884	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	4537008	0	0
ReadyAndValidImplyGrant_A	400926921	202884	0	0
ReqAndReadyImplyGrant_A	400926921	202884	0	0
ReqImpliesValid_A	400926921	1107380	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	202884	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	4537008	0	0
T1	371160	1810	0	0
T2	248761	71	0	0
T3	215065	0	0	0
T7	559339	8167	0	0
T8	407009	1898	0	0
T9	290064	174	0	0
T10	440997	1664	0	0
T11	288204	121	0	0
T12	2943	137	0	0
T13	1136	35	0	0
T14	0	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	1107380	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	1212	0	0
T9	290064	20	0	0
T10	440997	11	0	0
T11	288204	34	0	0
T12	2943	52	0	0
T13	1136	3	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	202884	0	0
T1	371160	7	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	14	0	0
T8	407009	462	0	0
T9	290064	11	0	0
T10	440997	11	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	3	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	198248	0	0
GntImpliesValid_A	400926921	198248	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	198248	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	5052457	0	0
ReadyAndValidImplyGrant_A	400926921	198248	0	0
ReqAndReadyImplyGrant_A	400926921	198248	0	0
ReqImpliesValid_A	400926921	1203832	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	198248	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	5052457	0	0
T1	371160	1046	0	0
T2	248761	89	0	0
T3	215065	0	0	0
T7	559339	36048	0	0
T8	407009	0	0	0
T9	290064	191	0	0
T10	440997	1124	0	0
T11	288204	252	0	0
T12	2943	264	0	0
T13	1136	93	0	0
T14	0	238	0	0
T15	0	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	1203832	0	0
T1	371160	12	0	0
T2	248761	19	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	35	0	0
T10	440997	59	0	0
T11	288204	11	0	0
T12	2943	32	0	0
T13	1136	15	0	0
T14	0	7	0	0
T15	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198248	0	0
T1	371160	12	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	11	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	7	0	0
T14	0	7	0	0
T15	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	211778	0	0
GntImpliesValid_A	400926921	211778	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	211778	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2885253	0	0
ReadyAndValidImplyGrant_A	400926921	211778	0	0
ReqAndReadyImplyGrant_A	400926921	211778	0	0
ReqImpliesValid_A	400926921	587631	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	211778	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2885253	0	0
T1	371160	4992	0	0
T2	248761	55	0	0
T3	215065	1	0	0
T7	559339	3025	0	0
T8	407009	3592	0	0
T9	290064	32	0	0
T10	440997	5626	0	0
T11	288204	37	0	0
T12	2943	22	0	0
T13	1136	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	587631	0	0
T1	371160	370	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	190	0	0
T8	407009	2462	0	0
T9	290064	9	0	0
T10	440997	15	0	0
T11	288204	12	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	211778	0	0
T1	371160	17	0	0
T2	248761	11	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	1077	0	0
T9	290064	8	0	0
T10	440997	15	0	0
T11	288204	8	0	0
T12	2943	21	0	0
T13	1136	11	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T7
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	203425	0	0
GntImpliesValid_A	400926921	203425	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	203425	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2820023	0	0
ReadyAndValidImplyGrant_A	400926921	203425	0	0
ReqAndReadyImplyGrant_A	400926921	203425	0	0
ReqImpliesValid_A	400926921	525261	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	203425	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2820023	0	0
T1	371160	6189	0	0
T2	248761	42	0	0
T3	215065	1	0	0
T7	559339	3702	0	0
T8	407009	1859	0	0
T9	290064	69	0	0
T10	440997	3824	0	0
T11	288204	86	0	0
T12	2943	17	0	0
T13	1136	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	525261	0	0
T1	371160	170	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	512	0	0
T8	407009	1327	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	29	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	203425	0	0
T1	371160	15	0	0
T2	248761	10	0	0
T3	215065	0	0	0
T7	559339	12	0	0
T8	407009	528	0	0
T9	290064	17	0	0
T10	440997	8	0	0
T11	288204	16	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T15,T16
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T15,T16

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T12,T15,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	200678	0	0
GntImpliesValid_A	400926921	200678	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	200678	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2860114	0	0
ReadyAndValidImplyGrant_A	400926921	200678	0	0
ReqAndReadyImplyGrant_A	400926921	200678	0	0
ReqImpliesValid_A	400926921	533236	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	200678	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2860114	0	0
T1	371160	3937	0	0
T2	248761	33	0	0
T3	215065	1	0	0
T7	559339	5389	0	0
T8	407009	1	0	0
T9	290064	21	0	0
T10	440997	5321	0	0
T11	288204	26	0	0
T12	2943	15	0	0
T13	1136	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	533236	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	16	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200678	0	0
T1	371160	11	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	15	0	0
T8	407009	0	0	0
T9	290064	6	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	8	0	0
T15	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	198076	0	0
GntImpliesValid_A	400926921	198076	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	198076	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2812651	0	0
ReadyAndValidImplyGrant_A	400926921	198076	0	0
ReqAndReadyImplyGrant_A	400926921	198076	0	0
ReqImpliesValid_A	400926921	522025	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	198076	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2812651	0	0
T1	371160	1987	0	0
T2	248761	37	0	0
T3	215065	1	0	0
T7	559339	3052	0	0
T8	407009	1	0	0
T9	290064	42	0	0
T10	440997	8479	0	0
T11	288204	88	0	0
T12	2943	20	0	0
T13	1136	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	522025	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	457	0	0
T8	407009	0	0	0
T9	290064	9	0	0
T10	440997	474	0	0
T11	288204	14	0	0
T12	2943	21	0	0
T13	1136	5	0	0
T14	0	29	0	0
T15	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	198076	0	0
T1	371160	8	0	0
T2	248761	8	0	0
T3	215065	0	0	0
T7	559339	13	0	0
T8	407009	0	0	0
T9	290064	8	0	0
T10	440997	19	0	0
T11	288204	14	0	0
T12	2943	20	0	0
T13	1136	5	0	0
T14	0	11	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	200742	0	0
GntImpliesValid_A	400926921	200742	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	200742	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2846085	0	0
ReadyAndValidImplyGrant_A	400926921	200742	0	0
ReqAndReadyImplyGrant_A	400926921	200742	0	0
ReqImpliesValid_A	400926921	547795	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	200742	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2846085	0	0
T1	371160	4229	0	0
T2	248761	39	0	0
T3	215065	1610	0	0
T7	559339	3648	0	0
T8	407009	3771	0	0
T9	290064	45	0	0
T10	440997	4690	0	0
T11	288204	32	0	0
T12	2943	16	0	0
T13	1136	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	547795	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	1166	0	0
T7	559339	10	0	0
T8	407009	2460	0	0
T9	290064	10	0	0
T10	440997	166	0	0
T11	288204	17	0	0
T12	2943	15	0	0
T13	1136	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	200742	0	0
T1	371160	12	0	0
T2	248761	9	0	0
T3	215065	493	0	0
T7	559339	10	0	0
T8	407009	1121	0	0
T9	290064	10	0	0
T10	440997	13	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T12,T14
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T12,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T9,T12,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	201570	0	0
GntImpliesValid_A	400926921	201570	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	201570	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2807716	0	0
ReadyAndValidImplyGrant_A	400926921	201570	0	0
ReqAndReadyImplyGrant_A	400926921	201570	0	0
ReqImpliesValid_A	400926921	551917	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	201570	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2807716	0	0
T1	371160	1285	0	0
T2	248761	66	0	0
T3	215065	1	0	0
T7	559339	3491	0	0
T8	407009	1	0	0
T9	290064	53	0	0
T10	440997	6146	0	0
T11	288204	42	0	0
T12	2943	16	0	0
T13	1136	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	551917	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	16	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	19	0	0
T13	1136	7	0	0
T14	0	13	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	201570	0	0
T1	371160	8	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	9	0	0
T8	407009	0	0	0
T9	290064	11	0	0
T10	440997	15	0	0
T11	288204	11	0	0
T12	2943	17	0	0
T13	1136	7	0	0
T14	0	8	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T14

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T12,T14
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	196606	0	0
GntImpliesValid_A	400926921	196606	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	196606	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2778713	0	0
ReadyAndValidImplyGrant_A	400926921	196606	0	0
ReqAndReadyImplyGrant_A	400926921	196606	0	0
ReqImpliesValid_A	400926921	535832	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	196606	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2778713	0	0
T1	371160	2709	0	0
T2	248761	38	0	0
T3	215065	1	0	0
T7	559339	3432	0	0
T8	407009	1	0	0
T9	290064	45	0	0
T10	440997	4513	0	0
T11	288204	55	0	0
T12	2943	13	0	0
T13	1136	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	535832	0	0
T1	371160	137	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	16	0	0
T13	1136	8	0	0
T14	0	17	0	0
T15	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	196606	0	0
T1	371160	12	0	0
T2	248761	7	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	12	0	0
T10	440997	12	0	0
T11	288204	10	0	0
T12	2943	14	0	0
T13	1136	8	0	0
T14	0	14	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T7,T9
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T8,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	206818	0	0
GntImpliesValid_A	400926921	206818	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	206818	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2875647	0	0
ReadyAndValidImplyGrant_A	400926921	206818	0	0
ReqAndReadyImplyGrant_A	400926921	206818	0	0
ReqImpliesValid_A	400926921	578435	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	206818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2875647	0	0
T1	371160	3909	0	0
T2	248761	20	0	0
T3	215065	1	0	0
T7	559339	3034	0	0
T8	407009	1628	0	0
T9	290064	54	0	0
T10	440997	3395	0	0
T11	288204	42	0	0
T12	2943	18	0	0
T13	1136	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	578435	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	490	0	0
T8	407009	1154	0	0
T9	290064	29	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	19	0	0
T13	1136	11	0	0
T14	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	206818	0	0
T1	371160	9	0	0
T2	248761	5	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	490	0	0
T9	290064	16	0	0
T10	440997	10	0	0
T11	288204	11	0	0
T12	2943	18	0	0
T13	1136	11	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	224512	0	0
GntImpliesValid_A	400926921	224512	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	224512	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2897336	0	0
ReadyAndValidImplyGrant_A	400926921	224512	0	0
ReqAndReadyImplyGrant_A	400926921	224512	0	0
ReqImpliesValid_A	400926921	571283	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	224512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2897336	0	0
T1	371160	6974	0	0
T2	248761	36	0	0
T3	215065	1739	0	0
T7	559339	3707	0	0
T8	407009	3096	0	0
T9	290064	38	0	0
T10	440997	3304	0	0
T11	288204	25	0	0
T12	2943	19	0	0
T13	1136	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	571283	0	0
T1	371160	37	0	0
T2	248761	12	0	0
T3	215065	1230	0	0
T7	559339	381	0	0
T8	407009	2279	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	13	0	0
T12	2943	22	0	0
T13	1136	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	224512	0	0
T1	371160	20	0	0
T2	248761	12	0	0
T3	215065	538	0	0
T7	559339	12	0	0
T8	407009	956	0	0
T9	290064	9	0	0
T10	440997	8	0	0
T11	288204	7	0	0
T12	2943	20	0	0
T13	1136	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	192924	0	0
GntImpliesValid_A	400926921	192924	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	192924	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2878245	0	0
ReadyAndValidImplyGrant_A	400926921	192924	0	0
ReqAndReadyImplyGrant_A	400926921	192924	0	0
ReqImpliesValid_A	400926921	508794	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	192924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2878245	0	0
T1	371160	6650	0	0
T2	248761	31	0	0
T3	215065	1	0	0
T7	559339	3485	0	0
T8	407009	1	0	0
T9	290064	54	0	0
T10	440997	3136	0	0
T11	288204	25	0	0
T12	2943	14	0	0
T13	1136	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	508794	0	0
T1	371160	331	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	321	0	0
T8	407009	0	0	0
T9	290064	20	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	192924	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	9	0	0
T11	288204	5	0	0
T12	2943	13	0	0
T13	1136	9	0	0
T14	0	8	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	213975	0	0
GntImpliesValid_A	400926921	213975	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	213975	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2913639	0	0
ReadyAndValidImplyGrant_A	400926921	213975	0	0
ReqAndReadyImplyGrant_A	400926921	213975	0	0
ReqImpliesValid_A	400926921	615270	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	213975	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2913639	0	0
T1	371160	3405	0	0
T2	248761	26	0	0
T3	215065	1841	0	0
T7	559339	3600	0	0
T8	407009	1	0	0
T9	290064	56	0	0
T10	440997	4406	0	0
T11	288204	86	0	0
T12	2943	17	0	0
T13	1136	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	615270	0	0
T1	371160	367	0	0
T2	248761	6	0	0
T3	215065	1203	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	18	0	0
T10	440997	219	0	0
T11	288204	16	0	0
T12	2943	18	0	0
T13	1136	8	0	0
T14	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	213975	0	0
T1	371160	10	0	0
T2	248761	6	0	0
T3	215065	539	0	0
T7	559339	10	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	13	0	0
T11	288204	16	0	0
T12	2943	17	0	0
T13	1136	8	0	0
T14	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T12
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T9,T10,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	208090	0	0
GntImpliesValid_A	400926921	208090	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	208090	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2872665	0	0
ReadyAndValidImplyGrant_A	400926921	208090	0	0
ReqAndReadyImplyGrant_A	400926921	208090	0	0
ReqImpliesValid_A	400926921	550080	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	208090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2872665	0	0
T1	371160	5407	0	0
T2	248761	36	0	0
T3	215065	1	0	0
T7	559339	2338	0	0
T8	407009	1	0	0
T9	290064	52	0	0
T10	440997	2701	0	0
T11	288204	65	0	0
T12	2943	24	0	0
T13	1136	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	550080	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	20	0	0
T10	440997	51	0	0
T11	288204	12	0	0
T12	2943	25	0	0
T13	1136	6	0	0
T14	0	8	0	0
T15	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	208090	0	0
T1	371160	16	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	7	0	0
T8	407009	0	0	0
T9	290064	15	0	0
T10	440997	10	0	0
T11	288204	12	0	0
T12	2943	24	0	0
T13	1136	6	0	0
T14	0	7	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	194951	0	0
GntImpliesValid_A	400926921	194951	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	194951	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2861963	0	0
ReadyAndValidImplyGrant_A	400926921	194951	0	0
ReqAndReadyImplyGrant_A	400926921	194951	0	0
ReqImpliesValid_A	400926921	525054	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	194951	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2861963	0	0
T1	371160	5396	0	0
T2	248761	60	0	0
T3	215065	1	0	0
T7	559339	3741	0	0
T8	407009	1	0	0
T9	290064	82	0	0
T10	440997	5094	0	0
T11	288204	49	0	0
T12	2943	16	0	0
T13	1136	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	525054	0	0
T1	371160	133	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	41	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	19	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	20	0	0
T15	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	194951	0	0
T1	371160	18	0	0
T2	248761	9	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	14	0	0
T11	288204	10	0	0
T12	2943	15	0	0
T13	1136	5	0	0
T14	0	10	0	0
T15	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T11,T13
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T11,T13

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T11,T13
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	209311	0	0
GntImpliesValid_A	400926921	209311	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	209311	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	2858321	0	0
ReadyAndValidImplyGrant_A	400926921	209311	0	0
ReqAndReadyImplyGrant_A	400926921	209311	0	0
ReqImpliesValid_A	400926921	610572	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	0	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	209311	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2858321	0	0
T1	371160	3075	0	0
T2	248761	39	0	0
T3	215065	1	0	0
T7	559339	2996	0	0
T8	407009	1	0	0
T9	290064	66	0	0
T10	440997	3918	0	0
T11	288204	39	0	0
T12	2943	16	0	0
T13	1136	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	610572	0	0
T1	371160	362	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	12	0	0
T12	2943	15	0	0
T13	1136	13	0	0
T14	0	6	0	0
T15	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	209311	0	0
T1	371160	12	0	0
T2	248761	12	0	0
T3	215065	0	0	0
T7	559339	11	0	0
T8	407009	0	0	0
T9	290064	14	0	0
T10	440997	12	0	0
T11	288204	9	0	0
T12	2943	15	0	0
T13	1136	12	0	0
T14	0	6	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	833968	0	0
GntImpliesValid_A	400926921	833968	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	833968	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	10748631	0	0
ReadyAndValidImplyGrant_A	400926921	833968	0	0
ReqAndReadyImplyGrant_A	400926921	833968	0	0
ReqImpliesValid_A	400926921	2256550	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	15565	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	833968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	10748631	0	0
T1	371160	15846	0	0
T2	248761	139	0	0
T3	215065	1202	0	0
T7	559339	22521	0	0
T8	407009	1617	0	0
T9	290064	215	0	0
T10	440997	19903	0	0
T11	288204	131	0	0
T12	2943	1	0	0
T13	1136	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	2256550	0	0
T1	371160	662	0	0
T2	248761	53	0	0
T3	215065	493	0	0
T7	559339	3297	0	0
T8	407009	678	0	0
T9	290064	83	0	0
T10	440997	949	0	0
T11	288204	49	0	0
T12	2943	54	0	0
T13	1136	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	15565	0	900
T16	4989	3	0	1
T17	16056	0	0	1
T18	61345	0	0	1
T19	4527	2	0	1
T20	3758	3	0	1
T21	9520	9	0	1
T22	14557	16	0	1
T23	0	1	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	68	0	0
T27	0	17	0	0
T28	1915	0	0	1
T29	20541	0	0	1
T30	305286	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	833968	0	0
T1	371160	41	0	0
T2	248761	42	0	0
T3	215065	379	0	0
T7	559339	71	0	0
T8	407009	508	0	0
T9	290064	61	0	0
T10	440997	54	0	0
T11	288204	43	0	0
T12	2943	54	0	0
T13	1136	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400926921	400793624	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	400926921	814521	0	0
GntImpliesValid_A	400926921	814521	0	0
GrantKnown_A	400926921	400793624	0	0
IdxKnown_A	400926921	400793624	0	0
IndexIsCorrect_A	400926921	814521	0	0
LockArbDecision_A	400926921	0	0	0
NoReadyValidNoGrant_A	400926921	336124653	0	0
ReadyAndValidImplyGrant_A	400926921	814521	0	0
ReqAndReadyImplyGrant_A	400926921	814521	0	0
ReqImpliesValid_A	400926921	12347794	0	0
ReqStaysHighUntilGranted0_M	400926921	0	0	0
RoundRobin_A	400926921	26797	0	900
ValidKnown_A	400926921	400793624	0	0
gen_data_port_assertion.DataFlow_A	400926921	814521	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	336124653	0	0
T1	371160	359027	0	0
T2	248761	207258	0	0
T3	215065	179059	0	0
T7	559339	529264	0	0
T8	407009	338702	0	0
T9	290064	241404	0	0
T10	440997	416757	0	0
T11	288204	239911	0	0
T12	2943	1	0	0
T13	1136	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	12347794	0	0
T1	371160	11379	0	0
T2	248761	155	0	0
T3	215065	1572	0	0
T7	559339	20760	0	0
T8	407009	5793	0	0
T9	290064	243	0	0
T10	440997	23378	0	0
T11	288204	189	0	0
T12	2943	56	0	0
T13	1136	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	26797	0	900
T7	559339	0	0	1
T8	407009	9	0	1
T9	290064	0	0	1
T10	440997	0	0	1
T11	288204	0	0	1
T12	2943	0	0	1
T13	1136	1	0	1
T14	243561	0	0	1
T15	2072	0	0	1
T16	4989	3	0	1
T17	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	0	5	0	0
T22	0	23	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	400793624	0	0
T1	371160	371147	0	0
T2	248761	248699	0	0
T3	215065	215057	0	0
T7	559339	559255	0	0
T8	407009	407007	0	0
T9	290064	289998	0	0
T10	440997	440972	0	0
T11	288204	288119	0	0
T12	2943	2896	0	0
T13	1136	1074	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400926921	814521	0	0
T1	371160	30	0	0
T2	248761	36	0	0
T3	215065	367	0	0
T7	559339	64	0	0
T8	407009	1288	0	0
T9	290064	61	0	0
T10	440997	61	0	0
T11	288204	47	0	0
T12	2943	56	0	0
T13	1136	19	0	0