Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1495071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

237355

1

T1

2

T2

17

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588589	1			T1	26		T2	40		T3	29
values[0x0]	555313	1			T1	3		T2	36		T3	29
values[0x1]	588524	1			T1	26		T2	43		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1154857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

577569

1

T1

20

T2

44

T3

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27413	1			T1	6		T2	1		T7	3
valid_sources[0x01]	28219	1			T7	4		T8	57		T10	44
valid_sources[0x02]	27429	1			T1	1		T2	3		T3	16
valid_sources[0x03]	27170	1			T1	1		T2	4		T7	1
valid_sources[0x04]	26970	1			T1	1		T7	2		T9	2
valid_sources[0x05]	27036	1			T1	1		T2	6		T9	1
valid_sources[0x06]	26897	1			T1	2		T7	4		T8	41
valid_sources[0x07]	26880	1			T7	1		T9	1		T8	39
valid_sources[0x08]	26913	1			T1	2		T3	8		T9	2
valid_sources[0x09]	26378	1			T2	2		T7	2		T9	2
valid_sources[0x0a]	26697	1			T9	2		T8	45		T10	41
valid_sources[0x0b]	27384	1			T1	1		T9	1		T8	42
valid_sources[0x0c]	26490	1			T7	1		T9	2		T8	50
valid_sources[0x0d]	26648	1			T1	1		T7	1		T8	51
valid_sources[0x0e]	27121	1			T1	1		T7	3		T9	2
valid_sources[0x0f]	27115	1			T1	1		T2	1		T7	2
valid_sources[0x10]	27747	1			T1	2		T9	4		T8	51
valid_sources[0x11]	27548	1			T1	1		T2	1		T9	2
valid_sources[0x12]	27224	1			T2	3		T3	16		T7	3
valid_sources[0x13]	28338	1			T1	1		T2	4		T7	1
valid_sources[0x14]	26985	1			T8	41		T10	49		T11	77
valid_sources[0x15]	26399	1			T3	2		T7	5		T9	1
valid_sources[0x16]	26700	1			T1	1		T2	1		T9	1
valid_sources[0x17]	27150	1			T1	1		T7	2		T9	1
valid_sources[0x18]	27967	1			T7	3		T9	2		T8	47
valid_sources[0x19]	26973	1			T1	2		T3	6		T7	4
valid_sources[0x1a]	26385	1			T2	1		T9	2		T8	42
valid_sources[0x1b]	27044	1			T2	1		T7	1		T9	2
valid_sources[0x1c]	27510	1			T1	2		T3	2		T8	30
valid_sources[0x1d]	28128	1			T1	1		T7	1		T9	1
valid_sources[0x1e]	27658	1			T3	3		T9	4		T8	48
valid_sources[0x1f]	27284	1			T2	3		T7	3		T9	2
valid_sources[0x20]	25951	1			T7	2		T8	51		T10	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25082

1

T1

1

T9

4

T8

47

values[0x0]

all_enables

biggest_size

187210

1

T2

16

T3

9

T7

16

values[0x1]

all_enables

biggest_size

25063

1

T1

1

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1512218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245585

1

T1

7

T2

35

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	602028	1			T1	40		T2	63		T3	45
values[0x0]	553234	1			T1	2		T2	68		T3	44
values[0x1]	602541	1			T1	21		T2	56		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1160265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

597538

1

T1

28

T2

68

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27368	1			T2	6		T3	4		T9	6
valid_sources[0x01]	27311	1			T2	2		T3	3		T9	6
valid_sources[0x02]	28022	1			T2	1		T3	4		T8	46
valid_sources[0x03]	28322	1			T1	1		T3	2		T8	43
valid_sources[0x04]	27718	1			T1	1		T2	3		T3	1
valid_sources[0x05]	26929	1			T1	1		T2	3		T3	3
valid_sources[0x06]	27596	1			T1	2		T2	2		T3	3
valid_sources[0x07]	27194	1			T1	2		T2	3		T3	4
valid_sources[0x08]	27330	1			T1	1		T2	1		T9	1
valid_sources[0x09]	27434	1			T1	2		T2	4		T3	3
valid_sources[0x0a]	27042	1			T2	4		T3	3		T9	1
valid_sources[0x0b]	27311	1			T2	3		T3	2		T7	1
valid_sources[0x0c]	26979	1			T1	1		T2	12		T3	8
valid_sources[0x0d]	26832	1			T1	2		T2	1		T3	1
valid_sources[0x0e]	27921	1			T1	1		T2	2		T3	3
valid_sources[0x0f]	27099	1			T1	1		T2	1		T7	11
valid_sources[0x10]	27796	1			T1	2		T2	9		T3	2
valid_sources[0x11]	27601	1			T1	1		T2	4		T3	3
valid_sources[0x12]	27705	1			T1	3		T2	10		T3	3
valid_sources[0x13]	26978	1			T2	2		T8	46		T10	23
valid_sources[0x14]	27356	1			T1	1		T2	5		T3	2
valid_sources[0x15]	26556	1			T2	1		T8	35		T10	38
valid_sources[0x16]	27225	1			T1	1		T2	1		T3	1
valid_sources[0x17]	27608	1			T1	1		T2	1		T3	1
valid_sources[0x18]	28205	1			T1	1		T2	5		T3	3
valid_sources[0x19]	26801	1			T1	1		T2	1		T3	4
valid_sources[0x1a]	27811	1			T1	3		T3	5		T9	1
valid_sources[0x1b]	27329	1			T1	2		T8	51		T10	35
valid_sources[0x1c]	27553	1			T1	1		T2	6		T7	7
valid_sources[0x1d]	28144	1			T1	1		T2	6		T3	2
valid_sources[0x1e]	27375	1			T3	3		T9	1		T8	47
valid_sources[0x1f]	26851	1			T1	1		T2	1		T7	3
valid_sources[0x20]	27957	1			T7	3		T8	48		T10	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25813

1

T1

3

T2

3

T7

3

values[0x0]

all_enables

biggest_size

193872

1

T1

1

T2

29

T3

15

values[0x1]

all_enables

biggest_size

25900

1

T1

3

T2

3

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1504132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239197

1

T1

7

T2

19

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	592636	1			T1	17		T2	47		T3	62
values[0x0]	559332	1			T1	6		T2	69		T3	68
values[0x1]	591361	1			T1	33		T2	53		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1162369	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

580960

1

T1

21

T2

49

T3

69

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27043	1			T2	3		T3	1		T7	1
valid_sources[0x01]	27888	1			T1	1		T2	1		T3	4
valid_sources[0x02]	27320	1			T1	2		T2	2		T3	4
valid_sources[0x03]	26890	1			T1	1		T2	2		T3	1
valid_sources[0x04]	26525	1			T2	7		T3	4		T7	4
valid_sources[0x05]	27354	1			T1	2		T2	4		T3	1
valid_sources[0x06]	27576	1			T2	8		T3	1		T9	1
valid_sources[0x07]	27215	1			T1	2		T2	2		T3	5
valid_sources[0x08]	27395	1			T1	1		T2	1		T3	2
valid_sources[0x09]	27285	1			T2	2		T3	1		T7	7
valid_sources[0x0a]	26740	1			T1	2		T2	5		T3	2
valid_sources[0x0b]	26484	1			T2	6		T3	4		T7	1
valid_sources[0x0c]	26525	1			T1	3		T2	1		T3	2
valid_sources[0x0d]	26637	1			T2	3		T3	2		T7	3
valid_sources[0x0e]	28334	1			T1	2		T2	1		T3	3
valid_sources[0x0f]	27052	1			T1	1		T2	1		T3	3
valid_sources[0x10]	27643	1			T2	1		T3	2		T7	3
valid_sources[0x11]	27497	1			T1	1		T3	1		T7	1
valid_sources[0x12]	28340	1			T2	2		T3	4		T7	4
valid_sources[0x13]	27244	1			T1	1		T2	5		T3	1
valid_sources[0x14]	26968	1			T2	1		T3	2		T7	1
valid_sources[0x15]	26560	1			T1	1		T2	3		T3	1
valid_sources[0x16]	27424	1			T1	1		T2	3		T3	3
valid_sources[0x17]	27908	1			T1	1		T3	3		T7	4
valid_sources[0x18]	27237	1			T1	6		T3	2		T7	2
valid_sources[0x19]	27459	1			T1	2		T2	6		T3	3
valid_sources[0x1a]	26966	1			T1	3		T2	7		T3	2
valid_sources[0x1b]	27492	1			T2	4		T3	3		T7	4
valid_sources[0x1c]	26980	1			T1	2		T2	2		T7	1
valid_sources[0x1d]	27834	1			T2	2		T3	2		T7	2
valid_sources[0x1e]	27521	1			T2	1		T3	4		T7	1
valid_sources[0x1f]	26405	1			T2	3		T3	3		T7	3
valid_sources[0x20]	27315	1			T3	5		T7	3		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25380

1

T1

1

T2

2

T3

3

values[0x0]

all_enables

biggest_size

188796

1

T1

2

T2

12

T3

29

values[0x1]

all_enables

biggest_size

25021

1

T1

4

T2

5

T3

3