Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7609281	0	0
GntImpliesValid_A	2147483647	7609281	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7609281	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	441420052	0	0
ReadyAndValidImplyGrant_A	2147483647	7609281	0	0
ReqAndReadyImplyGrant_A	2147483647	7609281	0	0
ReqImpliesValid_A	2147483647	32672347	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40909	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7609281	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	110784	109824	0	0
T2	55944	55104	0	0
T3	6748584	6747768	0	0
T7	285024	281808	0	0
T8	2381880	2380848	0	0
T9	189216	188448	0	0
T10	440688	439416	0	0
T11	2054376	2029608	0	0
T12	957264	954552	0	0
T13	1795056	1794576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	110784	109824	0	0
T2	55944	55104	0	0
T3	6748584	6747768	0	0
T7	285024	281808	0	0
T8	2381880	2380848	0	0
T9	189216	188448	0	0
T10	440688	439416	0	0
T11	2054376	2029608	0	0
T12	957264	954552	0	0
T13	1795056	1794576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	110784	109824	0	0
T2	55944	55104	0	0
T3	6748584	6747768	0	0
T7	285024	281808	0	0
T8	2381880	2380848	0	0
T9	189216	188448	0	0
T10	440688	439416	0	0
T11	2054376	2029608	0	0
T12	957264	954552	0	0
T13	1795056	1794576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	441420052	0	0
T1	110784	2171	0	0
T2	55944	711	0	0
T3	6748584	235987	0	0
T7	285024	13580	0	0
T8	2381880	110497	0	0
T9	189216	4372	0	0
T10	440688	14167	0	0
T11	2054376	126356	0	0
T12	957264	22834	0	0
T13	1795056	112112	0	0
T14	0	31020	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32672347	0	0
T1	110784	2086	0	0
T2	55944	561	0	0
T3	6748584	672	0	0
T7	285024	1026	0	0
T8	2381880	78521	0	0
T9	189216	3016	0	0
T10	440688	11033	0	0
T11	2054376	22355	0	0
T12	957264	25009	0	0
T13	1795056	18034	0	0
T14	0	38132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40909	0	21600
T1	9232	5	0	2
T2	4662	0	0	2
T3	562382	0	0	2
T7	23752	0	0	2
T8	198490	0	0	2
T9	15768	2	0	2
T10	36724	26	0	2
T11	171198	2	0	2
T12	79772	319	0	2
T13	149588	0	0	2
T14	0	283	0	0
T15	0	352	0	0
T16	0	1	0	0
T17	0	45	0	0
T18	0	534	0	0
T19	0	336	0	0
T20	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	110784	109824	0	0
T2	55944	55104	0	0
T3	6748584	6747768	0	0
T7	285024	281808	0	0
T8	2381880	2380848	0	0
T9	189216	188448	0	0
T10	440688	439416	0	0
T11	2054376	2029608	0	0
T12	957264	954552	0	0
T13	1795056	1794576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7609281	0	0
T1	110784	1883	0	0
T2	55944	475	0	0
T3	6748584	435	0	0
T7	285024	440	0	0
T8	2381880	8863	0	0
T9	189216	2662	0	0
T10	440688	9121	0	0
T11	2054376	7713	0	0
T12	957264	19129	0	0
T13	1795056	7882	0	0
T14	0	18527	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	857035	0	0
GntImpliesValid_A	404523062	857035	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	857035	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	11801364	0	0
ReadyAndValidImplyGrant_A	404523062	857035	0	0
ReqAndReadyImplyGrant_A	404523062	857035	0	0
ReqImpliesValid_A	404523062	2439487	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	857035	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	11801364	0	0
T1	4616	171	0	0
T2	2331	46	0	0
T3	281191	230	0	0
T7	11876	423	0	0
T8	99245	4032	0	0
T9	7884	242	0	0
T10	18362	753	0	0
T11	85599	5640	0	0
T12	39886	1318	0	0
T13	74794	6297	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2439487	0	0
T1	4616	248	0	0
T2	2331	77	0	0
T3	281191	71	0	0
T7	11876	97	0	0
T8	99245	776	0	0
T9	7884	327	0	0
T10	18362	1258	0	0
T11	85599	1099	0	0
T12	39886	2175	0	0
T13	74794	1725	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	857035	0	0
T1	4616	209	0	0
T2	2331	61	0	0
T3	281191	53	0	0
T7	11876	59	0	0
T8	99245	534	0	0
T9	7884	284	0	0
T10	18362	1005	0	0
T11	85599	724	0	0
T12	39886	1745	0	0
T13	74794	886	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	858886	0	0
GntImpliesValid_A	404523062	858886	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	858886	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	11632520	0	0
ReadyAndValidImplyGrant_A	404523062	858886	0	0
ReqAndReadyImplyGrant_A	404523062	858886	0	0
ReqImpliesValid_A	404523062	2438615	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	858886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	11632520	0	0
T1	4616	199	0	0
T2	2331	41	0	0
T3	281191	187	0	0
T7	11876	319	0	0
T8	99245	6765	0	0
T9	7884	216	0	0
T10	18362	726	0	0
T11	85599	5115	0	0
T12	39886	1413	0	0
T13	74794	6254	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2438615	0	0
T1	4616	286	0	0
T2	2331	74	0	0
T3	281191	67	0	0
T7	11876	71	0	0
T8	99245	22728	0	0
T9	7884	289	0	0
T10	18362	1235	0	0
T11	85599	1216	0	0
T12	39886	3668	0	0
T13	74794	1639	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	858886	0	0
T1	4616	242	0	0
T2	2331	57	0	0
T3	281191	49	0	0
T7	11876	45	0	0
T8	99245	2711	0	0
T9	7884	252	0	0
T10	18362	980	0	0
T11	85599	739	0	0
T12	39886	2539	0	0
T13	74794	862	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	205300	0	0
GntImpliesValid_A	404523062	205300	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	205300	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2932343	0	0
ReadyAndValidImplyGrant_A	404523062	205300	0	0
ReqAndReadyImplyGrant_A	404523062	205300	0	0
ReqImpliesValid_A	404523062	529340	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	205300	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2932343	0	0
T1	4616	54	0	0
T2	2331	12	0	0
T3	281191	45	0	0
T7	11876	58	0	0
T8	99245	997	0	0
T9	7884	61	0	0
T10	18362	289	0	0
T11	85599	900	0	0
T12	39886	295	0	0
T13	74794	1596	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	529340	0	0
T1	4616	57	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	36	0	0
T8	99245	4205	0	0
T9	7884	64	0	0
T10	18362	328	0	0
T11	85599	179	0	0
T12	39886	304	0	0
T13	74794	304	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205300	0	0
T1	4616	55	0	0
T2	2331	12	0	0
T3	281191	10	0	0
T7	11876	14	0	0
T8	99245	485	0	0
T9	7884	62	0	0
T10	18362	308	0	0
T11	85599	130	0	0
T12	39886	298	0	0
T13	74794	219	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	216725	0	0
GntImpliesValid_A	404523062	216725	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	216725	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2891011	0	0
ReadyAndValidImplyGrant_A	404523062	216725	0	0
ReqAndReadyImplyGrant_A	404523062	216725	0	0
ReqImpliesValid_A	404523062	561368	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	216725	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2891011	0	0
T1	4616	42	0	0
T2	2331	13	0	0
T3	281191	41	0	0
T7	11876	122	0	0
T8	99245	1	0	0
T9	7884	71	0	0
T10	18362	239	0	0
T11	85599	958	0	0
T12	39886	1044	0	0
T13	74794	1506	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	561368	0	0
T1	4616	47	0	0
T2	2331	14	0	0
T3	281191	27	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	272	0	0
T11	85599	154	0	0
T12	39886	1529	0	0
T13	74794	322	0	0
T14	0	1613	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	216725	0	0
T1	4616	44	0	0
T2	2331	13	0	0
T3	281191	13	0	0
T7	11876	15	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	255	0	0
T11	85599	129	0	0
T12	39886	1285	0	0
T13	74794	246	0	0
T14	0	1353	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	205639	0	0
GntImpliesValid_A	404523062	205639	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	205639	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	4932915	0	0
ReadyAndValidImplyGrant_A	404523062	205639	0	0
ReqAndReadyImplyGrant_A	404523062	205639	0	0
ReqImpliesValid_A	404523062	988295	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	205639	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	4932915	0	0
T1	4616	359	0	0
T2	2331	63	0	0
T3	281191	75	0	0
T7	11876	197	0	0
T8	99245	0	0	0
T9	7884	831	0	0
T10	18362	1392	0	0
T11	85599	1240	0	0
T12	39886	1768	0	0
T13	74794	1785	0	0
T14	0	10296	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	988295	0	0
T1	4616	80	0	0
T2	2331	25	0	0
T3	281191	17	0	0
T7	11876	25	0	0
T8	99245	0	0	0
T9	7884	171	0	0
T10	18362	379	0	0
T11	85599	1263	0	0
T12	39886	332	0	0
T13	74794	247	0	0
T14	0	9053	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	205639	0	0
T1	4616	49	0	0
T2	2331	13	0	0
T3	281191	11	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	95	0	0
T10	18362	260	0	0
T11	85599	268	0	0
T12	39886	270	0	0
T13	74794	199	0	0
T14	0	1439	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	208350	0	0
GntImpliesValid_A	404523062	208350	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	208350	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	4917560	0	0
ReadyAndValidImplyGrant_A	404523062	208350	0	0
ReqAndReadyImplyGrant_A	404523062	208350	0	0
ReqImpliesValid_A	404523062	1181708	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	208350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	4917560	0	0
T1	4616	227	0	0
T2	2331	71	0	0
T3	281191	103	0	0
T7	11876	132	0	0
T8	99245	3055	0	0
T9	7884	581	0	0
T10	18362	2488	0	0
T11	85599	919	0	0
T12	39886	3495	0	0
T13	74794	1298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	1181708	0	0
T1	4616	58	0	0
T2	2331	18	0	0
T3	281191	22	0	0
T7	11876	16	0	0
T8	99245	16193	0	0
T9	7884	122	0	0
T10	18362	669	0	0
T11	85599	143	0	0
T12	39886	554	0	0
T13	74794	298	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	208350	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	986	0	0
T9	7884	77	0	0
T10	18362	250	0	0
T11	85599	122	0	0
T12	39886	291	0	0
T13	74794	227	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	209703	0	0
GntImpliesValid_A	404523062	209703	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	209703	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	4829904	0	0
ReadyAndValidImplyGrant_A	404523062	209703	0	0
ReqAndReadyImplyGrant_A	404523062	209703	0	0
ReqImpliesValid_A	404523062	1192221	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	209703	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	4829904	0	0
T1	4616	181	0	0
T2	2331	106	0	0
T3	281191	156	0	0
T7	11876	492	0	0
T8	99245	0	0	0
T9	7884	600	0	0
T10	18362	3086	0	0
T11	85599	7876	0	0
T12	39886	1223	0	0
T13	74794	1651	0	0
T14	0	7077	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	1192221	0	0
T1	4616	68	0	0
T2	2331	33	0	0
T3	281191	11	0	0
T7	11876	37	0	0
T8	99245	0	0	0
T9	7884	156	0	0
T10	18362	633	0	0
T11	85599	2397	0	0
T12	39886	323	0	0
T13	74794	260	0	0
T14	0	5552	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	209703	0	0
T1	4616	40	0	0
T2	2331	11	0	0
T3	281191	11	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	84	0	0
T10	18362	256	0	0
T11	85599	566	0	0
T12	39886	279	0	0
T13	74794	189	0	0
T14	0	1837	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	207914	0	0
GntImpliesValid_A	404523062	207914	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	207914	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	5325820	0	0
ReadyAndValidImplyGrant_A	404523062	207914	0	0
ReqAndReadyImplyGrant_A	404523062	207914	0	0
ReqImpliesValid_A	404523062	1069792	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	207914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	5325820	0	0
T1	4616	194	0	0
T2	2331	180	0	0
T3	281191	59	0	0
T7	11876	115	0	0
T8	99245	0	0	0
T9	7884	676	0	0
T10	18362	1890	0	0
T11	85599	2970	0	0
T12	39886	5890	0	0
T13	74794	1408	0	0
T14	0	13647	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	1069792	0	0
T1	4616	53	0	0
T2	2331	18	0	0
T3	281191	21	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	115	0	0
T10	18362	493	0	0
T11	85599	341	0	0
T12	39886	3453	0	0
T13	74794	262	0	0
T14	0	8850	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207914	0	0
T1	4616	41	0	0
T2	2331	14	0	0
T3	281191	9	0	0
T7	11876	10	0	0
T8	99245	0	0	0
T9	7884	76	0	0
T10	18362	239	0	0
T11	85599	113	0	0
T12	39886	764	0	0
T13	74794	214	0	0
T14	0	2045	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	203326	0	0
GntImpliesValid_A	404523062	203326	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	203326	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2868155	0	0
ReadyAndValidImplyGrant_A	404523062	203326	0	0
ReqAndReadyImplyGrant_A	404523062	203326	0	0
ReqImpliesValid_A	404523062	513332	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	203326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2868155	0	0
T1	4616	59	0	0
T2	2331	13	0	0
T3	281191	59	0	0
T7	11876	90	0	0
T8	99245	1	0	0
T9	7884	66	0	0
T10	18362	238	0	0
T11	85599	767	0	0
T12	39886	282	0	0
T13	74794	1584	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	513332	0	0
T1	4616	66	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	269	0	0
T11	85599	104	0	0
T12	39886	287	0	0
T13	74794	247	0	0
T14	0	1551	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203326	0	0
T1	4616	62	0	0
T2	2331	12	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	66	0	0
T10	18362	253	0	0
T11	85599	95	0	0
T12	39886	283	0	0
T13	74794	211	0	0
T14	0	1445	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	211273	0	0
GntImpliesValid_A	404523062	211273	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	211273	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2906516	0	0
ReadyAndValidImplyGrant_A	404523062	211273	0	0
ReqAndReadyImplyGrant_A	404523062	211273	0	0
ReqImpliesValid_A	404523062	514732	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	211273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2906516	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	60	0	0
T7	11876	133	0	0
T8	99245	1	0	0
T9	7884	74	0	0
T10	18362	232	0	0
T11	85599	872	0	0
T12	39886	295	0	0
T13	74794	1377	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	514732	0	0
T1	4616	45	0	0
T2	2331	12	0	0
T3	281191	22	0	0
T7	11876	18	0	0
T8	99245	0	0	0
T9	7884	81	0	0
T10	18362	255	0	0
T11	85599	122	0	0
T12	39886	298	0	0
T13	74794	307	0	0
T14	0	910	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211273	0	0
T1	4616	44	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	13	0	0
T8	99245	0	0	0
T9	7884	77	0	0
T10	18362	243	0	0
T11	85599	108	0	0
T12	39886	295	0	0
T13	74794	204	0	0
T14	0	877	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	211006	0	0
GntImpliesValid_A	404523062	211006	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	211006	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2940571	0	0
ReadyAndValidImplyGrant_A	404523062	211006	0	0
ReqAndReadyImplyGrant_A	404523062	211006	0	0
ReqImpliesValid_A	404523062	551738	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	211006	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2940571	0	0
T1	4616	48	0	0
T2	2331	18	0	0
T3	281191	62	0	0
T7	11876	131	0	0
T8	99245	2470	0	0
T9	7884	64	0	0
T10	18362	245	0	0
T11	85599	1007	0	0
T12	39886	711	0	0
T13	74794	1682	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	551738	0	0
T1	4616	49	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	19	0	0
T8	99245	9037	0	0
T9	7884	65	0	0
T10	18362	260	0	0
T11	85599	150	0	0
T12	39886	890	0	0
T13	74794	290	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211006	0	0
T1	4616	48	0	0
T2	2331	17	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	974	0	0
T9	7884	64	0	0
T10	18362	252	0	0
T11	85599	126	0	0
T12	39886	799	0	0
T13	74794	228	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	203538	0	0
GntImpliesValid_A	404523062	203538	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	203538	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2896270	0	0
ReadyAndValidImplyGrant_A	404523062	203538	0	0
ReqAndReadyImplyGrant_A	404523062	203538	0	0
ReqImpliesValid_A	404523062	522684	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	203538	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2896270	0	0
T1	4616	43	0	0
T2	2331	17	0	0
T3	281191	62	0	0
T7	11876	80	0	0
T8	99245	1	0	0
T9	7884	68	0	0
T10	18362	229	0	0
T11	85599	855	0	0
T12	39886	264	0	0
T13	74794	1620	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	522684	0	0
T1	4616	46	0	0
T2	2331	20	0	0
T3	281191	22	0	0
T7	11876	14	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	264	0	0
T11	85599	135	0	0
T12	39886	269	0	0
T13	74794	258	0	0
T14	0	1402	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	203538	0	0
T1	4616	44	0	0
T2	2331	18	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	67	0	0
T10	18362	246	0	0
T11	85599	117	0	0
T12	39886	265	0	0
T13	74794	213	0	0
T14	0	1250	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	215193	0	0
GntImpliesValid_A	404523062	215193	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	215193	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2927523	0	0
ReadyAndValidImplyGrant_A	404523062	215193	0	0
ReqAndReadyImplyGrant_A	404523062	215193	0	0
ReqImpliesValid_A	404523062	547122	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	215193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2927523	0	0
T1	4616	50	0	0
T2	2331	16	0	0
T3	281191	43	0	0
T7	11876	131	0	0
T8	99245	807	0	0
T9	7884	68	0	0
T10	18362	213	0	0
T11	85599	1086	0	0
T12	39886	319	0	0
T13	74794	1698	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	547122	0	0
T1	4616	55	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	16	0	0
T8	99245	4550	0	0
T9	7884	69	0	0
T10	18362	222	0	0
T11	85599	132	0	0
T12	39886	324	0	0
T13	74794	287	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	215193	0	0
T1	4616	52	0	0
T2	2331	15	0	0
T3	281191	12	0	0
T7	11876	15	0	0
T8	99245	485	0	0
T9	7884	68	0	0
T10	18362	217	0	0
T11	85599	129	0	0
T12	39886	320	0	0
T13	74794	234	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T9,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	212201	0	0
GntImpliesValid_A	404523062	212201	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	212201	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2905899	0	0
ReadyAndValidImplyGrant_A	404523062	212201	0	0
ReqAndReadyImplyGrant_A	404523062	212201	0	0
ReqImpliesValid_A	404523062	561749	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	212201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2905899	0	0
T1	4616	44	0	0
T2	2331	12	0	0
T3	281191	24	0	0
T7	11876	99	0	0
T8	99245	866	0	0
T9	7884	81	0	0
T10	18362	255	0	0
T11	85599	3990	0	0
T12	39886	247	0	0
T13	74794	1602	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	561749	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	18	0	0
T8	99245	4617	0	0
T9	7884	92	0	0
T10	18362	294	0	0
T11	85599	1637	0	0
T12	39886	256	0	0
T13	74794	303	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	212201	0	0
T1	4616	43	0	0
T2	2331	11	0	0
T3	281191	6	0	0
T7	11876	12	0	0
T8	99245	463	0	0
T9	7884	86	0	0
T10	18362	274	0	0
T11	85599	613	0	0
T12	39886	250	0	0
T13	74794	215	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	214993	0	0
GntImpliesValid_A	404523062	214993	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	214993	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2968683	0	0
ReadyAndValidImplyGrant_A	404523062	214993	0	0
ReqAndReadyImplyGrant_A	404523062	214993	0	0
ReqImpliesValid_A	404523062	551701	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	214993	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2968683	0	0
T1	4616	37	0	0
T2	2331	13	0	0
T3	281191	23	0	0
T7	11876	51	0	0
T8	99245	872	0	0
T9	7884	73	0	0
T10	18362	235	0	0
T11	85599	1018	0	0
T12	39886	282	0	0
T13	74794	1726	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	551701	0	0
T1	4616	38	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	9	0	0
T8	99245	5581	0	0
T9	7884	74	0	0
T10	18362	254	0	0
T11	85599	167	0	0
T12	39886	287	0	0
T13	74794	303	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	214993	0	0
T1	4616	37	0	0
T2	2331	12	0	0
T3	281191	7	0	0
T7	11876	8	0	0
T8	99245	553	0	0
T9	7884	73	0	0
T10	18362	244	0	0
T11	85599	123	0	0
T12	39886	283	0	0
T13	74794	221	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	221550	0	0
GntImpliesValid_A	404523062	221550	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	221550	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2949373	0	0
ReadyAndValidImplyGrant_A	404523062	221550	0	0
ReqAndReadyImplyGrant_A	404523062	221550	0	0
ReqImpliesValid_A	404523062	575893	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	221550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2949373	0	0
T1	4616	49	0	0
T2	2331	12	0	0
T3	281191	46	0	0
T7	11876	72	0	0
T8	99245	1	0	0
T9	7884	84	0	0
T10	18362	227	0	0
T11	85599	1511	0	0
T12	39886	279	0	0
T13	74794	1584	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	575893	0	0
T1	4616	52	0	0
T2	2331	11	0	0
T3	281191	16	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	89	0	0
T10	18362	262	0	0
T11	85599	436	0	0
T12	39886	1238	0	0
T13	74794	341	0	0
T14	0	1844	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	221550	0	0
T1	4616	50	0	0
T2	2331	11	0	0
T3	281191	15	0	0
T7	11876	8	0	0
T8	99245	0	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	231	0	0
T12	39886	757	0	0
T13	74794	217	0	0
T14	0	1543	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	224797	0	0
GntImpliesValid_A	404523062	224797	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	224797	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	3006374	0	0
ReadyAndValidImplyGrant_A	404523062	224797	0	0
ReqAndReadyImplyGrant_A	404523062	224797	0	0
ReqImpliesValid_A	404523062	529089	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	224797	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	3006374	0	0
T1	4616	89	0	0
T2	2331	6	0	0
T3	281191	55	0	0
T7	11876	72	0	0
T8	99245	1	0	0
T9	7884	119	0	0
T10	18362	238	0	0
T11	85599	1335	0	0
T12	39886	755	0	0
T13	74794	1439	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	529089	0	0
T1	4616	96	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	22	0	0
T8	99245	0	0	0
T9	7884	132	0	0
T10	18362	269	0	0
T11	85599	202	0	0
T12	39886	936	0	0
T13	74794	247	0	0
T14	0	2283	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	224797	0	0
T1	4616	92	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	17	0	0
T8	99245	0	0	0
T9	7884	125	0	0
T10	18362	253	0	0
T11	85599	172	0	0
T12	39886	844	0	0
T13	74794	198	0	0
T14	0	2050	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T9,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	201086	0	0
GntImpliesValid_A	404523062	201086	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	201086	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2859918	0	0
ReadyAndValidImplyGrant_A	404523062	201086	0	0
ReqAndReadyImplyGrant_A	404523062	201086	0	0
ReqImpliesValid_A	404523062	482510	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	201086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2859918	0	0
T1	4616	60	0	0
T2	2331	8	0	0
T3	281191	93	0	0
T7	11876	42	0	0
T8	99245	1082	0	0
T9	7884	78	0	0
T10	18362	224	0	0
T11	85599	855	0	0
T12	39886	1015	0	0
T13	74794	1556	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	482510	0	0
T1	4616	59	0	0
T2	2331	9	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	4999	0	0
T9	7884	83	0	0
T10	18362	251	0	0
T11	85599	153	0	0
T12	39886	1320	0	0
T13	74794	363	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	201086	0	0
T1	4616	59	0	0
T2	2331	8	0	0
T3	281191	18	0	0
T7	11876	5	0	0
T8	99245	534	0	0
T9	7884	80	0	0
T10	18362	237	0	0
T11	85599	108	0	0
T12	39886	1166	0	0
T13	74794	225	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	210913	0	0
GntImpliesValid_A	404523062	210913	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	210913	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2866139	0	0
ReadyAndValidImplyGrant_A	404523062	210913	0	0
ReqAndReadyImplyGrant_A	404523062	210913	0	0
ReqImpliesValid_A	404523062	528342	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	210913	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2866139	0	0
T1	4616	46	0	0
T2	2331	6	0	0
T3	281191	63	0	0
T7	11876	56	0	0
T8	99245	1	0	0
T9	7884	68	0	0
T10	18362	254	0	0
T11	85599	910	0	0
T12	39886	266	0	0
T13	74794	1717	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	528342	0	0
T1	4616	51	0	0
T2	2331	5	0	0
T3	281191	14	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	71	0	0
T10	18362	285	0	0
T11	85599	103	0	0
T12	39886	277	0	0
T13	74794	254	0	0
T14	0	896	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	210913	0	0
T1	4616	48	0	0
T2	2331	5	0	0
T3	281191	11	0	0
T7	11876	7	0	0
T8	99245	0	0	0
T9	7884	69	0	0
T10	18362	269	0	0
T11	85599	103	0	0
T12	39886	270	0	0
T13	74794	209	0	0
T14	0	878	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	211600	0	0
GntImpliesValid_A	404523062	211600	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	211600	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2956589	0	0
ReadyAndValidImplyGrant_A	404523062	211600	0	0
ReqAndReadyImplyGrant_A	404523062	211600	0	0
ReqImpliesValid_A	404523062	547276	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	211600	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2956589	0	0
T1	4616	62	0	0
T2	2331	18	0	0
T3	281191	66	0	0
T7	11876	104	0	0
T8	99245	1	0	0
T9	7884	92	0	0
T10	18362	267	0	0
T11	85599	850	0	0
T12	39886	729	0	0
T13	74794	1573	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	547276	0	0
T1	4616	65	0	0
T2	2331	21	0	0
T3	281191	15	0	0
T7	11876	25	0	0
T8	99245	0	0	0
T9	7884	101	0	0
T10	18362	302	0	0
T11	85599	122	0	0
T12	39886	898	0	0
T13	74794	294	0	0
T14	0	959	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	211600	0	0
T1	4616	63	0	0
T2	2331	19	0	0
T3	281191	15	0	0
T7	11876	12	0	0
T8	99245	0	0	0
T9	7884	96	0	0
T10	18362	284	0	0
T11	85599	106	0	0
T12	39886	812	0	0
T13	74794	225	0	0
T14	0	935	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	217864	0	0
GntImpliesValid_A	404523062	217864	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	217864	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2990194	0	0
ReadyAndValidImplyGrant_A	404523062	217864	0	0
ReqAndReadyImplyGrant_A	404523062	217864	0	0
ReqImpliesValid_A	404523062	584771	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	217864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2990194	0	0
T1	4616	56	0	0
T2	2331	16	0	0
T3	281191	76	0	0
T7	11876	54	0	0
T8	99245	1	0	0
T9	7884	86	0	0
T10	18362	244	0	0
T11	85599	906	0	0
T12	39886	660	0	0
T13	74794	1779	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	584771	0	0
T1	4616	61	0	0
T2	2331	15	0	0
T3	281191	18	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	91	0	0
T10	18362	273	0	0
T11	85599	174	0	0
T12	39886	801	0	0
T13	74794	358	0	0
T14	0	1695	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	217864	0	0
T1	4616	58	0	0
T2	2331	15	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	88	0	0
T10	18362	258	0	0
T11	85599	125	0	0
T12	39886	729	0	0
T13	74794	230	0	0
T14	0	1465	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	207176	0	0
GntImpliesValid_A	404523062	207176	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	207176	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	2908348	0	0
ReadyAndValidImplyGrant_A	404523062	207176	0	0
ReqAndReadyImplyGrant_A	404523062	207176	0	0
ReqImpliesValid_A	404523062	524178	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	0	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	207176	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2908348	0	0
T1	4616	55	0	0
T2	2331	11	0	0
T3	281191	51	0	0
T7	11876	120	0	0
T8	99245	1	0	0
T9	7884	71	0	0
T10	18362	201	0	0
T11	85599	4305	0	0
T12	39886	280	0	0
T13	74794	1674	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	524178	0	0
T1	4616	62	0	0
T2	2331	10	0	0
T3	281191	15	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	74	0	0
T10	18362	224	0	0
T11	85599	1977	0	0
T12	39886	287	0	0
T13	74794	260	0	0
T14	0	1524	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	207176	0	0
T1	4616	58	0	0
T2	2331	10	0	0
T3	281191	14	0	0
T7	11876	11	0	0
T8	99245	0	0	0
T9	7884	72	0	0
T10	18362	212	0	0
T11	85599	619	0	0
T12	39886	282	0	0
T13	74794	226	0	0
T14	0	1410	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	838804	0	0
GntImpliesValid_A	404523062	838804	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	838804	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	11068511	0	0
ReadyAndValidImplyGrant_A	404523062	838804	0	0
ReqAndReadyImplyGrant_A	404523062	838804	0	0
ReqImpliesValid_A	404523062	2150350	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	16362	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	838804	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	11068511	0	0
T1	4616	1	0	0
T2	2331	1	0	0
T3	281191	136	0	0
T7	11876	357	0	0
T8	99245	3853	0	0
T9	7884	1	0	0
T10	18362	1	0	0
T11	85599	8495	0	0
T12	39886	3	0	0
T13	74794	6027	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	2150350	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	45	0	0
T7	11876	120	0	0
T8	99245	842	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	4298	0	0
T12	39886	2450	0	0
T13	74794	1663	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	16362	0	900
T1	4616	4	0	1
T2	2331	0	0	1
T3	281191	0	0	1
T7	11876	0	0	1
T8	99245	0	0	1
T9	7884	1	0	1
T10	18362	10	0	1
T11	85599	2	0	1
T12	39886	303	0	1
T13	74794	0	0	1
T14	0	59	0	0
T15	0	52	0	0
T17	0	36	0	0
T19	0	182	0	0
T20	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	838804	0	0
T1	4616	205	0	0
T2	2331	54	0	0
T3	281191	44	0	0
T7	11876	52	0	0
T8	99245	561	0	0
T9	7884	261	0	0
T10	18362	1010	0	0
T11	85599	1440	0	0
T12	39886	2450	0	0
T13	74794	916	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404523062	404392263	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	404523062	834409	0	0
GntImpliesValid_A	404523062	834409	0	0
GrantKnown_A	404523062	404392263	0	0
IdxKnown_A	404523062	404392263	0	0
IndexIsCorrect_A	404523062	834409	0	0
LockArbDecision_A	404523062	0	0	0
NoReadyValidNoGrant_A	404523062	340137552	0	0
ReadyAndValidImplyGrant_A	404523062	834409	0	0
ReqAndReadyImplyGrant_A	404523062	834409	0	0
ReqImpliesValid_A	404523062	12586054	0	0
ReqStaysHighUntilGranted0_M	404523062	0	0	0
RoundRobin_A	404523062	24547	0	900
ValidKnown_A	404523062	404392263	0	0
gen_data_port_assertion.DataFlow_A	404523062	834409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	340137552	0	0
T1	4616	1	0	0
T2	2331	1	0	0
T3	281191	234172	0	0
T7	11876	10130	0	0
T8	99245	85688	0	0
T9	7884	1	0	0
T10	18362	1	0	0
T11	85599	71976	0	0
T12	39886	1	0	0
T13	74794	61679	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	12586054	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	169	0	0
T7	11876	399	0	0
T8	99245	4993	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	5651	0	0
T12	39886	1853	0	0
T13	74794	7202	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	24547	0	900
T1	4616	1	0	1
T2	2331	0	0	1
T3	281191	0	0	1
T7	11876	0	0	1
T8	99245	0	0	1
T9	7884	1	0	1
T10	18362	16	0	1
T11	85599	0	0	1
T12	39886	16	0	1
T13	74794	0	0	1
T14	0	224	0	0
T15	0	300	0	0
T16	0	1	0	0
T17	0	9	0	0
T18	0	534	0	0
T19	0	154	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	404392263	0	0
T1	4616	4576	0	0
T2	2331	2296	0	0
T3	281191	281157	0	0
T7	11876	11742	0	0
T8	99245	99202	0	0
T9	7884	7852	0	0
T10	18362	18309	0	0
T11	85599	84567	0	0
T12	39886	39773	0	0
T13	74794	74774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404523062	834409	0	0
T1	4616	196	0	0
T2	2331	60	0	0
T3	281191	37	0	0
T7	11876	57	0	0
T8	99245	577	0	0
T9	7884	283	0	0
T10	18362	1072	0	0
T11	85599	707	0	0
T12	39886	1853	0	0
T13	74794	868	0	0