Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2312580	1			T1	1916		T2	1185		T3	262
values[2]	171571	1			T2	37		T3	22		T9	197
values[3]	36976	1			T3	2		T7	19		T8	11
values[4]	23699	1			T7	1		T8	11		T17	269
values[5]	17443	1			T8	11		T17	226		T18	1
values[6]	13389	1			T8	11		T17	138		T18	2
values[7]	11094	1			T8	11		T17	65		T18	1
values[8]	9622	1			T8	12		T17	23		T18	1
values[9]	8707	1			T8	11		T17	5		T18	1
values[10]	7775	1			T8	11		T18	1		T38	27
values[11]	6853	1			T8	11		T18	1		T38	45
values[12]	6008	1			T8	11		T18	2		T38	42
values[13]	5623	1			T8	11		T18	3		T38	23
values[14]	5094	1			T8	12		T18	1		T38	11
values[15]	4894	1			T8	12		T18	2		T38	3
values[16]	4468	1			T8	11		T18	3		T38	3
values[17]	4106	1			T8	11		T18	4		T38	1
values[18]	3790	1			T8	11		T18	2		T161	1
values[19]	3630	1			T8	11		T18	1		T161	1
values[20]	3503	1			T8	11		T18	1		T161	1
values[21]	3521	1			T8	11		T18	1		T161	1
values[22]	3269	1			T8	11		T18	1		T161	1
values[23]	3039	1			T8	11		T18	1		T161	1
values[24]	2921	1			T8	11		T18	2		T161	1
values[25]	2878	1			T8	11		T18	5		T161	1
values[26]	2676	1			T8	11		T18	1		T161	1
values[27]	2477	1			T8	11		T18	3		T161	1
values[28]	2480	1			T8	11		T18	2		T161	1
values[29]	2394	1			T8	11		T18	2		T161	1
values[30]	2246	1			T8	11		T18	3		T161	1
values[31]	2103	1			T8	11		T18	1		T161	1
values[32]	2088	1			T8	11		T18	1		T161	1
values[33]	2104	1			T8	11		T18	1		T161	1
values[34]	2033	1			T8	11		T18	2		T161	1
values[35]	1849	1			T8	11		T18	1		T161	1
values[36]	1782	1			T8	11		T18	5		T161	1
values[37]	1794	1			T8	11		T18	2		T161	1
values[38]	1699	1			T8	11		T18	3		T161	1
values[39]	1648	1			T8	11		T18	1		T161	1
values[40]	1666	1			T8	11		T18	1		T161	1
values[41]	1689	1			T8	11		T18	1		T161	1
values[42]	1648	1			T8	11		T18	3		T161	1
values[43]	1589	1			T8	11		T18	1		T161	1
values[44]	1549	1			T8	11		T18	1		T161	1
values[45]	1568	1			T8	12		T18	1		T161	1
values[46]	1537	1			T8	11		T18	3		T161	1
values[47]	1531	1			T8	11		T18	6		T161	1
values[48]	1519	1			T8	11		T18	1		T161	1
values[49]	1423	1			T8	12		T18	2		T161	1
values[50]	1472	1			T8	11		T18	3		T161	1
values[51]	1510	1			T8	11		T18	1		T161	1
values[52]	1491	1			T8	11		T18	3		T161	1
values[53]	1433	1			T8	11		T18	1		T161	1
values[54]	1420	1			T8	11		T18	1		T161	1
values[55]	1392	1			T8	11		T18	1		T161	1
values[56]	1396	1			T8	11		T18	1		T161	1
values[57]	1456	1			T8	11		T18	1		T161	1
values[58]	1428	1			T8	12		T18	2		T161	1
values[59]	1449	1			T8	11		T18	1		T161	1
values[60]	1514	1			T8	12		T18	1		T161	1
values[61]	1606	1			T8	11		T18	1		T161	1
values[62]	2768	1			T8	11		T18	2		T161	1
values[63]	8266	1			T8	13		T18	5		T161	1
values[64]	125903	1			T8	2083		T18	144		T161	210

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2385881	1			T1	1967		T2	1036		T3	151
values[2]	404398	1			T2	66		T3	55		T9	554
values[3]	41138	1			T3	16		T9	29		T7	130
values[4]	8350	1			T3	8		T9	1		T7	38
values[5]	4017	1			T3	3		T7	13		T8	20
values[6]	2726	1			T3	1		T7	5		T8	6
values[7]	2147	1			T7	3		T8	4		T17	14
values[8]	1767	1			T7	1		T17	9		T18	6
values[9]	1648	1			T17	2		T18	6		T23	2
values[10]	1496	1			T18	6		T23	4		T161	1
values[11]	1506	1			T18	3		T23	2		T161	1
values[12]	1393	1			T18	3		T161	1		T67	4
values[13]	1312	1			T18	3		T161	1		T67	4
values[14]	1208	1			T18	3		T161	1		T67	4
values[15]	1092	1			T18	6		T161	1		T67	4
values[16]	1037	1			T18	2		T161	1		T67	4
values[17]	975	1			T18	2		T161	1		T67	4
values[18]	1030	1			T18	2		T161	1		T67	4
values[19]	980	1			T18	2		T161	1		T67	4
values[20]	921	1			T18	2		T161	1		T67	4
values[21]	841	1			T18	1		T161	1		T67	4
values[22]	771	1			T161	1		T67	4		T5	1
values[23]	782	1			T161	1		T67	4		T5	1
values[24]	741	1			T161	1		T67	4		T5	1
values[25]	699	1			T161	1		T67	4		T5	1
values[26]	698	1			T161	1		T67	4		T5	1
values[27]	655	1			T161	1		T67	4		T5	1
values[28]	673	1			T161	1		T67	4		T5	1
values[29]	633	1			T161	1		T67	4		T5	1
values[30]	628	1			T161	1		T67	4		T5	1
values[31]	597	1			T161	1		T67	4		T5	1
values[32]	576	1			T161	1		T67	4		T5	1
values[33]	552	1			T161	1		T67	4		T5	1
values[34]	552	1			T161	1		T67	4		T5	1
values[35]	540	1			T161	1		T67	4		T5	1
values[36]	549	1			T161	1		T67	4		T5	1
values[37]	515	1			T161	1		T67	4		T5	1
values[38]	474	1			T161	1		T67	4		T5	1
values[39]	530	1			T161	1		T67	4		T5	1
values[40]	518	1			T161	1		T67	4		T5	1
values[41]	511	1			T161	1		T67	4		T5	1
values[42]	456	1			T161	1		T67	4		T5	1
values[43]	462	1			T161	1		T67	4		T5	1
values[44]	475	1			T161	1		T67	5		T5	1
values[45]	460	1			T161	1		T67	4		T5	1
values[46]	467	1			T161	1		T67	4		T5	1
values[47]	475	1			T161	1		T67	4		T5	1
values[48]	464	1			T161	1		T67	4		T5	1
values[49]	478	1			T161	1		T67	4		T5	1
values[50]	451	1			T161	1		T67	4		T5	1
values[51]	433	1			T161	1		T67	4		T5	1
values[52]	409	1			T161	1		T67	4		T5	1
values[53]	381	1			T161	1		T67	4		T5	1
values[54]	398	1			T161	1		T67	4		T5	1
values[55]	386	1			T161	2		T67	4		T5	1
values[56]	386	1			T161	1		T67	4		T5	1
values[57]	406	1			T161	1		T67	4		T5	2
values[58]	392	1			T161	1		T67	4		T5	1
values[59]	392	1			T161	1		T67	4		T5	1
values[60]	395	1			T161	1		T67	4		T5	1
values[61]	396	1			T161	1		T67	4		T5	1
values[62]	640	1			T161	1		T67	4		T5	1
values[63]	2360	1			T161	1		T67	5		T5	1
values[64]	28233	1			T161	225		T67	792		T5	169

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	284644	1			T1	2047		T2	8		T3	2
values[2]	1656088	1			T2	1246		T3	2		T9	2417
values[3]	501509	1			T2	45		T3	328		T9	189
values[4]	50653	1			T3	20		T7	95		T8	11
values[5]	33725	1			T3	1		T7	4		T8	11
values[6]	25203	1			T8	11		T17	284		T18	8
values[7]	19935	1			T8	11		T17	175		T18	1
values[8]	16768	1			T8	11		T17	91		T18	4
values[9]	14121	1			T8	11		T17	72		T18	2
values[10]	12357	1			T8	11		T17	66		T18	14
values[11]	10679	1			T8	11		T17	47		T18	8
values[12]	9620	1			T8	11		T17	37		T18	19
values[13]	8571	1			T8	11		T17	22		T18	4
values[14]	7499	1			T8	11		T17	5		T18	8
values[15]	6642	1			T8	11		T17	3		T18	2
values[16]	6062	1			T8	11		T17	1		T18	5
values[17]	5804	1			T8	11		T18	4		T38	2
values[18]	5281	1			T8	11		T18	12		T38	4
values[19]	4736	1			T8	11		T18	5		T38	1
values[20]	4471	1			T8	11		T18	4		T161	1
values[21]	4110	1			T8	11		T18	7		T161	1
values[22]	3672	1			T8	11		T18	2		T161	1
values[23]	3540	1			T8	11		T18	1		T161	1
values[24]	3251	1			T8	11		T18	3		T161	1
values[25]	2939	1			T8	11		T18	2		T161	1
values[26]	2753	1			T8	11		T18	1		T161	1
values[27]	2677	1			T8	11		T18	1		T161	1
values[28]	2477	1			T8	11		T18	2		T161	1
values[29]	2362	1			T8	11		T18	1		T161	1
values[30]	2283	1			T8	11		T18	2		T161	1
values[31]	2215	1			T8	11		T18	7		T161	1
values[32]	2118	1			T8	11		T18	2		T161	1
values[33]	2041	1			T8	11		T18	1		T161	1
values[34]	1957	1			T8	11		T18	1		T161	1
values[35]	1846	1			T8	11		T18	1		T161	1
values[36]	1897	1			T8	11		T18	3		T161	1
values[37]	1813	1			T8	11		T18	1		T161	1
values[38]	1737	1			T8	11		T18	2		T161	1
values[39]	1688	1			T8	11		T18	2		T161	1
values[40]	1684	1			T8	11		T18	2		T161	1
values[41]	1705	1			T8	12		T18	1		T161	1
values[42]	1665	1			T8	11		T18	5		T161	1
values[43]	1610	1			T8	11		T18	3		T161	1
values[44]	1616	1			T8	12		T18	1		T161	1
values[45]	1555	1			T8	11		T18	1		T161	1
values[46]	1557	1			T8	11		T18	1		T161	1
values[47]	1562	1			T8	11		T18	2		T161	1
values[48]	1608	1			T8	11		T18	2		T161	1
values[49]	1571	1			T8	11		T18	1		T161	1
values[50]	1543	1			T8	11		T18	5		T161	1
values[51]	1505	1			T8	12		T18	1		T161	1
values[52]	1525	1			T8	11		T18	5		T161	1
values[53]	1457	1			T8	11		T18	1		T161	1
values[54]	1444	1			T8	11		T18	2		T161	1
values[55]	1411	1			T8	11		T18	1		T161	1
values[56]	1412	1			T8	11		T18	1		T161	1
values[57]	1464	1			T8	11		T18	1		T161	1
values[58]	1499	1			T8	11		T18	1		T161	1
values[59]	1477	1			T8	11		T18	3		T161	1
values[60]	1475	1			T8	11		T18	2		T161	1
values[61]	1642	1			T8	12		T18	1		T161	1
values[62]	2566	1			T8	11		T18	2		T161	1
values[63]	7711	1			T8	13		T18	1		T161	1
values[64]	126618	1			T8	2047		T18	6		T161	183