Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1557352 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 247284 1 T1 270 T2 168 T3 44


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 612223 1 T1 664 T2 414 T3 95
values[0x0] 579850 1 T1 617 T2 398 T3 94
values[0x1] 612563 1 T1 635 T2 410 T3 97


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1203745 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 600891 1 T1 670 T2 413 T3 94


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27943 1 T1 19 T2 12 T9 57
valid_sources[0x01] 29844 1 T1 22 T2 32 T9 63
valid_sources[0x02] 27498 1 T1 69 T9 37 T7 24
valid_sources[0x03] 28318 1 T1 43 T9 51 T7 37
valid_sources[0x04] 28828 1 T1 8 T3 19 T9 36
valid_sources[0x05] 29034 1 T1 39 T2 37 T9 55
valid_sources[0x06] 28083 1 T1 20 T2 21 T9 32
valid_sources[0x07] 27799 1 T1 16 T2 38 T3 17
valid_sources[0x08] 27396 1 T1 7 T2 53 T3 8
valid_sources[0x09] 27720 1 T1 42 T2 46 T9 53
valid_sources[0x0a] 28578 1 T2 110 T9 62 T7 47
valid_sources[0x0b] 28877 1 T1 46 T9 46 T7 27
valid_sources[0x0c] 28058 1 T1 25 T3 3 T9 36
valid_sources[0x0d] 27109 1 T1 38 T2 66 T3 12
valid_sources[0x0e] 28347 1 T1 42 T2 18 T9 50
valid_sources[0x0f] 27627 1 T1 9 T9 32 T7 34
valid_sources[0x10] 28173 1 T1 6 T2 3 T9 46
valid_sources[0x11] 27723 1 T1 30 T2 19 T9 39
valid_sources[0x12] 28090 1 T1 35 T3 10 T9 37
valid_sources[0x13] 28395 1 T9 48 T7 51 T10 3
valid_sources[0x14] 27583 1 T1 18 T9 39 T7 39
valid_sources[0x15] 27916 1 T1 95 T9 31 T7 31
valid_sources[0x16] 26928 1 T1 39 T2 2 T3 2
valid_sources[0x17] 28412 1 T1 49 T2 2 T9 49
valid_sources[0x18] 27664 1 T1 48 T9 50 T7 50
valid_sources[0x19] 28827 1 T2 29 T3 21 T9 39
valid_sources[0x1a] 29210 1 T1 36 T9 48 T7 27
valid_sources[0x1b] 28959 1 T1 12 T2 22 T9 50
valid_sources[0x1c] 27837 1 T1 6 T2 13 T3 17
valid_sources[0x1d] 28713 1 T1 30 T2 43 T9 35
valid_sources[0x1e] 29099 1 T9 37 T7 37 T10 2
valid_sources[0x1f] 28289 1 T1 14 T3 62 T9 56
valid_sources[0x20] 27885 1 T1 49 T9 47 T7 45


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26061 1 T1 22 T2 19 T3 7
values[0x0] all_enables biggest_size 195005 1 T1 215 T2 137 T3 33
values[0x1] all_enables biggest_size 26218 1 T1 33 T2 12 T3 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1568230 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 255329 1 T1 304 T2 158 T3 30


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 622186 1 T1 678 T2 362 T3 76
values[0x0] 576905 1 T1 631 T2 371 T3 68
values[0x1] 624468 1 T1 658 T2 369 T3 90


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1203475 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 620084 1 T1 684 T2 392 T3 76


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28813 1 T1 5 T3 1 T9 49
valid_sources[0x01] 28943 1 T1 25 T2 35 T3 9
valid_sources[0x02] 28829 1 T1 78 T2 78 T9 41
valid_sources[0x03] 27536 1 T1 38 T2 22 T3 6
valid_sources[0x04] 28564 1 T1 15 T2 19 T3 2
valid_sources[0x05] 27792 1 T1 39 T2 18 T9 28
valid_sources[0x06] 28906 1 T1 10 T2 10 T3 4
valid_sources[0x07] 28464 1 T1 25 T2 2 T3 3
valid_sources[0x08] 28825 1 T1 11 T2 14 T9 57
valid_sources[0x09] 28052 1 T1 50 T2 18 T3 5
valid_sources[0x0a] 28373 1 T2 2 T3 4 T9 48
valid_sources[0x0b] 28457 1 T1 47 T3 1 T9 75
valid_sources[0x0c] 28451 1 T1 34 T2 23 T3 1
valid_sources[0x0d] 28880 1 T1 42 T9 48 T7 16
valid_sources[0x0e] 28251 1 T1 32 T2 41 T3 1
valid_sources[0x0f] 28354 1 T1 11 T2 26 T3 4
valid_sources[0x10] 27792 1 T1 16 T3 2 T9 62
valid_sources[0x11] 27367 1 T1 50 T2 8 T3 5
valid_sources[0x12] 27872 1 T1 40 T2 16 T3 2
valid_sources[0x13] 28532 1 T2 55 T3 16 T9 54
valid_sources[0x14] 28585 1 T1 35 T2 57 T9 43
valid_sources[0x15] 28170 1 T1 86 T2 7 T3 8
valid_sources[0x16] 28113 1 T1 52 T3 1 T9 66
valid_sources[0x17] 28814 1 T1 57 T2 39 T3 5
valid_sources[0x18] 27737 1 T1 54 T2 6 T3 6
valid_sources[0x19] 28226 1 T2 25 T3 3 T9 55
valid_sources[0x1a] 29027 1 T1 28 T9 35 T7 31
valid_sources[0x1b] 28551 1 T1 19 T2 1 T3 11
valid_sources[0x1c] 28161 1 T1 5 T3 7 T9 61
valid_sources[0x1d] 28758 1 T1 15 T2 33 T3 10
valid_sources[0x1e] 28480 1 T3 1 T9 58 T7 59
valid_sources[0x1f] 28890 1 T1 10 T2 11 T3 1
valid_sources[0x20] 29259 1 T1 68 T3 10 T9 52


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26621 1 T1 37 T2 12 T3 2
values[0x0] all_enables biggest_size 202112 1 T1 244 T2 132 T3 24
values[0x1] all_enables biggest_size 26596 1 T1 23 T2 14 T3 4


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1571653 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 250759 1 T1 311 T2 181 T3 54


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 618136 1 T1 685 T2 438 T3 117
values[0x0] 586346 1 T1 688 T2 434 T3 121
values[0x1] 617930 1 T1 674 T2 427 T3 115


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1214972 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 607440 1 T1 685 T2 416 T3 119


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27949 1 T1 8 T2 4 T9 43
valid_sources[0x01] 28694 1 T1 26 T2 25 T9 37
valid_sources[0x02] 28899 1 T1 75 T2 28 T9 28
valid_sources[0x03] 28562 1 T1 19 T2 24 T9 39
valid_sources[0x04] 28038 1 T1 18 T2 47 T9 34
valid_sources[0x05] 28254 1 T1 42 T2 25 T3 9
valid_sources[0x06] 27847 1 T1 6 T2 18 T9 39
valid_sources[0x07] 28361 1 T1 19 T2 19 T9 26
valid_sources[0x08] 28689 1 T1 6 T2 12 T3 27
valid_sources[0x09] 27351 1 T1 38 T2 9 T3 4
valid_sources[0x0a] 28525 1 T2 15 T9 50 T7 36
valid_sources[0x0b] 28568 1 T1 54 T2 25 T3 9
valid_sources[0x0c] 28415 1 T1 24 T2 14 T9 35
valid_sources[0x0d] 28248 1 T1 45 T2 30 T9 39
valid_sources[0x0e] 28870 1 T1 43 T2 23 T9 36
valid_sources[0x0f] 28544 1 T1 10 T2 22 T9 56
valid_sources[0x10] 29391 1 T1 16 T2 17 T9 42
valid_sources[0x11] 28055 1 T1 34 T2 18 T9 36
valid_sources[0x12] 28491 1 T1 43 T2 26 T3 8
valid_sources[0x13] 27919 1 T2 24 T3 6 T9 56
valid_sources[0x14] 28626 1 T1 31 T2 29 T9 36
valid_sources[0x15] 28329 1 T1 82 T2 27 T9 51
valid_sources[0x16] 28512 1 T1 39 T2 14 T9 56
valid_sources[0x17] 28416 1 T1 37 T2 12 T3 20
valid_sources[0x18] 27562 1 T1 51 T2 23 T9 39
valid_sources[0x19] 29162 1 T2 8 T3 15 T9 34
valid_sources[0x1a] 29486 1 T1 35 T2 21 T9 44
valid_sources[0x1b] 30054 1 T1 19 T2 10 T9 32
valid_sources[0x1c] 28150 1 T1 18 T2 24 T9 41
valid_sources[0x1d] 28599 1 T1 25 T2 8 T9 61
valid_sources[0x1e] 28549 1 T2 21 T3 37 T9 37
valid_sources[0x1f] 28212 1 T1 17 T2 32 T9 45
valid_sources[0x20] 27913 1 T1 79 T2 18 T9 39


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26376 1 T1 21 T2 13 T3 3
values[0x0] all_enables biggest_size 198043 1 T1 258 T2 153 T3 45
values[0x1] all_enables biggest_size 26340 1 T1 32 T2 15 T3 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%