Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7803627	0	0
GntImpliesValid_A	2147483647	7803627	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7803627	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	468142614	0	0
ReadyAndValidImplyGrant_A	2147483647	7803627	0	0
ReqAndReadyImplyGrant_A	2147483647	7803627	0	0
ReqImpliesValid_A	2147483647	34639403	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50589	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7803627	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434664	433800	0	0
T2	123648	122736	0	0
T3	6194136	6194016	0	0
T4	5895624	5895480	0	0
T7	3784440	3784344	0	0
T8	11863344	11863248	0	0
T9	306936	306336	0	0
T10	48528	47376	0	0
T11	332664	331824	0	0
T12	77616	76200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434664	433800	0	0
T2	123648	122736	0	0
T3	6194136	6194016	0	0
T4	5895624	5895480	0	0
T7	3784440	3784344	0	0
T8	11863344	11863248	0	0
T9	306936	306336	0	0
T10	48528	47376	0	0
T11	332664	331824	0	0
T12	77616	76200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434664	433800	0	0
T2	123648	122736	0	0
T3	6194136	6194016	0	0
T4	5895624	5895480	0	0
T7	3784440	3784344	0	0
T8	11863344	11863248	0	0
T9	306936	306336	0	0
T10	48528	47376	0	0
T11	332664	331824	0	0
T12	77616	76200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	468142614	0	0
T1	434664	9378	0	0
T2	123648	2821	0	0
T3	6194136	217953	0	0
T4	5895624	2011659	0	0
T7	3784440	160714	0	0
T8	11863344	461635	0	0
T9	306936	8576	0	0
T10	48528	540	0	0
T11	332664	10117	0	0
T12	77616	1847	0	0
T13	0	1356	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34639403	0	0
T1	434664	6143	0	0
T2	123648	2146	0	0
T3	6194136	1325	0	0
T4	5895624	370901	0	0
T7	3784440	12057	0	0
T8	11863344	25355	0	0
T9	306936	9583	0	0
T10	48528	484	0	0
T11	332664	9245	0	0
T12	77616	1215	0	0
T13	0	410	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50589	0	21600
T1	36222	13	0	2
T2	10304	2	0	2
T3	516178	0	0	2
T4	491302	0	0	2
T7	315370	0	0	2
T8	988612	0	0	2
T9	25578	31	0	2
T10	4044	0	0	2
T11	27722	32	0	2
T12	6468	5	0	2
T14	0	642	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	0	4	0	0
T18	0	418	0	0
T19	0	20	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	434664	433800	0	0
T2	123648	122736	0	0
T3	6194136	6194016	0	0
T4	5895624	5895480	0	0
T7	3784440	3784344	0	0
T8	11863344	11863248	0	0
T9	306936	306336	0	0
T10	48528	47376	0	0
T11	332664	331824	0	0
T12	77616	76200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7803627	0	0
T1	434664	5905	0	0
T2	123648	1876	0	0
T3	6194136	873	0	0
T4	5895624	5168	0	0
T7	3784440	7435	0	0
T8	11863344	8235	0	0
T9	306936	8494	0	0
T10	48528	459	0	0
T11	332664	7953	0	0
T12	77616	1060	0	0
T13	0	246	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	867277	0	0
GntImpliesValid_A	434339865	867277	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	867277	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	12092739	0	0
ReadyAndValidImplyGrant_A	434339865	867277	0	0
ReqAndReadyImplyGrant_A	434339865	867277	0	0
ReqImpliesValid_A	434339865	2498561	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	867277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	12092739	0	0
T1	18111	601	0	0
T2	5152	154	0	0
T3	258089	395	0	0
T4	245651	170669	0	0
T7	157685	3293	0	0
T8	494306	2822	0	0
T9	12789	705	0	0
T10	2022	36	0	0
T11	13861	651	0	0
T12	3234	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	2498561	0	0
T1	18111	626	0	0
T2	5152	199	0	0
T3	258089	112	0	0
T4	245651	19179	0	0
T7	157685	1137	0	0
T8	494306	949	0	0
T9	12789	1208	0	0
T10	2022	45	0	0
T11	13861	1088	0	0
T12	3234	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867277	0	0
T1	18111	613	0	0
T2	5152	176	0	0
T3	258089	89	0	0
T4	245651	575	0	0
T7	157685	812	0	0
T8	494306	677	0	0
T9	12789	956	0	0
T10	2022	40	0	0
T11	13861	869	0	0
T12	3234	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	861401	0	0
GntImpliesValid_A	434339865	861401	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	861401	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	12108474	0	0
ReadyAndValidImplyGrant_A	434339865	861401	0	0
ReqAndReadyImplyGrant_A	434339865	861401	0	0
ReqImpliesValid_A	434339865	2427294	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	861401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	12108474	0	0
T1	18111	656	0	0
T2	5152	160	0	0
T3	258089	336	0	0
T4	245651	180536	0	0
T7	157685	3549	0	0
T8	494306	2879	0	0
T9	12789	698	0	0
T10	2022	43	0	0
T11	13861	624	0	0
T12	3234	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	2427294	0	0
T1	18111	695	0	0
T2	5152	225	0	0
T3	258089	87	0	0
T4	245651	21820	0	0
T7	157685	1193	0	0
T8	494306	1002	0	0
T9	12789	1177	0	0
T10	2022	66	0	0
T11	13861	1083	0	0
T12	3234	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	861401	0	0
T1	18111	675	0	0
T2	5152	192	0	0
T3	258089	78	0	0
T4	245651	618	0	0
T7	157685	866	0	0
T8	494306	693	0	0
T9	12789	937	0	0
T10	2022	54	0	0
T11	13861	853	0	0
T12	3234	119	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	223704	0	0
GntImpliesValid_A	434339865	223704	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	223704	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3091097	0	0
ReadyAndValidImplyGrant_A	434339865	223704	0	0
ReqAndReadyImplyGrant_A	434339865	223704	0	0
ReqImpliesValid_A	434339865	600053	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	223704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3091097	0	0
T1	18111	169	0	0
T2	5152	59	0	0
T3	258089	146	0	0
T4	245651	46289	0	0
T7	157685	900	0	0
T8	494306	1	0	0
T9	12789	230	0	0
T10	2022	10	0	0
T11	13861	217	0	0
T12	3234	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	600053	0	0
T1	18111	168	0	0
T2	5152	62	0	0
T3	258089	40	0	0
T4	245651	2293	0	0
T7	157685	264	0	0
T8	494306	0	0	0
T9	12789	255	0	0
T10	2022	13	0	0
T11	13861	230	0	0
T12	3234	35	0	0
T13	0	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223704	0	0
T1	18111	168	0	0
T2	5152	60	0	0
T3	258089	29	0	0
T4	245651	128	0	0
T7	157685	224	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	11	0	0
T11	13861	223	0	0
T12	3234	33	0	0
T13	0	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	214348	0	0
GntImpliesValid_A	434339865	214348	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	214348	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3077309	0	0
ReadyAndValidImplyGrant_A	434339865	214348	0	0
ReqAndReadyImplyGrant_A	434339865	214348	0	0
ReqImpliesValid_A	434339865	571625	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	214348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3077309	0	0
T1	18111	183	0	0
T2	5152	63	0	0
T3	258089	174	0	0
T4	245651	49476	0	0
T7	157685	827	0	0
T8	494306	1709	0	0
T9	12789	230	0	0
T10	2022	12	0	0
T11	13861	194	0	0
T12	3234	27	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	571625	0	0
T1	18111	184	0	0
T2	5152	70	0	0
T3	258089	42	0	0
T4	245651	3443	0	0
T7	157685	283	0	0
T8	494306	1099	0	0
T9	12789	251	0	0
T10	2022	13	0	0
T11	13861	209	0	0
T12	3234	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214348	0	0
T1	18111	183	0	0
T2	5152	66	0	0
T3	258089	38	0	0
T4	245651	143	0	0
T7	157685	204	0	0
T8	494306	494	0	0
T9	12789	240	0	0
T10	2022	12	0	0
T11	13861	201	0	0
T12	3234	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	222975	0	0
GntImpliesValid_A	434339865	222975	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	222975	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	5803259	0	0
ReadyAndValidImplyGrant_A	434339865	222975	0	0
ReqAndReadyImplyGrant_A	434339865	222975	0	0
ReqImpliesValid_A	434339865	1418582	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	222975	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	5803259	0	0
T1	18111	1033	0	0
T2	5152	290	0	0
T3	258089	90	0	0
T4	245651	366181	0	0
T7	157685	2283	0	0
T8	494306	11490	0	0
T9	12789	836	0	0
T10	2022	40	0	0
T11	13861	976	0	0
T12	3234	418	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	1418582	0	0
T1	18111	206	0	0
T2	5152	92	0	0
T3	258089	29	0	0
T4	245651	52997	0	0
T7	157685	380	0	0
T8	494306	4084	0	0
T9	12789	295	0	0
T10	2022	9	0	0
T11	13861	346	0	0
T12	3234	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222975	0	0
T1	18111	182	0	0
T2	5152	56	0	0
T3	258089	23	0	0
T4	245651	145	0	0
T7	157685	236	0	0
T8	494306	552	0	0
T9	12789	210	0	0
T10	2022	9	0	0
T11	13861	239	0	0
T12	3234	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	206169	0	0
GntImpliesValid_A	434339865	206169	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	206169	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	4709683	0	0
ReadyAndValidImplyGrant_A	434339865	206169	0	0
ReqAndReadyImplyGrant_A	434339865	206169	0	0
ReqImpliesValid_A	434339865	1044568	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	206169	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	4709683	0	0
T1	18111	986	0	0
T2	5152	445	0	0
T3	258089	105	0	0
T4	245651	46228	0	0
T7	157685	994	0	0
T8	494306	0	0	0
T9	12789	920	0	0
T10	2022	94	0	0
T11	13861	1450	0	0
T12	3234	311	0	0
T13	0	983	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	1044568	0	0
T1	18111	182	0	0
T2	5152	101	0	0
T3	258089	21	0	0
T4	245651	2068	0	0
T7	157685	238	0	0
T8	494306	0	0	0
T9	12789	259	0	0
T10	2022	14	0	0
T11	13861	410	0	0
T12	3234	79	0	0
T13	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206169	0	0
T1	18111	144	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	138	0	0
T7	157685	184	0	0
T8	494306	0	0	0
T9	12789	205	0	0
T10	2022	14	0	0
T11	13861	218	0	0
T12	3234	44	0	0
T13	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	207207	0	0
GntImpliesValid_A	434339865	207207	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	207207	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	4400016	0	0
ReadyAndValidImplyGrant_A	434339865	207207	0	0
ReqAndReadyImplyGrant_A	434339865	207207	0	0
ReqImpliesValid_A	434339865	985285	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	207207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	4400016	0	0
T1	18111	2672	0	0
T2	5152	255	0	0
T3	258089	95	0	0
T4	245651	42863	0	0
T7	157685	1220	0	0
T8	494306	0	0	0
T9	12789	908	0	0
T10	2022	46	0	0
T11	13861	1637	0	0
T12	3234	229	0	0
T13	0	373	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	985285	0	0
T1	18111	287	0	0
T2	5152	73	0	0
T3	258089	26	0	0
T4	245651	2531	0	0
T7	157685	274	0	0
T8	494306	0	0	0
T9	12789	342	0	0
T10	2022	10	0	0
T11	13861	441	0	0
T12	3234	66	0	0
T13	0	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	207207	0	0
T1	18111	169	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	132	0	0
T7	157685	199	0	0
T8	494306	0	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	239	0	0
T12	3234	34	0	0
T13	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	223736	0	0
GntImpliesValid_A	434339865	223736	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	223736	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	4353165	0	0
ReadyAndValidImplyGrant_A	434339865	223736	0	0
ReqAndReadyImplyGrant_A	434339865	223736	0	0
ReqImpliesValid_A	434339865	1258854	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	223736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	4353165	0	0
T1	18111	825	0	0
T2	5152	624	0	0
T3	258089	116	0	0
T4	245651	53117	0	0
T7	157685	1435	0	0
T8	494306	15743	0	0
T9	12789	918	0	0
T10	2022	67	0	0
T11	13861	1369	0	0
T12	3234	237	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	1258854	0	0
T1	18111	173	0	0
T2	5152	122	0	0
T3	258089	22	0	0
T4	245651	3960	0	0
T7	157685	297	0	0
T8	494306	5149	0	0
T9	12789	356	0	0
T10	2022	9	0	0
T11	13861	387	0	0
T12	3234	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	223736	0	0
T1	18111	166	0	0
T2	5152	55	0	0
T3	258089	22	0	0
T4	245651	141	0	0
T7	157685	220	0	0
T8	494306	565	0	0
T9	12789	231	0	0
T10	2022	9	0	0
T11	13861	222	0	0
T12	3234	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	214801	0	0
GntImpliesValid_A	434339865	214801	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	214801	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3068478	0	0
ReadyAndValidImplyGrant_A	434339865	214801	0	0
ReqAndReadyImplyGrant_A	434339865	214801	0	0
ReqImpliesValid_A	434339865	582683	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	214801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3068478	0	0
T1	18111	138	0	0
T2	5152	56	0	0
T3	258089	122	0	0
T4	245651	48561	0	0
T7	157685	881	0	0
T8	494306	1554	0	0
T9	12789	224	0	0
T10	2022	14	0	0
T11	13861	237	0	0
T12	3234	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	582683	0	0
T1	18111	137	0	0
T2	5152	61	0	0
T3	258089	25	0	0
T4	245651	3029	0	0
T7	157685	245	0	0
T8	494306	1209	0	0
T9	12789	247	0	0
T10	2022	13	0	0
T11	13861	260	0	0
T12	3234	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	214801	0	0
T1	18111	137	0	0
T2	5152	58	0	0
T3	258089	23	0	0
T4	245651	141	0	0
T7	157685	204	0	0
T8	494306	465	0	0
T9	12789	235	0	0
T10	2022	13	0	0
T11	13861	248	0	0
T12	3234	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	210505	0	0
GntImpliesValid_A	434339865	210505	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	210505	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3087183	0	0
ReadyAndValidImplyGrant_A	434339865	210505	0	0
ReqAndReadyImplyGrant_A	434339865	210505	0	0
ReqImpliesValid_A	434339865	576552	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	210505	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3087183	0	0
T1	18111	166	0	0
T2	5152	61	0	0
T3	258089	146	0	0
T4	245651	45431	0	0
T7	157685	869	0	0
T8	494306	1672	0	0
T9	12789	244	0	0
T10	2022	16	0	0
T11	13861	204	0	0
T12	3234	25	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	576552	0	0
T1	18111	171	0	0
T2	5152	68	0	0
T3	258089	44	0	0
T4	245651	1156	0	0
T7	157685	206	0	0
T8	494306	1241	0	0
T9	12789	273	0	0
T10	2022	15	0	0
T11	13861	217	0	0
T12	3234	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210505	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	36	0	0
T4	245651	141	0	0
T7	157685	188	0	0
T8	494306	506	0	0
T9	12789	258	0	0
T10	2022	15	0	0
T11	13861	210	0	0
T12	3234	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	225196	0	0
GntImpliesValid_A	434339865	225196	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	225196	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3020810	0	0
ReadyAndValidImplyGrant_A	434339865	225196	0	0
ReqAndReadyImplyGrant_A	434339865	225196	0	0
ReqImpliesValid_A	434339865	604686	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	225196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3020810	0	0
T1	18111	156	0	0
T2	5152	53	0	0
T3	258089	113	0	0
T4	245651	52414	0	0
T7	157685	780	0	0
T8	494306	1719	0	0
T9	12789	219	0	0
T10	2022	13	0	0
T11	13861	210	0	0
T12	3234	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	604686	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	2639	0	0
T7	157685	214	0	0
T8	494306	1129	0	0
T9	12789	258	0	0
T10	2022	12	0	0
T11	13861	239	0	0
T12	3234	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	225196	0	0
T1	18111	155	0	0
T2	5152	52	0	0
T3	258089	26	0	0
T4	245651	145	0	0
T7	157685	182	0	0
T8	494306	514	0	0
T9	12789	238	0	0
T10	2022	12	0	0
T11	13861	224	0	0
T12	3234	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	210142	0	0
GntImpliesValid_A	434339865	210142	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	210142	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3013239	0	0
ReadyAndValidImplyGrant_A	434339865	210142	0	0
ReqAndReadyImplyGrant_A	434339865	210142	0	0
ReqImpliesValid_A	434339865	551833	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	210142	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3013239	0	0
T1	18111	145	0	0
T2	5152	43	0	0
T3	258089	105	0	0
T4	245651	45330	0	0
T7	157685	966	0	0
T8	494306	1552	0	0
T9	12789	197	0	0
T10	2022	7	0	0
T11	13861	196	0	0
T12	3234	25	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	551833	0	0
T1	18111	144	0	0
T2	5152	44	0	0
T3	258089	22	0	0
T4	245651	3543	0	0
T7	157685	267	0	0
T8	494306	1151	0	0
T9	12789	218	0	0
T10	2022	6	0	0
T11	13861	225	0	0
T12	3234	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	210142	0	0
T1	18111	144	0	0
T2	5152	43	0	0
T3	258089	22	0	0
T4	245651	136	0	0
T7	157685	217	0	0
T8	494306	475	0	0
T9	12789	207	0	0
T10	2022	6	0	0
T11	13861	210	0	0
T12	3234	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	216326	0	0
GntImpliesValid_A	434339865	216326	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	216326	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3020619	0	0
ReadyAndValidImplyGrant_A	434339865	216326	0	0
ReqAndReadyImplyGrant_A	434339865	216326	0	0
ReqImpliesValid_A	434339865	541844	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	216326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3020619	0	0
T1	18111	159	0	0
T2	5152	48	0	0
T3	258089	76	0	0
T4	245651	38630	0	0
T7	157685	845	0	0
T8	494306	1635	0	0
T9	12789	223	0	0
T10	2022	11	0	0
T11	13861	186	0	0
T12	3234	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	541844	0	0
T1	18111	162	0	0
T2	5152	51	0	0
T3	258089	21	0	0
T4	245651	2485	0	0
T7	157685	259	0	0
T8	494306	1155	0	0
T9	12789	248	0	0
T10	2022	10	0	0
T11	13861	209	0	0
T12	3234	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	216326	0	0
T1	18111	160	0	0
T2	5152	49	0	0
T3	258089	21	0	0
T4	245651	137	0	0
T7	157685	210	0	0
T8	494306	502	0	0
T9	12789	235	0	0
T10	2022	10	0	0
T11	13861	197	0	0
T12	3234	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	222135	0	0
GntImpliesValid_A	434339865	222135	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	222135	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3030371	0	0
ReadyAndValidImplyGrant_A	434339865	222135	0	0
ReqAndReadyImplyGrant_A	434339865	222135	0	0
ReqImpliesValid_A	434339865	617983	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	222135	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3030371	0	0
T1	18111	185	0	0
T2	5152	62	0	0
T3	258089	142	0	0
T4	245651	43697	0	0
T7	157685	921	0	0
T8	494306	1456	0	0
T9	12789	215	0	0
T10	2022	17	0	0
T11	13861	223	0	0
T12	3234	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	617983	0	0
T1	18111	188	0	0
T2	5152	63	0	0
T3	258089	37	0	0
T4	245651	3086	0	0
T7	157685	285	0	0
T8	494306	1070	0	0
T9	12789	234	0	0
T10	2022	18	0	0
T11	13861	244	0	0
T12	3234	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	222135	0	0
T1	18111	186	0	0
T2	5152	62	0	0
T3	258089	34	0	0
T4	245651	135	0	0
T7	157685	221	0	0
T8	494306	454	0	0
T9	12789	224	0	0
T10	2022	17	0	0
T11	13861	233	0	0
T12	3234	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	220216	0	0
GntImpliesValid_A	434339865	220216	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	220216	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3036832	0	0
ReadyAndValidImplyGrant_A	434339865	220216	0	0
ReqAndReadyImplyGrant_A	434339865	220216	0	0
ReqImpliesValid_A	434339865	558752	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	220216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3036832	0	0
T1	18111	166	0	0
T2	5152	44	0	0
T3	258089	73	0	0
T4	245651	49015	0	0
T7	157685	868	0	0
T8	494306	1474	0	0
T9	12789	226	0	0
T10	2022	16	0	0
T11	13861	203	0	0
T12	3234	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	558752	0	0
T1	18111	173	0	0
T2	5152	45	0	0
T3	258089	18	0	0
T4	245651	4843	0	0
T7	157685	233	0	0
T8	494306	1165	0	0
T9	12789	259	0	0
T10	2022	21	0	0
T11	13861	228	0	0
T12	3234	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	220216	0	0
T1	18111	169	0	0
T2	5152	44	0	0
T3	258089	18	0	0
T4	245651	159	0	0
T7	157685	206	0	0
T8	494306	470	0	0
T9	12789	242	0	0
T10	2022	18	0	0
T11	13861	215	0	0
T12	3234	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	209235	0	0
GntImpliesValid_A	434339865	209235	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	209235	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3040246	0	0
ReadyAndValidImplyGrant_A	434339865	209235	0	0
ReqAndReadyImplyGrant_A	434339865	209235	0	0
ReqImpliesValid_A	434339865	577977	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	209235	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3040246	0	0
T1	18111	163	0	0
T2	5152	47	0	0
T3	258089	109	0	0
T4	245651	47666	0	0
T7	157685	932	0	0
T8	494306	1	0	0
T9	12789	200	0	0
T10	2022	17	0	0
T11	13861	215	0	0
T12	3234	20	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	577977	0	0
T1	18111	162	0	0
T2	5152	52	0	0
T3	258089	34	0	0
T4	245651	3885	0	0
T7	157685	265	0	0
T8	494306	0	0	0
T9	12789	221	0	0
T10	2022	16	0	0
T11	13861	232	0	0
T12	3234	23	0	0
T13	0	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	209235	0	0
T1	18111	162	0	0
T2	5152	49	0	0
T3	258089	30	0	0
T4	245651	147	0	0
T7	157685	214	0	0
T8	494306	0	0	0
T9	12789	210	0	0
T10	2022	16	0	0
T11	13861	223	0	0
T12	3234	21	0	0
T13	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	233969	0	0
GntImpliesValid_A	434339865	233969	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	233969	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3146611	0	0
ReadyAndValidImplyGrant_A	434339865	233969	0	0
ReqAndReadyImplyGrant_A	434339865	233969	0	0
ReqImpliesValid_A	434339865	605938	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	233969	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3146611	0	0
T1	18111	165	0	0
T2	5152	96	0	0
T3	258089	59	0	0
T4	245651	48394	0	0
T7	157685	807	0	0
T8	494306	1	0	0
T9	12789	253	0	0
T10	2022	14	0	0
T11	13861	222	0	0
T12	3234	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	605938	0	0
T1	18111	166	0	0
T2	5152	109	0	0
T3	258089	16	0	0
T4	245651	2398	0	0
T7	157685	230	0	0
T8	494306	0	0	0
T9	12789	288	0	0
T10	2022	15	0	0
T11	13861	249	0	0
T12	3234	55	0	0
T13	0	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	233969	0	0
T1	18111	165	0	0
T2	5152	102	0	0
T3	258089	16	0	0
T4	245651	143	0	0
T7	157685	193	0	0
T8	494306	0	0	0
T9	12789	270	0	0
T10	2022	14	0	0
T11	13861	235	0	0
T12	3234	51	0	0
T13	0	37	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	208266	0	0
GntImpliesValid_A	434339865	208266	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	208266	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3008878	0	0
ReadyAndValidImplyGrant_A	434339865	208266	0	0
ReqAndReadyImplyGrant_A	434339865	208266	0	0
ReqImpliesValid_A	434339865	545008	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	208266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3008878	0	0
T1	18111	147	0	0
T2	5152	40	0	0
T3	258089	124	0	0
T4	245651	42480	0	0
T7	157685	974	0	0
T8	494306	1	0	0
T9	12789	231	0	0
T10	2022	18	0	0
T11	13861	229	0	0
T12	3234	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	545008	0	0
T1	18111	150	0	0
T2	5152	41	0	0
T3	258089	28	0	0
T4	245651	3168	0	0
T7	157685	255	0	0
T8	494306	0	0	0
T9	12789	250	0	0
T10	2022	17	0	0
T11	13861	264	0	0
T12	3234	31	0	0
T13	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	208266	0	0
T1	18111	148	0	0
T2	5152	40	0	0
T3	258089	28	0	0
T4	245651	142	0	0
T7	157685	227	0	0
T8	494306	0	0	0
T9	12789	240	0	0
T10	2022	17	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	33	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	217096	0	0
GntImpliesValid_A	434339865	217096	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	217096	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3054856	0	0
ReadyAndValidImplyGrant_A	434339865	217096	0	0
ReqAndReadyImplyGrant_A	434339865	217096	0	0
ReqImpliesValid_A	434339865	588421	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	217096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3054856	0	0
T1	18111	169	0	0
T2	5152	60	0	0
T3	258089	114	0	0
T4	245651	47168	0	0
T7	157685	911	0	0
T8	494306	1	0	0
T9	12789	232	0	0
T10	2022	9	0	0
T11	13861	229	0	0
T12	3234	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	588421	0	0
T1	18111	168	0	0
T2	5152	69	0	0
T3	258089	25	0	0
T4	245651	3797	0	0
T7	157685	263	0	0
T8	494306	0	0	0
T9	12789	267	0	0
T10	2022	8	0	0
T11	13861	246	0	0
T12	3234	31	0	0
T13	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217096	0	0
T1	18111	168	0	0
T2	5152	64	0	0
T3	258089	20	0	0
T4	245651	139	0	0
T7	157685	217	0	0
T8	494306	0	0	0
T9	12789	249	0	0
T10	2022	8	0	0
T11	13861	237	0	0
T12	3234	29	0	0
T13	0	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	206282	0	0
GntImpliesValid_A	434339865	206282	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	206282	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3028115	0	0
ReadyAndValidImplyGrant_A	434339865	206282	0	0
ReqAndReadyImplyGrant_A	434339865	206282	0	0
ReqImpliesValid_A	434339865	572114	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	206282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3028115	0	0
T1	18111	161	0	0
T2	5152	54	0	0
T3	258089	113	0	0
T4	245651	47969	0	0
T7	157685	842	0	0
T8	494306	1	0	0
T9	12789	229	0	0
T10	2022	16	0	0
T11	13861	225	0	0
T12	3234	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	572114	0	0
T1	18111	166	0	0
T2	5152	59	0	0
T3	258089	25	0	0
T4	245651	4584	0	0
T7	157685	245	0	0
T8	494306	0	0	0
T9	12789	256	0	0
T10	2022	15	0	0
T11	13861	244	0	0
T12	3234	36	0	0
T13	0	33	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	206282	0	0
T1	18111	163	0	0
T2	5152	56	0	0
T3	258089	25	0	0
T4	245651	145	0	0
T7	157685	194	0	0
T8	494306	0	0	0
T9	12789	242	0	0
T10	2022	15	0	0
T11	13861	234	0	0
T12	3234	35	0	0
T13	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	230215	0	0
GntImpliesValid_A	434339865	230215	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	230215	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3092604	0	0
ReadyAndValidImplyGrant_A	434339865	230215	0	0
ReqAndReadyImplyGrant_A	434339865	230215	0	0
ReqImpliesValid_A	434339865	590758	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	230215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3092604	0	0
T1	18111	183	0	0
T2	5152	56	0	0
T3	258089	138	0	0
T4	245651	44470	0	0
T7	157685	839	0	0
T8	494306	1	0	0
T9	12789	208	0	0
T10	2022	9	0	0
T11	13861	200	0	0
T12	3234	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	590758	0	0
T1	18111	182	0	0
T2	5152	61	0	0
T3	258089	26	0	0
T4	245651	3387	0	0
T7	157685	233	0	0
T8	494306	0	0	0
T9	12789	241	0	0
T10	2022	8	0	0
T11	13861	213	0	0
T12	3234	27	0	0
T13	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	230215	0	0
T1	18111	182	0	0
T2	5152	58	0	0
T3	258089	25	0	0
T4	245651	152	0	0
T7	157685	204	0	0
T8	494306	0	0	0
T9	12789	224	0	0
T10	2022	8	0	0
T11	13861	206	0	0
T12	3234	27	0	0
T13	0	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	217881	0	0
GntImpliesValid_A	434339865	217881	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	217881	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	3007315	0	0
ReadyAndValidImplyGrant_A	434339865	217881	0	0
ReqAndReadyImplyGrant_A	434339865	217881	0	0
ReqImpliesValid_A	434339865	540047	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	0	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	217881	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	3007315	0	0
T1	18111	148	0	0
T2	5152	49	0	0
T3	258089	139	0	0
T4	245651	48031	0	0
T7	157685	1034	0	0
T8	494306	1901	0	0
T9	12789	228	0	0
T10	2022	13	0	0
T11	13861	218	0	0
T12	3234	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	540047	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	49	0	0
T4	245651	3340	0	0
T7	157685	287	0	0
T8	494306	1171	0	0
T9	12789	259	0	0
T10	2022	12	0	0
T11	13861	237	0	0
T12	3234	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	217881	0	0
T1	18111	147	0	0
T2	5152	48	0	0
T3	258089	32	0	0
T4	245651	152	0	0
T7	157685	238	0	0
T8	494306	535	0	0
T9	12789	243	0	0
T10	2022	12	0	0
T11	13861	227	0	0
T12	3234	31	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	867325	0	0
GntImpliesValid_A	434339865	867325	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	867325	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	11432852	0	0
ReadyAndValidImplyGrant_A	434339865	867325	0	0
ReqAndReadyImplyGrant_A	434339865	867325	0	0
ReqImpliesValid_A	434339865	2337522	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	16836	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	867325	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	11432852	0	0
T1	18111	1	0	0
T2	5152	1	0	0
T3	258089	323	0	0
T4	245651	181614	0	0
T7	157685	2651	0	0
T8	494306	2273	0	0
T9	12789	1	0	0
T10	2022	1	0	0
T11	13861	1	0	0
T12	3234	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	2337522	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	109	0	0
T4	245651	19478	0	0
T7	157685	1030	0	0
T8	494306	900	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	16836	0	900
T1	18111	8	0	1
T2	5152	1	0	1
T3	258089	0	0	1
T4	245651	0	0	1
T7	157685	0	0	1
T8	494306	0	0	1
T9	12789	13	0	1
T10	2022	0	0	1
T11	13861	14	0	1
T12	3234	3	0	1
T14	0	35	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	157	0	0
T19	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867325	0	0
T1	18111	677	0	0
T2	5152	202	0	0
T3	258089	92	0	0
T4	245651	574	0	0
T7	157685	793	0	0
T8	494306	683	0	0
T9	12789	951	0	0
T10	2022	62	0	0
T11	13861	902	0	0
T12	3234	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	434339865	434206911	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	434339865	867220	0	0
GntImpliesValid_A	434339865	867220	0	0
GrantKnown_A	434339865	434206911	0	0
IdxKnown_A	434339865	434206911	0	0
IndexIsCorrect_A	434339865	867220	0	0
LockArbDecision_A	434339865	0	0	0
NoReadyValidNoGrant_A	434339865	364417863	0	0
ReadyAndValidImplyGrant_A	434339865	867220	0	0
ReqAndReadyImplyGrant_A	434339865	867220	0	0
ReqImpliesValid_A	434339865	13442463	0	0
ReqStaysHighUntilGranted0_M	434339865	0	0	0
RoundRobin_A	434339865	33753	0	900
ValidKnown_A	434339865	434206911	0	0
gen_data_port_assertion.DataFlow_A	434339865	867220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	364417863	0	0
T1	18111	1	0	0
T2	5152	1	0	0
T3	258089	214600	0	0
T4	245651	225430	0	0
T7	157685	131093	0	0
T8	494306	411749	0	0
T9	12789	1	0	0
T10	2022	1	0	0
T11	13861	1	0	0
T12	3234	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	13442463	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	441	0	0
T4	245651	197792	0	0
T7	157685	3474	0	0
T8	494306	2881	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	33753	0	900
T1	18111	5	0	1
T2	5152	1	0	1
T3	258089	0	0	1
T4	245651	0	0	1
T7	157685	0	0	1
T8	494306	0	0	1
T9	12789	18	0	1
T10	2022	0	0	1
T11	13861	18	0	1
T12	3234	2	0	1
T14	0	607	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	261	0	0
T19	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	434206911	0	0
T1	18111	18075	0	0
T2	5152	5114	0	0
T3	258089	258084	0	0
T4	245651	245645	0	0
T7	157685	157681	0	0
T8	494306	494302	0	0
T9	12789	12764	0	0
T10	2022	1974	0	0
T11	13861	13826	0	0
T12	3234	3175	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434339865	867220	0	0
T1	18111	674	0	0
T2	5152	177	0	0
T3	258089	99	0	0
T4	245651	560	0	0
T7	157685	782	0	0
T8	494306	650	0	0
T9	12789	970	0	0
T10	2022	57	0	0
T11	13861	842	0	0
T12	3234	107	0	0