Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1588976 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251995 1 T1 30 T2 83 T3 78


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 625726 1 T1 41 T2 161 T3 214
values[0x0] 591055 1 T1 52 T2 170 T3 202
values[0x1] 624190 1 T1 67 T2 148 T3 188


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1228128 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 612843 1 T1 64 T2 171 T3 201


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29178 1 T1 3 T2 23 T7 3
valid_sources[0x01] 28503 1 T1 1 T7 10 T8 57
valid_sources[0x02] 28416 1 T2 1 T7 8 T8 49
valid_sources[0x03] 28345 1 T1 1 T3 3 T7 9
valid_sources[0x04] 27997 1 T1 9 T2 3 T7 5
valid_sources[0x05] 28363 1 T1 5 T3 24 T7 7
valid_sources[0x06] 28002 1 T1 3 T2 11 T7 3
valid_sources[0x07] 28878 1 T1 2 T2 34 T3 1
valid_sources[0x08] 28896 1 T1 2 T2 32 T3 26
valid_sources[0x09] 28689 1 T1 6 T3 13 T7 9
valid_sources[0x0a] 28852 1 T2 24 T3 10 T7 6
valid_sources[0x0b] 29996 1 T2 1 T7 13 T8 41
valid_sources[0x0c] 28460 1 T1 2 T7 12 T8 50
valid_sources[0x0d] 27614 1 T1 5 T3 1 T7 6
valid_sources[0x0e] 28929 1 T1 2 T2 37 T7 3
valid_sources[0x0f] 28424 1 T3 10 T7 9 T8 48
valid_sources[0x10] 29107 1 T1 1 T2 6 T3 15
valid_sources[0x11] 29080 1 T1 3 T7 4 T8 57
valid_sources[0x12] 29307 1 T1 5 T2 1 T3 45
valid_sources[0x13] 28581 1 T1 2 T2 1 T3 51
valid_sources[0x14] 28837 1 T2 20 T3 17 T7 1
valid_sources[0x15] 29042 1 T1 4 T3 35 T7 13
valid_sources[0x16] 28696 1 T1 2 T3 22 T7 5
valid_sources[0x17] 28091 1 T1 2 T2 7 T3 36
valid_sources[0x18] 28228 1 T1 2 T7 8 T8 40
valid_sources[0x19] 28097 1 T3 3 T7 5 T8 53
valid_sources[0x1a] 29119 1 T1 6 T2 4 T3 2
valid_sources[0x1b] 28973 1 T2 2 T3 54 T7 6
valid_sources[0x1c] 29651 1 T1 3 T7 4 T8 28
valid_sources[0x1d] 29105 1 T2 1 T3 4 T7 6
valid_sources[0x1e] 28626 1 T1 5 T3 21 T7 7
valid_sources[0x1f] 29375 1 T1 3 T2 16 T3 34
valid_sources[0x20] 29091 1 T1 1 T3 2 T7 5


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26606 1 T1 1 T2 8 T3 10
values[0x0] all_enables biggest_size 198774 1 T1 22 T2 66 T3 59
values[0x1] all_enables biggest_size 26615 1 T1 7 T2 9 T3 9


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1593808 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 259747 1 T1 13 T2 86 T3 92


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 634855 1 T1 43 T2 228 T3 210
values[0x0] 584750 1 T1 43 T2 210 T3 214
values[0x1] 633950 1 T1 55 T2 216 T3 239


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1222899 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 630656 1 T1 38 T2 223 T3 223


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28963 1 T2 3 T3 4 T7 4
valid_sources[0x01] 29250 1 T1 2 T2 8 T3 6
valid_sources[0x02] 28624 1 T2 18 T3 6 T7 5
valid_sources[0x03] 28742 1 T2 10 T3 13 T7 14
valid_sources[0x04] 28839 1 T1 1 T2 9 T3 13
valid_sources[0x05] 28706 1 T1 1 T2 9 T3 10
valid_sources[0x06] 29068 1 T2 6 T3 5 T7 11
valid_sources[0x07] 28528 1 T2 6 T3 8 T7 7
valid_sources[0x08] 28821 1 T2 8 T3 16 T7 5
valid_sources[0x09] 29244 1 T2 1 T3 1 T7 8
valid_sources[0x0a] 29017 1 T2 7 T3 7 T7 7
valid_sources[0x0b] 29002 1 T2 10 T3 4 T7 7
valid_sources[0x0c] 28731 1 T2 14 T3 24 T7 5
valid_sources[0x0d] 27708 1 T2 12 T3 48 T7 8
valid_sources[0x0e] 28545 1 T1 10 T2 28 T3 8
valid_sources[0x0f] 28256 1 T2 14 T3 15 T7 7
valid_sources[0x10] 29607 1 T2 7 T3 8 T7 4
valid_sources[0x11] 29249 1 T2 9 T3 12 T7 8
valid_sources[0x12] 29362 1 T2 4 T7 5 T8 76
valid_sources[0x13] 28298 1 T1 1 T2 10 T3 5
valid_sources[0x14] 28830 1 T2 6 T3 7 T7 4
valid_sources[0x15] 29634 1 T1 13 T2 1 T3 13
valid_sources[0x16] 28721 1 T1 11 T2 14 T3 14
valid_sources[0x17] 28371 1 T2 15 T3 5 T7 8
valid_sources[0x18] 29183 1 T1 4 T2 6 T3 7
valid_sources[0x19] 28669 1 T2 10 T3 8 T7 7
valid_sources[0x1a] 29024 1 T2 4 T3 14 T7 1
valid_sources[0x1b] 29152 1 T2 6 T3 5 T7 8
valid_sources[0x1c] 29845 1 T2 8 T3 4 T7 3
valid_sources[0x1d] 29461 1 T1 13 T2 9 T3 16
valid_sources[0x1e] 28691 1 T2 6 T3 25 T7 9
valid_sources[0x1f] 29634 1 T2 13 T3 26 T7 7
valid_sources[0x20] 29333 1 T1 2 T2 15 T3 10


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27564 1 T1 1 T2 4 T3 7
values[0x0] all_enables biggest_size 205042 1 T1 11 T2 73 T3 76
values[0x1] all_enables biggest_size 27141 1 T1 1 T2 9 T3 9


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1598539 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 254495 1 T1 21 T2 75 T3 85


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 628789 1 T1 48 T2 196 T3 172
values[0x0] 595466 1 T1 47 T2 172 T3 191
values[0x1] 628779 1 T1 46 T2 202 T3 207


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1235829 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 617205 1 T1 51 T2 187 T3 183


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29147 1 T2 4 T3 9 T7 6
valid_sources[0x01] 28872 1 T2 14 T3 11 T7 9
valid_sources[0x02] 28785 1 T2 8 T3 14 T7 5
valid_sources[0x03] 29109 1 T2 16 T3 6 T7 4
valid_sources[0x04] 28731 1 T2 6 T3 7 T7 6
valid_sources[0x05] 28111 1 T2 23 T3 13 T7 7
valid_sources[0x06] 28659 1 T2 10 T3 8 T7 6
valid_sources[0x07] 29026 1 T2 1 T3 11 T7 3
valid_sources[0x08] 29337 1 T2 8 T3 9 T7 4
valid_sources[0x09] 29527 1 T2 11 T3 13 T7 4
valid_sources[0x0a] 28618 1 T2 20 T3 7 T7 6
valid_sources[0x0b] 29248 1 T1 19 T2 4 T3 10
valid_sources[0x0c] 28825 1 T1 17 T2 14 T3 8
valid_sources[0x0d] 28401 1 T2 5 T3 10 T7 5
valid_sources[0x0e] 28940 1 T2 31 T3 15 T7 6
valid_sources[0x0f] 28386 1 T2 9 T3 18 T7 12
valid_sources[0x10] 29091 1 T2 11 T3 5 T7 8
valid_sources[0x11] 29898 1 T2 3 T3 10 T7 3
valid_sources[0x12] 29178 1 T1 4 T2 7 T3 4
valid_sources[0x13] 29479 1 T1 35 T2 1 T3 8
valid_sources[0x14] 29756 1 T2 15 T3 5 T7 7
valid_sources[0x15] 28450 1 T2 4 T3 11 T7 7
valid_sources[0x16] 28211 1 T2 1 T3 8 T7 7
valid_sources[0x17] 28672 1 T2 4 T3 4 T7 3
valid_sources[0x18] 28550 1 T3 3 T7 6 T8 41
valid_sources[0x19] 28712 1 T2 3 T3 10 T7 7
valid_sources[0x1a] 29398 1 T2 3 T3 8 T7 3
valid_sources[0x1b] 28688 1 T2 8 T3 5 T7 14
valid_sources[0x1c] 29560 1 T2 2 T3 6 T7 3
valid_sources[0x1d] 29784 1 T3 14 T7 6 T8 49
valid_sources[0x1e] 28780 1 T2 7 T3 12 T7 6
valid_sources[0x1f] 28893 1 T2 9 T3 10 T7 4
valid_sources[0x20] 28835 1 T2 24 T3 7 T7 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26888 1 T1 4 T2 6 T3 9
values[0x0] all_enables biggest_size 200817 1 T1 17 T2 58 T3 70
values[0x1] all_enables biggest_size 26790 1 T2 11 T3 6 T7 10

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%