Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8079441	0	0
GntImpliesValid_A	2147483647	8079441	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8079441	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	510712623	0	0
ReadyAndValidImplyGrant_A	2147483647	8079441	0	0
ReqAndReadyImplyGrant_A	2147483647	8079441	0	0
ReqImpliesValid_A	2147483647	38277235	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	41765	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8079441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54648	53808	0	0
T2	412176	401904	0	0
T3	14409888	14408976	0	0
T7	8170392	8165208	0	0
T8	1798560	1798392	0	0
T9	123024	122088	0	0
T10	40008	39840	0	0
T11	67632	66528	0	0
T12	9830232	9830016	0	0
T13	3622032	3617256	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54648	53808	0	0
T2	412176	401904	0	0
T3	14409888	14408976	0	0
T7	8170392	8165208	0	0
T8	1798560	1798392	0	0
T9	123024	122088	0	0
T10	40008	39840	0	0
T11	67632	66528	0	0
T12	9830232	9830016	0	0
T13	3622032	3617256	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54648	53808	0	0
T2	412176	401904	0	0
T3	14409888	14408976	0	0
T7	8170392	8165208	0	0
T8	1798560	1798392	0	0
T9	123024	122088	0	0
T10	40008	39840	0	0
T11	67632	66528	0	0
T12	9830232	9830016	0	0
T13	3622032	3617256	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	510712623	0	0
T1	54648	654	0	0
T2	412176	23742	0	0
T3	14409888	507452	0	0
T7	8170392	445933	0	0
T8	1798560	89787	0	0
T9	123024	3613	0	0
T10	40008	487	0	0
T11	67632	1010	0	0
T12	9830232	3096378	0	0
T13	3622032	66055	0	0
T14	0	4269	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38277235	0	0
T1	54648	516	0	0
T2	412176	4588	0	0
T3	14409888	3151	0	0
T7	8170392	83431	0	0
T8	1798560	48924	0	0
T9	123024	3362	0	0
T10	40008	461	0	0
T11	67632	605	0	0
T12	9830232	499659	0	0
T13	3622032	107298	0	0
T14	0	1858	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41765	0	21600
T7	340433	8	0	1
T8	74940	0	0	1
T9	10252	10	0	2
T10	3334	0	0	2
T11	5636	0	0	2
T12	819186	0	0	2
T13	301836	1368	0	2
T14	101494	1	0	2
T15	236514	1021	0	1
T16	0	35	0	0
T17	0	53	0	0
T18	0	1	0	0
T19	0	8	0	0
T20	0	20	0	0
T21	0	29	0	0
T22	0	1	0	0
T23	0	8	0	0
T24	0	4	0	0
T25	0	64	0	0
T26	1690094	0	0	2
T27	111806	0	0	2
T28	2097	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54648	53808	0	0
T2	412176	401904	0	0
T3	14409888	14408976	0	0
T7	8170392	8165208	0	0
T8	1798560	1798392	0	0
T9	123024	122088	0	0
T10	40008	39840	0	0
T11	67632	66528	0	0
T12	9830232	9830016	0	0
T13	3622032	3617256	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8079441	0	0
T1	54648	442	0	0
T2	412176	1572	0	0
T3	14409888	1835	0	0
T7	8170392	26992	0	0
T8	1798560	8240	0	0
T9	123024	2855	0	0
T10	40008	436	0	0
T11	67632	508	0	0
T12	9830232	8353	0	0
T13	3622032	63335	0	0
T14	0	1314	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	885257	0	0
GntImpliesValid_A	465879021	885257	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	885257	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	13742276	0	0
ReadyAndValidImplyGrant_A	465879021	885257	0	0
ReqAndReadyImplyGrant_A	465879021	885257	0	0
ReqImpliesValid_A	465879021	2656010	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	885257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	13742276	0	0
T1	2277	41	0	0
T2	17174	1563	0	0
T3	600412	874	0	0
T7	340433	19435	0	0
T8	74940	4650	0	0
T9	5126	235	0	0
T10	1667	30	0	0
T11	2818	52	0	0
T12	409593	261691	0	0
T13	150918	4201	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	2656010	0	0
T1	2277	54	0	0
T2	17174	589	0	0
T3	600412	307	0	0
T7	340433	6684	0	0
T8	74940	986	0	0
T9	5126	324	0	0
T10	1667	47	0	0
T11	2818	79	0	0
T12	409593	30012	0	0
T13	150918	8120	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	885257	0	0
T1	2277	47	0	0
T2	17174	263	0	0
T3	600412	222	0	0
T7	340433	3257	0	0
T8	74940	646	0	0
T9	5126	279	0	0
T10	1667	38	0	0
T11	2818	65	0	0
T12	409593	924	0	0
T13	150918	6159	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	912836	0	0
GntImpliesValid_A	465879021	912836	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	912836	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	13943145	0	0
ReadyAndValidImplyGrant_A	465879021	912836	0	0
ReqAndReadyImplyGrant_A	465879021	912836	0	0
ReqImpliesValid_A	465879021	2752050	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	912836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	13943145	0	0
T1	2277	32	0	0
T2	17174	1337	0	0
T3	600412	731	0	0
T7	340433	19945	0	0
T8	74940	4915	0	0
T9	5126	242	0	0
T10	1667	36	0	0
T11	2818	46	0	0
T12	409593	262967	0	0
T13	150918	4274	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	2752050	0	0
T1	2277	49	0	0
T2	17174	286	0	0
T3	600412	325	0	0
T7	340433	6573	0	0
T8	74940	1206	0	0
T9	5126	409	0	0
T10	1667	45	0	0
T11	2818	57	0	0
T12	409593	29467	0	0
T13	150918	7753	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	912836	0	0
T1	2277	40	0	0
T2	17174	182	0	0
T3	600412	215	0	0
T7	340433	3360	0	0
T8	74940	704	0	0
T9	5126	325	0	0
T10	1667	40	0	0
T11	2818	51	0	0
T12	409593	916	0	0
T13	150918	6012	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	225729	0	0
GntImpliesValid_A	465879021	225729	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	225729	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3421029	0	0
ReadyAndValidImplyGrant_A	465879021	225729	0	0
ReqAndReadyImplyGrant_A	465879021	225729	0	0
ReqImpliesValid_A	465879021	634452	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	225729	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3421029	0	0
T1	2277	15	0	0
T2	17174	359	0	0
T3	600412	255	0	0
T7	340433	3982	0	0
T8	74940	1184	0	0
T9	5126	84	0	0
T10	1667	21	0	0
T11	2818	21	0	0
T12	409593	83770	0	0
T13	150918	1343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	634452	0	0
T1	2277	20	0	0
T2	17174	50	0	0
T3	600412	76	0	0
T7	340433	635	0	0
T8	74940	4462	0	0
T9	5126	93	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	2876	0	0
T13	150918	1780	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225729	0	0
T1	2277	17	0	0
T2	17174	43	0	0
T3	600412	55	0	0
T7	340433	540	0	0
T8	74940	482	0	0
T9	5126	88	0	0
T10	1667	20	0	0
T11	2818	20	0	0
T12	409593	255	0	0
T13	150918	1560	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	223301	0	0
GntImpliesValid_A	465879021	223301	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	223301	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3439803	0	0
ReadyAndValidImplyGrant_A	465879021	223301	0	0
ReqAndReadyImplyGrant_A	465879021	223301	0	0
ReqImpliesValid_A	465879021	649769	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	223301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3439803	0	0
T1	2277	13	0	0
T2	17174	1009	0	0
T3	600412	280	0	0
T7	340433	3822	0	0
T8	74940	1	0	0
T9	5126	74	0	0
T10	1667	17	0	0
T11	2818	13	0	0
T12	409593	65326	0	0
T13	150918	1218	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	649769	0	0
T1	2277	12	0	0
T2	17174	437	0	0
T3	600412	76	0	0
T7	340433	586	0	0
T8	74940	0	0	0
T9	5126	81	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	5879	0	0
T13	150918	5013	0	0
T14	0	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223301	0	0
T1	2277	12	0	0
T2	17174	164	0	0
T3	600412	59	0	0
T7	340433	508	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	16	0	0
T11	2818	12	0	0
T12	409593	211	0	0
T13	150918	3114	0	0
T14	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	221469	0	0
GntImpliesValid_A	465879021	221469	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	221469	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	5457540	0	0
ReadyAndValidImplyGrant_A	465879021	221469	0	0
ReqAndReadyImplyGrant_A	465879021	221469	0	0
ReqImpliesValid_A	465879021	1224296	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	221469	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	5457540	0	0
T1	2277	46	0	0
T2	17174	299	0	0
T3	600412	266	0	0
T7	340433	6465	0	0
T8	74940	0	0	0
T9	5126	321	0	0
T10	1667	68	0	0
T11	2818	90	0	0
T12	409593	135096	0	0
T13	150918	3400	0	0
T14	0	2347	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	1224296	0	0
T1	2277	9	0	0
T2	17174	46	0	0
T3	600412	57	0	0
T7	340433	625	0	0
T8	74940	0	0	0
T9	5126	123	0	0
T10	1667	13	0	0
T11	2818	30	0	0
T12	409593	8489	0	0
T13	150918	6878	0	0
T14	0	330	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	221469	0	0
T1	2277	9	0	0
T2	17174	26	0	0
T3	600412	43	0	0
T7	340433	527	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	13	0	0
T11	2818	15	0	0
T12	409593	251	0	0
T13	150918	1467	0	0
T14	0	141	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	224517	0	0
GntImpliesValid_A	465879021	224517	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	224517	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	5782471	0	0
ReadyAndValidImplyGrant_A	465879021	224517	0	0
ReqAndReadyImplyGrant_A	465879021	224517	0	0
ReqImpliesValid_A	465879021	1157785	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	224517	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	5782471	0	0
T1	2277	87	0	0
T2	17174	258	0	0
T3	600412	605	0	0
T7	340433	9397	0	0
T8	74940	1244	0	0
T9	5126	726	0	0
T10	1667	48	0	0
T11	2818	112	0	0
T12	409593	355640	0	0
T13	150918	21013	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	1157785	0	0
T1	2277	17	0	0
T2	17174	40	0	0
T3	600412	116	0	0
T7	340433	3637	0	0
T8	74940	1415	0	0
T9	5126	249	0	0
T10	1667	15	0	0
T11	2818	15	0	0
T12	409593	35594	0	0
T13	150918	19414	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	224517	0	0
T1	2277	11	0	0
T2	17174	29	0	0
T3	600412	58	0	0
T7	340433	1061	0	0
T8	74940	498	0	0
T9	5126	100	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	215	0	0
T13	150918	2055	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	220057	0	0
GntImpliesValid_A	465879021	220057	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	220057	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	5342715	0	0
ReadyAndValidImplyGrant_A	465879021	220057	0	0
ReqAndReadyImplyGrant_A	465879021	220057	0	0
ReqImpliesValid_A	465879021	1274475	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	220057	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	5342715	0	0
T1	2277	116	0	0
T2	17174	681	0	0
T3	600412	797	0	0
T7	340433	7248	0	0
T8	74940	0	0	0
T9	5126	306	0	0
T10	1667	33	0	0
T11	2818	150	0	0
T12	409593	134070	0	0
T13	150918	6260	0	0
T14	0	1185	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	1274475	0	0
T1	2277	34	0	0
T2	17174	35	0	0
T3	600412	106	0	0
T7	340433	698	0	0
T8	74940	0	0	0
T9	5126	116	0	0
T10	1667	12	0	0
T11	2818	43	0	0
T12	409593	10870	0	0
T13	150918	8548	0	0
T14	0	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220057	0	0
T1	2277	14	0	0
T2	17174	23	0	0
T3	600412	43	0	0
T7	340433	539	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	10	0	0
T11	2818	16	0	0
T12	409593	228	0	0
T13	150918	2122	0	0
T14	0	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	222254	0	0
GntImpliesValid_A	465879021	222254	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	222254	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	5631112	0	0
ReadyAndValidImplyGrant_A	465879021	222254	0	0
ReqAndReadyImplyGrant_A	465879021	222254	0	0
ReqImpliesValid_A	465879021	1222633	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	222254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	5631112	0	0
T1	2277	122	0	0
T2	17174	144	0	0
T3	600412	391	0	0
T7	340433	10671	0	0
T8	74940	0	0	0
T9	5126	547	0	0
T10	1667	42	0	0
T11	2818	326	0	0
T12	409593	86217	0	0
T13	150918	6252	0	0
T14	0	737	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	1222633	0	0
T1	2277	29	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	8845	0	0
T8	74940	0	0	0
T9	5126	143	0	0
T10	1667	12	0	0
T11	2818	49	0	0
T12	409593	4623	0	0
T13	150918	3863	0	0
T14	0	160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	222254	0	0
T1	2277	8	0	0
T2	17174	21	0	0
T3	600412	48	0	0
T7	340433	1112	0	0
T8	74940	0	0	0
T9	5126	77	0	0
T10	1667	12	0	0
T11	2818	21	0	0
T12	409593	253	0	0
T13	150918	1556	0	0
T14	0	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	217576	0	0
GntImpliesValid_A	465879021	217576	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	217576	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3409286	0	0
ReadyAndValidImplyGrant_A	465879021	217576	0	0
ReqAndReadyImplyGrant_A	465879021	217576	0	0
ReqImpliesValid_A	465879021	634504	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	217576	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3409286	0	0
T1	2277	8	0	0
T2	17174	217	0	0
T3	600412	189	0	0
T7	340433	3598	0	0
T8	74940	1	0	0
T9	5126	75	0	0
T10	1667	18	0	0
T11	2818	11	0	0
T12	409593	79272	0	0
T13	150918	1086	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	634504	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	75	0	0
T7	340433	602	0	0
T8	74940	0	0	0
T9	5126	86	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	4220	0	0
T13	150918	2235	0	0
T14	0	178	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	217576	0	0
T1	2277	7	0	0
T2	17174	24	0	0
T3	600412	47	0	0
T7	340433	503	0	0
T8	74940	0	0	0
T9	5126	80	0	0
T10	1667	17	0	0
T11	2818	10	0	0
T12	409593	254	0	0
T13	150918	1659	0	0
T14	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	223620	0	0
GntImpliesValid_A	465879021	223620	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	223620	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3461841	0	0
ReadyAndValidImplyGrant_A	465879021	223620	0	0
ReqAndReadyImplyGrant_A	465879021	223620	0	0
ReqImpliesValid_A	465879021	650735	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	223620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3461841	0	0
T1	2277	8	0	0
T2	17174	149	0	0
T3	600412	172	0	0
T7	340433	3742	0	0
T8	74940	1132	0	0
T9	5126	93	0	0
T10	1667	17	0	0
T11	2818	16	0	0
T12	409593	74152	0	0
T13	150918	2140	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	650735	0	0
T1	2277	9	0	0
T2	17174	38	0	0
T3	600412	58	0	0
T7	340433	560	0	0
T8	74940	2051	0	0
T9	5126	106	0	0
T10	1667	16	0	0
T11	2818	17	0	0
T12	409593	4331	0	0
T13	150918	3917	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223620	0	0
T1	2277	8	0	0
T2	17174	23	0	0
T3	600412	42	0	0
T7	340433	507	0	0
T8	74940	482	0	0
T9	5126	99	0	0
T10	1667	16	0	0
T11	2818	16	0	0
T12	409593	229	0	0
T13	150918	3027	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	220793	0	0
GntImpliesValid_A	465879021	220793	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	220793	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3443755	0	0
ReadyAndValidImplyGrant_A	465879021	220793	0	0
ReqAndReadyImplyGrant_A	465879021	220793	0	0
ReqImpliesValid_A	465879021	623061	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	220793	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3443755	0	0
T1	2277	23	0	0
T2	17174	244	0	0
T3	600412	226	0	0
T7	340433	3832	0	0
T8	74940	958	0	0
T9	5126	67	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	71806	0	0
T13	150918	954	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	623061	0	0
T1	2277	22	0	0
T2	17174	1082	0	0
T3	600412	50	0	0
T7	340433	575	0	0
T8	74940	4989	0	0
T9	5126	80	0	0
T10	1667	11	0	0
T11	2818	11	0	0
T12	409593	3912	0	0
T13	150918	1201	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	220793	0	0
T1	2277	22	0	0
T2	17174	128	0	0
T3	600412	48	0	0
T7	340433	507	0	0
T8	74940	514	0	0
T9	5126	73	0	0
T10	1667	11	0	0
T11	2818	10	0	0
T12	409593	216	0	0
T13	150918	1076	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	219840	0	0
GntImpliesValid_A	465879021	219840	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	219840	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3411310	0	0
ReadyAndValidImplyGrant_A	465879021	219840	0	0
ReqAndReadyImplyGrant_A	465879021	219840	0	0
ReqImpliesValid_A	465879021	643436	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	219840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3411310	0	0
T1	2277	15	0	0
T2	17174	136	0	0
T3	600412	221	0	0
T7	340433	5521	0	0
T8	74940	1419	0	0
T9	5126	70	0	0
T10	1667	22	0	0
T11	2818	18	0	0
T12	409593	68129	0	0
T13	150918	1037	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	643436	0	0
T1	2277	16	0	0
T2	17174	18	0	0
T3	600412	76	0	0
T7	340433	2912	0	0
T8	74940	1804	0	0
T9	5126	81	0	0
T10	1667	23	0	0
T11	2818	17	0	0
T12	409593	1820	0	0
T13	150918	2218	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	219840	0	0
T1	2277	15	0	0
T2	17174	18	0	0
T3	600412	54	0	0
T7	340433	1076	0	0
T8	74940	506	0	0
T9	5126	75	0	0
T10	1667	22	0	0
T11	2818	17	0	0
T12	409593	226	0	0
T13	150918	1626	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	226937	0	0
GntImpliesValid_A	465879021	226937	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	226937	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3444344	0	0
ReadyAndValidImplyGrant_A	465879021	226937	0	0
ReqAndReadyImplyGrant_A	465879021	226937	0	0
ReqImpliesValid_A	465879021	640329	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	226937	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3444344	0	0
T1	2277	13	0	0
T2	17174	193	0	0
T3	600412	218	0	0
T7	340433	5203	0	0
T8	74940	1070	0	0
T9	5126	83	0	0
T10	1667	13	0	0
T11	2818	11	0	0
T12	409593	76583	0	0
T13	150918	1515	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	640329	0	0
T1	2277	14	0	0
T2	17174	58	0	0
T3	600412	49	0	0
T7	340433	5634	0	0
T8	74940	4067	0	0
T9	5126	100	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	4851	0	0
T13	150918	2864	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226937	0	0
T1	2277	13	0	0
T2	17174	27	0	0
T3	600412	41	0	0
T7	340433	1071	0	0
T8	74940	459	0	0
T9	5126	91	0	0
T10	1667	12	0	0
T11	2818	10	0	0
T12	409593	224	0	0
T13	150918	2188	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	225475	0	0
GntImpliesValid_A	465879021	225475	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	225475	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3456834	0	0
ReadyAndValidImplyGrant_A	465879021	225475	0	0
ReqAndReadyImplyGrant_A	465879021	225475	0	0
ReqImpliesValid_A	465879021	645753	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	225475	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3456834	0	0
T1	2277	7	0	0
T2	17174	170	0	0
T3	600412	195	0	0
T7	340433	5139	0	0
T8	74940	1151	0	0
T9	5126	78	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	85584	0	0
T13	150918	1174	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	645753	0	0
T1	2277	6	0	0
T2	17174	30	0	0
T3	600412	49	0	0
T7	340433	4992	0	0
T8	74940	4780	0	0
T9	5126	83	0	0
T10	1667	8	0	0
T11	2818	14	0	0
T12	409593	4197	0	0
T13	150918	2013	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	225475	0	0
T1	2277	6	0	0
T2	17174	25	0	0
T3	600412	46	0	0
T7	340433	998	0	0
T8	74940	522	0	0
T9	5126	80	0	0
T10	1667	7	0	0
T11	2818	13	0	0
T12	409593	253	0	0
T13	150918	1592	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	223167	0	0
GntImpliesValid_A	465879021	223167	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	223167	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3397422	0	0
ReadyAndValidImplyGrant_A	465879021	223167	0	0
ReqAndReadyImplyGrant_A	465879021	223167	0	0
ReqImpliesValid_A	465879021	653316	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	223167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3397422	0	0
T1	2277	17	0	0
T2	17174	204	0	0
T3	600412	204	0	0
T7	340433	3773	0	0
T8	74940	2286	0	0
T9	5126	56	0	0
T10	1667	16	0	0
T11	2818	8	0	0
T12	409593	73497	0	0
T13	150918	1885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	653316	0	0
T1	2277	18	0	0
T2	17174	34	0	0
T3	600412	58	0	0
T7	340433	533	0	0
T8	74940	9498	0	0
T9	5126	59	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	5517	0	0
T13	150918	2438	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	223167	0	0
T1	2277	17	0	0
T2	17174	27	0	0
T3	600412	47	0	0
T7	340433	482	0	0
T8	74940	1035	0	0
T9	5126	57	0	0
T10	1667	15	0	0
T11	2818	7	0	0
T12	409593	240	0	0
T13	150918	2160	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	228350	0	0
GntImpliesValid_A	465879021	228350	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	228350	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3443362	0	0
ReadyAndValidImplyGrant_A	465879021	228350	0	0
ReqAndReadyImplyGrant_A	465879021	228350	0	0
ReqImpliesValid_A	465879021	627545	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	228350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3443362	0	0
T1	2277	11	0	0
T2	17174	249	0	0
T3	600412	203	0	0
T7	340433	4037	0	0
T8	74940	1	0	0
T9	5126	76	0	0
T10	1667	10	0	0
T11	2818	15	0	0
T12	409593	75936	0	0
T13	150918	1682	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	627545	0	0
T1	2277	10	0	0
T2	17174	39	0	0
T3	600412	50	0	0
T7	340433	594	0	0
T8	74940	0	0	0
T9	5126	83	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	3182	0	0
T13	150918	2491	0	0
T14	0	160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	228350	0	0
T1	2277	10	0	0
T2	17174	32	0	0
T3	600412	47	0	0
T7	340433	535	0	0
T8	74940	0	0	0
T9	5126	79	0	0
T10	1667	9	0	0
T11	2818	14	0	0
T12	409593	221	0	0
T13	150918	2085	0	0
T14	0	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	249025	0	0
GntImpliesValid_A	465879021	249025	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	249025	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3499609	0	0
ReadyAndValidImplyGrant_A	465879021	249025	0	0
ReqAndReadyImplyGrant_A	465879021	249025	0	0
ReqImpliesValid_A	465879021	677517	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	249025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3499609	0	0
T1	2277	10	0	0
T2	17174	199	0	0
T3	600412	237	0	0
T7	340433	4142	0	0
T8	74940	1	0	0
T9	5126	84	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	78133	0	0
T13	150918	1903	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	677517	0	0
T1	2277	13	0	0
T2	17174	22	0	0
T3	600412	55	0	0
T7	340433	599	0	0
T8	74940	0	0	0
T9	5126	97	0	0
T10	1667	14	0	0
T11	2818	19	0	0
T12	409593	6666	0	0
T13	150918	3966	0	0
T14	0	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	249025	0	0
T1	2277	11	0	0
T2	17174	22	0	0
T3	600412	51	0	0
T7	340433	549	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	223	0	0
T13	150918	2933	0	0
T14	0	134	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	215143	0	0
GntImpliesValid_A	465879021	215143	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	215143	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3443158	0	0
ReadyAndValidImplyGrant_A	465879021	215143	0	0
ReqAndReadyImplyGrant_A	465879021	215143	0	0
ReqImpliesValid_A	465879021	584846	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	215143	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3443158	0	0
T1	2277	13	0	0
T2	17174	169	0	0
T3	600412	221	0	0
T7	340433	4852	0	0
T8	74940	1	0	0
T9	5126	65	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	73692	0	0
T13	150918	974	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	584846	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	47	0	0
T7	340433	2480	0	0
T8	74940	0	0	0
T9	5126	76	0	0
T10	1667	14	0	0
T11	2818	13	0	0
T12	409593	5438	0	0
T13	150918	1221	0	0
T14	0	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215143	0	0
T1	2277	12	0	0
T2	17174	25	0	0
T3	600412	41	0	0
T7	340433	1007	0	0
T8	74940	0	0	0
T9	5126	70	0	0
T10	1667	13	0	0
T11	2818	12	0	0
T12	409593	229	0	0
T13	150918	1096	0	0
T14	0	137	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	215794	0	0
GntImpliesValid_A	465879021	215794	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	215794	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3439515	0	0
ReadyAndValidImplyGrant_A	465879021	215794	0	0
ReqAndReadyImplyGrant_A	465879021	215794	0	0
ReqImpliesValid_A	465879021	612350	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	215794	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3439515	0	0
T1	2277	12	0	0
T2	17174	162	0	0
T3	600412	278	0	0
T7	340433	4070	0	0
T8	74940	1281	0	0
T9	5126	93	0	0
T10	1667	10	0	0
T11	2818	19	0	0
T12	409593	69707	0	0
T13	150918	816	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	612350	0	0
T1	2277	13	0	0
T2	17174	24	0	0
T3	600412	77	0	0
T7	340433	611	0	0
T8	74940	5221	0	0
T9	5126	100	0	0
T10	1667	9	0	0
T11	2818	20	0	0
T12	409593	3808	0	0
T13	150918	3061	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	215794	0	0
T1	2277	12	0	0
T2	17174	24	0	0
T3	600412	60	0	0
T7	340433	525	0	0
T8	74940	561	0	0
T9	5126	96	0	0
T10	1667	9	0	0
T11	2818	19	0	0
T12	409593	202	0	0
T13	150918	1937	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	226631	0	0
GntImpliesValid_A	465879021	226631	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	226631	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3484950	0	0
ReadyAndValidImplyGrant_A	465879021	226631	0	0
ReqAndReadyImplyGrant_A	465879021	226631	0	0
ReqImpliesValid_A	465879021	633272	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	226631	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3484950	0	0
T1	2277	12	0	0
T2	17174	222	0	0
T3	600412	221	0	0
T7	340433	5449	0	0
T8	74940	1	0	0
T9	5126	83	0	0
T10	1667	14	0	0
T11	2818	17	0	0
T12	409593	79646	0	0
T13	150918	608	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	633272	0	0
T1	2277	11	0	0
T2	17174	34	0	0
T3	600412	50	0	0
T7	340433	2726	0	0
T8	74940	0	0	0
T9	5126	98	0	0
T10	1667	13	0	0
T11	2818	18	0	0
T12	409593	4835	0	0
T13	150918	613	0	0
T14	0	163	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	226631	0	0
T1	2277	11	0	0
T2	17174	33	0	0
T3	600412	50	0	0
T7	340433	1060	0	0
T8	74940	0	0	0
T9	5126	90	0	0
T10	1667	13	0	0
T11	2818	17	0	0
T12	409593	250	0	0
T13	150918	609	0	0
T14	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	230072	0	0
GntImpliesValid_A	465879021	230072	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	230072	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3485301	0	0
ReadyAndValidImplyGrant_A	465879021	230072	0	0
ReqAndReadyImplyGrant_A	465879021	230072	0	0
ReqImpliesValid_A	465879021	650332	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	230072	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3485301	0	0
T1	2277	18	0	0
T2	17174	459	0	0
T3	600412	169	0	0
T7	340433	3713	0	0
T8	74940	1150	0	0
T9	5126	70	0	0
T10	1667	14	0	0
T11	2818	15	0	0
T12	409593	69423	0	0
T13	150918	594	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	650332	0	0
T1	2277	19	0	0
T2	17174	110	0	0
T3	600412	56	0	0
T7	340433	565	0	0
T8	74940	1956	0	0
T9	5126	75	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	2240	0	0
T13	150918	603	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	230072	0	0
T1	2277	18	0	0
T2	17174	55	0	0
T3	600412	51	0	0
T7	340433	503	0	0
T8	74940	486	0	0
T9	5126	72	0	0
T10	1667	13	0	0
T11	2818	14	0	0
T12	409593	228	0	0
T13	150918	597	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	233870	0	0
GntImpliesValid_A	465879021	233870	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	233870	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	3556549	0	0
ReadyAndValidImplyGrant_A	465879021	233870	0	0
ReqAndReadyImplyGrant_A	465879021	233870	0	0
ReqImpliesValid_A	465879021	688651	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	0	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	233870	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	3556549	0	0
T1	2277	13	0	0
T2	17174	161	0	0
T3	600412	181	0	0
T7	340433	6027	0	0
T8	74940	1	0	0
T9	5126	83	0	0
T10	1667	11	0	0
T11	2818	15	0	0
T12	409593	80400	0	0
T13	150918	1722	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	688651	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	62	0	0
T7	340433	3842	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	4059	0	0
T13	150918	2485	0	0
T14	0	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	233870	0	0
T1	2277	12	0	0
T2	17174	23	0	0
T3	600412	50	0	0
T7	340433	985	0	0
T8	74940	0	0	0
T9	5126	82	0	0
T10	1667	10	0	0
T11	2818	14	0	0
T12	409593	233	0	0
T13	150918	2102	0	0
T14	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	913897	0	0
GntImpliesValid_A	465879021	913897	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	913897	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	13195401	0	0
ReadyAndValidImplyGrant_A	465879021	913897	0	0
ReqAndReadyImplyGrant_A	465879021	913897	0	0
ReqImpliesValid_A	465879021	2644045	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	18217	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	913897	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	13195401	0	0
T1	2277	1	0	0
T2	17174	1031	0	0
T3	600412	617	0	0
T7	340433	18546	0	0
T8	74940	4081	0	0
T9	5126	1	0	0
T10	1667	1	0	0
T11	2818	1	0	0
T12	409593	291193	0	0
T13	150918	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	2644045	0	0
T1	2277	59	0	0
T2	17174	258	0	0
T3	600412	275	0	0
T7	340433	8056	0	0
T8	74940	1019	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	24789	0	0
T13	150918	8418	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	18217	0	900
T7	340433	8	0	1
T8	74940	0	0	1
T9	5126	4	0	1
T10	1667	0	0	1
T11	2818	0	0	1
T12	409593	0	0	1
T13	150918	1087	0	1
T14	50747	0	0	1
T15	0	544	0	0
T16	0	15	0	0
T17	0	53	0	0
T21	0	19	0	0
T23	0	8	0	0
T24	0	4	0	0
T25	0	64	0	0
T26	845047	0	0	1
T27	55903	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	913897	0	0
T1	2277	59	0	0
T2	17174	173	0	0
T3	600412	206	0	0
T7	340433	3185	0	0
T8	74940	680	0	0
T9	5126	316	0	0
T10	1667	45	0	0
T11	2818	46	0	0
T12	409593	987	0	0
T13	150918	8418	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	465879021	465757945	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	465879021	873831	0	0
GntImpliesValid_A	465879021	873831	0	0
GrantKnown_A	465879021	465757945	0	0
IdxKnown_A	465879021	465757945	0	0
IndexIsCorrect_A	465879021	873831	0	0
LockArbDecision_A	465879021	0	0	0
NoReadyValidNoGrant_A	465879021	392379895	0	0
ReadyAndValidImplyGrant_A	465879021	873831	0	0
ReqAndReadyImplyGrant_A	465879021	873831	0	0
ReqImpliesValid_A	465879021	15096073	0	0
ReqStaysHighUntilGranted0_M	465879021	0	0	0
RoundRobin_A	465879021	23548	0	900
ValidKnown_A	465879021	465757945	0	0
gen_data_port_assertion.DataFlow_A	465879021	873831	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	392379895	0	0
T1	2277	1	0	0
T2	17174	14127	0	0
T3	600412	499701	0	0
T7	340433	283324	0	0
T8	74940	63259	0	0
T9	5126	1	0	0
T10	1667	1	0	0
T11	2818	1	0	0
T12	409593	364448	0	0
T13	150918	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	15096073	0	0
T1	2277	51	0	0
T2	17174	1265	0	0
T3	600412	953	0	0
T7	340433	19867	0	0
T8	74940	5470	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	287984	0	0
T13	150918	6185	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	23548	0	900
T9	5126	6	0	1
T10	1667	0	0	1
T11	2818	0	0	1
T12	409593	0	0	1
T13	150918	281	0	1
T14	50747	1	0	1
T15	236514	477	0	1
T16	0	20	0	0
T18	0	1	0	0
T19	0	8	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	0	1	0	0
T26	845047	0	0	1
T27	55903	0	0	1
T28	2097	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	465757945	0	0
T1	2277	2242	0	0
T2	17174	16746	0	0
T3	600412	600374	0	0
T7	340433	340217	0	0
T8	74940	74933	0	0
T9	5126	5087	0	0
T10	1667	1660	0	0
T11	2818	2772	0	0
T12	409593	409584	0	0
T13	150918	150719	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465879021	873831	0	0
T1	2277	51	0	0
T2	17174	162	0	0
T3	600412	211	0	0
T7	340433	2595	0	0
T8	74940	665	0	0
T9	5126	302	0	0
T10	1667	52	0	0
T11	2818	56	0	0
T12	409593	885	0	0
T13	150918	6185	0	0