Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_main_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_fixed_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_usb_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_spi_host0_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_spi_host1_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_main_ni |
Yes |
Yes |
T2,T7,T13 |
Yes |
T1,T2,T3 |
INPUT |
rst_fixed_ni |
Yes |
Yes |
T2,T7,T13 |
Yes |
T1,T2,T3 |
INPUT |
rst_usb_ni |
Yes |
Yes |
T2,T7,T13 |
Yes |
T1,T2,T3 |
INPUT |
rst_spi_host0_ni |
Yes |
Yes |
T2,T7,T13 |
Yes |
T1,T2,T3 |
INPUT |
rst_spi_host1_ni |
Yes |
Yes |
T2,T7,T13 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.d_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T7,T8 |
Yes |
T2,T7,T8 |
INPUT |
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] |
Yes |
Yes |
T2,T7,T8 |
Yes |
T2,T7,T8 |
INPUT |
tl_rv_core_ibex__corei_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__corei_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__corei_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__corei_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__corei_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__corei_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__corei_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__corei_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_i.d_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T7,T14 |
Yes |
T1,T7,T14 |
INPUT |
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] |
Yes |
Yes |
T1,T7,T14 |
Yes |
T1,T7,T14 |
INPUT |
tl_rv_core_ibex__cored_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__cored_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__cored_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cored_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cored_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cored_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cored_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cored_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_i.d_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
INPUT |
tl_rv_dm__sba_i.a_user.rsvd[4:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
INPUT |
tl_rv_dm__sba_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__sba_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__sba_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__sba_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__sba_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__sba_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__sba_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__sba_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rv_dm__regs_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rv_dm__regs_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_address[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_address[20:4] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_address[21] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_address[23:22] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__regs_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__regs_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_error |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
INPUT |
tl_rv_dm__regs_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__regs_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__regs_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__regs_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__regs_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rv_dm__mem_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rv_dm__mem_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_address[11:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_address[15:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__mem_o.a_address[16] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_address[31:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__mem_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__mem_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_dm__mem_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_dm__mem_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__mem_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__mem_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_dm__mem_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_dm__mem_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rom_ctrl__rom_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rom_ctrl__rom_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_address[15:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_address[31:16] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__rom_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__rom_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__rom_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__rom_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__rom_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__rom_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__rom_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__rom_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rom_ctrl__regs_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_address[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_address[16:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_address[20:17] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rom_ctrl__regs_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rom_ctrl__regs_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__regs_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__regs_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rom_ctrl__regs_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rom_ctrl__regs_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_peri_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_peri_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_address[22:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_peri_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_peri_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_peri_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_peri_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_peri_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T2,T3,T7 |
INPUT |
tl_peri_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_peri_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_peri_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_peri_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_peri_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_spi_host0_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_spi_host0_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_address[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_spi_host0_o.a_address[19:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host0_o.a_address[21:20] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_address[29:22] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host0_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host0_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host0_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host0_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host0_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host0_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host0_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host0_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host0_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_spi_host1_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_spi_host1_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_address[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_address[16] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_address[19:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_address[21:20] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_address[29:22] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_spi_host1_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_spi_host1_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host1_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host1_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_spi_host1_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_spi_host1_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_usbdev_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_usbdev_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_address[11:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_usbdev_o.a_address[16:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_address[17] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_address[19:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_address[21:20] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_address[29:22] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_usbdev_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_usbdev_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_usbdev_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_usbdev_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_usbdev_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_usbdev_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_flash_ctrl__core_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_flash_ctrl__core_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_address[8:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_flash_ctrl__core_o.a_address[23:9] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__core_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__core_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__core_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__core_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__core_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__core_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__core_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T2,T3,T7 |
INPUT |
tl_flash_ctrl__core_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__core_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__core_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__core_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_flash_ctrl__prim_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_address[6:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_flash_ctrl__prim_o.a_address[14:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_address[15] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_address[23:16] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__prim_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__prim_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__prim_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__prim_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__prim_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__prim_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_flash_ctrl__mem_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_flash_ctrl__mem_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_address[19:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_address[28:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__mem_o.a_address[29] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_address[31:30] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__mem_o.a_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_flash_ctrl__mem_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__mem_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_flash_ctrl__mem_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_flash_ctrl__mem_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
INPUT |
tl_flash_ctrl__mem_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__mem_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__mem_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_flash_ctrl__mem_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_flash_ctrl__mem_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_hmac_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_hmac_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[12:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[15:13] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_address[16] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[19:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_hmac_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_hmac_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_hmac_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_hmac_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_hmac_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_hmac_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_kmac_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_kmac_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[11:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[16:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_address[17] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[19:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_kmac_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_kmac_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_kmac_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_kmac_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_kmac_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_kmac_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_aes_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_aes_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_address[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_address[19:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_aes_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_aes_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_aes_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_aes_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_aes_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_aes_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_entropy_src_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_entropy_src_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[16:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_address[18:17] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[19] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_entropy_src_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_entropy_src_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_entropy_src_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_entropy_src_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_entropy_src_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_entropy_src_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_csrng_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_csrng_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[6:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_csrng_o.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_address[16] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[17] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_address[18] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[19] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_csrng_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_csrng_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_csrng_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_csrng_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_csrng_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_csrng_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_edn0_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_edn0_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_address[6:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_edn0_o.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_address[18:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_address[19] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn0_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn0_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn0_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn0_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn0_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn0_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_edn1_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_edn1_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_address[6:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T2,T3,T7 |
OUTPUT |
tl_edn1_o.a_address[18:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_address[20:19] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_edn1_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_edn1_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn1_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn1_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_edn1_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_edn1_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rv_plic_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rv_plic_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_address[27:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_address[29:28] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_plic_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_plic_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_plic_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_plic_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_plic_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_plic_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_plic_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_plic_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_plic_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_otbn_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_otbn_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_address[17:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_address[19:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_otbn_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_otbn_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_otbn_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_otbn_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_otbn_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_otbn_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_keymgr_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_keymgr_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[17:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_address[18] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[19] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_address[20] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_keymgr_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_keymgr_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_keymgr_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_keymgr_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_keymgr_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_keymgr_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[15:8] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[20:16] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_rv_core_ibex__cfg_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_rv_core_ibex__cfg_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__cfg_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__cfg_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_rv_core_ibex__cfg_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_rv_core_ibex__cfg_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[17:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[20:18] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[24] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[30] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__regs_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__regs_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_source[5:0] |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__regs_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__regs_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__regs_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__regs_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_o.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_user.rsvd[2:0] |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:3] |
No |
No |
|
No |
|
OUTPUT |
tl_sram_ctrl_main__ram_o.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_address[16:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_address[27:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__ram_o.a_address[28] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_address[31:29] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__ram_o.a_source[5:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__ram_o.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_sram_ctrl_main__ram_o.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_o.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_sram_ctrl_main__ram_i.a_ready |
Yes |
Yes |
T2,T3,T7 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_sink |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_source[5:0] |
Yes |
Yes |
*T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__ram_i.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__ram_i.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_sram_ctrl_main__ram_i.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_sram_ctrl_main__ram_i.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
scanmode_i[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |