Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1535101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244273

1

T1

385

T2

25

T3

809

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	603468	1			T1	891		T2	44		T3	1872
values[0x0]	572430	1			T1	917		T2	48		T3	1822
values[0x1]	603476	1			T1	871		T2	51		T3	1927

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1186917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

592457

1

T1

895

T2

50

T3

1885

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27744	1			T1	37		T2	4		T3	80
valid_sources[0x01]	28096	1			T1	41		T3	56		T7	56
valid_sources[0x02]	28805	1			T1	53		T3	225		T7	86
valid_sources[0x03]	27421	1			T1	40		T3	83		T7	14
valid_sources[0x04]	26913	1			T1	45		T3	84		T8	1
valid_sources[0x05]	27246	1			T1	47		T2	12		T3	18
valid_sources[0x06]	27877	1			T1	35		T2	4		T3	45
valid_sources[0x07]	27734	1			T1	53		T3	132		T7	26
valid_sources[0x08]	28849	1			T1	41		T2	1		T3	160
valid_sources[0x09]	27416	1			T1	29		T3	137		T7	49
valid_sources[0x0a]	27364	1			T1	39		T3	118		T8	1
valid_sources[0x0b]	26619	1			T1	47		T3	51		T7	38
valid_sources[0x0c]	27792	1			T1	35		T3	80		T7	24
valid_sources[0x0d]	27286	1			T1	41		T2	2		T3	102
valid_sources[0x0e]	28381	1			T1	45		T3	91		T7	29
valid_sources[0x0f]	27038	1			T1	56		T3	13		T8	1
valid_sources[0x10]	27987	1			T1	43		T3	12		T7	17
valid_sources[0x11]	26951	1			T1	37		T3	18		T7	20
valid_sources[0x12]	27940	1			T1	39		T3	78		T7	13
valid_sources[0x13]	28220	1			T1	44		T3	163		T8	1
valid_sources[0x14]	27332	1			T1	31		T3	131		T9	197
valid_sources[0x15]	28253	1			T1	40		T3	160		T7	14
valid_sources[0x16]	27832	1			T1	45		T3	45		T9	129
valid_sources[0x17]	27455	1			T1	54		T2	5		T3	188
valid_sources[0x18]	27749	1			T1	51		T3	57		T7	37
valid_sources[0x19]	28154	1			T1	39		T3	72		T9	184
valid_sources[0x1a]	27303	1			T1	44		T2	34		T3	56
valid_sources[0x1b]	28598	1			T1	34		T3	72		T7	31
valid_sources[0x1c]	27444	1			T1	50		T3	91		T7	29
valid_sources[0x1d]	28222	1			T1	41		T3	45		T7	55
valid_sources[0x1e]	27331	1			T1	40		T2	4		T3	81
valid_sources[0x1f]	27292	1			T1	43		T3	84		T7	22
valid_sources[0x20]	27660	1			T1	44		T3	98		T9	193

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25791

1

T1

35

T2

3

T3

79

values[0x0]

all_enables

biggest_size

192654

1

T1

316

T2

20

T3

643

values[0x1]

all_enables

biggest_size

25828

1

T1

34

T2

2

T3

87

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1550049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251916

1

T1

357

T2

22

T3

829

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617794	1			T1	887		T2	40		T3	2107
values[0x0]	569108	1			T1	857		T2	36		T3	1925
values[0x1]	615063	1			T1	843		T2	50		T3	2014

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1188630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613335

1

T1

883

T2

49

T3

2001

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27734	1			T1	37		T2	3		T3	81
valid_sources[0x01]	28702	1			T1	43		T3	78		T7	54
valid_sources[0x02]	27936	1			T1	58		T2	4		T3	110
valid_sources[0x03]	28742	1			T1	28		T2	5		T3	90
valid_sources[0x04]	27733	1			T1	46		T2	1		T3	90
valid_sources[0x05]	28736	1			T1	38		T2	1		T3	67
valid_sources[0x06]	29145	1			T1	48		T3	84		T9	337
valid_sources[0x07]	28272	1			T1	39		T2	4		T3	124
valid_sources[0x08]	28602	1			T1	37		T2	1		T3	134
valid_sources[0x09]	28451	1			T1	34		T2	1		T3	130
valid_sources[0x0a]	28750	1			T1	48		T2	3		T3	117
valid_sources[0x0b]	28082	1			T1	39		T2	1		T3	81
valid_sources[0x0c]	27872	1			T1	46		T2	3		T3	64
valid_sources[0x0d]	28565	1			T1	42		T2	1		T3	115
valid_sources[0x0e]	28255	1			T1	50		T2	3		T3	105
valid_sources[0x0f]	27702	1			T1	31		T2	4		T3	79
valid_sources[0x10]	28006	1			T1	34		T2	8		T3	70
valid_sources[0x11]	27661	1			T1	43		T3	79		T7	7
valid_sources[0x12]	28332	1			T1	34		T2	1		T3	102
valid_sources[0x13]	27455	1			T1	56		T2	1		T3	122
valid_sources[0x14]	27551	1			T1	34		T2	2		T3	85
valid_sources[0x15]	27234	1			T1	43		T2	2		T3	63
valid_sources[0x16]	27617	1			T1	40		T2	1		T3	109
valid_sources[0x17]	27964	1			T1	44		T2	2		T3	165
valid_sources[0x18]	28433	1			T1	34		T2	3		T3	69
valid_sources[0x19]	28513	1			T1	36		T2	2		T3	65
valid_sources[0x1a]	28347	1			T1	39		T2	2		T3	81
valid_sources[0x1b]	27635	1			T1	31		T2	6		T3	80
valid_sources[0x1c]	28026	1			T1	49		T2	2		T3	96
valid_sources[0x1d]	27782	1			T1	45		T2	1		T3	97
valid_sources[0x1e]	27849	1			T1	41		T3	105		T7	26
valid_sources[0x1f]	28238	1			T1	52		T2	1		T3	112
valid_sources[0x20]	27296	1			T1	43		T2	3		T3	118

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26408

1

T1

40

T2

2

T3

106

values[0x0]

all_enables

biggest_size

198914

1

T1

286

T2

18

T3

634

values[0x1]

all_enables

biggest_size

26594

1

T1

31

T2

2

T3

89

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1542765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244853

1

T1

364

T2

10

T3

801

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	605994	1			T1	938		T2	46		T3	1836
values[0x0]	575471	1			T1	912		T2	32		T3	1826
values[0x1]	606153	1			T1	958		T2	34		T3	1902

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1192963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

594655

1

T1

945

T2

36

T3

1881

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27461	1			T1	44		T2	1		T3	84
valid_sources[0x01]	28198	1			T1	41		T2	3		T3	37
valid_sources[0x02]	27883	1			T1	42		T2	1		T3	63
valid_sources[0x03]	28002	1			T1	50		T3	151		T7	6
valid_sources[0x04]	28302	1			T1	37		T3	85		T9	249
valid_sources[0x05]	27330	1			T1	49		T2	2		T3	78
valid_sources[0x06]	29094	1			T1	53		T2	1		T3	89
valid_sources[0x07]	28879	1			T1	44		T2	4		T3	134
valid_sources[0x08]	28150	1			T1	42		T3	105		T8	2
valid_sources[0x09]	27699	1			T1	49		T2	1		T3	114
valid_sources[0x0a]	27946	1			T1	48		T2	2		T3	101
valid_sources[0x0b]	27568	1			T1	52		T2	1		T3	56
valid_sources[0x0c]	27955	1			T1	34		T2	6		T3	101
valid_sources[0x0d]	27445	1			T1	51		T2	1		T3	106
valid_sources[0x0e]	28824	1			T1	36		T2	1		T3	102
valid_sources[0x0f]	27576	1			T1	45		T2	3		T3	21
valid_sources[0x10]	27939	1			T1	36		T2	3		T3	32
valid_sources[0x11]	27425	1			T1	35		T3	53		T7	7
valid_sources[0x12]	28249	1			T1	50		T3	69		T7	19
valid_sources[0x13]	28067	1			T1	47		T2	4		T3	152
valid_sources[0x14]	28078	1			T1	40		T3	87		T9	121
valid_sources[0x15]	27544	1			T1	43		T3	41		T7	18
valid_sources[0x16]	27752	1			T1	38		T2	2		T3	31
valid_sources[0x17]	27751	1			T1	44		T2	1		T3	153
valid_sources[0x18]	27498	1			T1	41		T2	3		T3	98
valid_sources[0x19]	28071	1			T1	43		T2	1		T3	127
valid_sources[0x1a]	27383	1			T1	40		T2	3		T3	60
valid_sources[0x1b]	27629	1			T1	48		T2	2		T3	166
valid_sources[0x1c]	27946	1			T1	41		T2	2		T3	52
valid_sources[0x1d]	27892	1			T1	35		T2	2		T3	20
valid_sources[0x1e]	28080	1			T1	43		T2	2		T3	122
valid_sources[0x1f]	27664	1			T1	41		T2	1		T3	103
valid_sources[0x20]	27550	1			T1	40		T2	3		T3	124

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25609

1

T1

36

T2

1

T3

91

values[0x0]

all_enables

biggest_size

193209

1

T1

292

T2

8

T3

620

values[0x1]

all_enables

biggest_size

26035

1

T1

36

T2

1

T3

90