Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7576271	0	0
GntImpliesValid_A	2147483647	7576271	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7576271	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	439457417	0	0
ReadyAndValidImplyGrant_A	2147483647	7576271	0	0
ReqAndReadyImplyGrant_A	2147483647	7576271	0	0
ReqImpliesValid_A	2147483647	33766935	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44510	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7576271	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8794296	8794080	0	0
T2	7081224	7080216	0	0
T3	660384	646488	0	0
T7	1995384	1994448	0	0
T8	34560	33384	0	0
T9	1534464	1529928	0	0
T10	730488	729456	0	0
T11	270672	270000	0	0
T12	1259400	1257816	0	0
T13	172704	171624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8794296	8794080	0	0
T2	7081224	7080216	0	0
T3	660384	646488	0	0
T7	1995384	1994448	0	0
T8	34560	33384	0	0
T9	1534464	1529928	0	0
T10	730488	729456	0	0
T11	270672	270000	0	0
T12	1259400	1257816	0	0
T13	172704	171624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8794296	8794080	0	0
T2	7081224	7080216	0	0
T3	660384	646488	0	0
T7	1995384	1994448	0	0
T8	34560	33384	0	0
T9	1534464	1529928	0	0
T10	730488	729456	0	0
T11	270672	270000	0	0
T12	1259400	1257816	0	0
T13	172704	171624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	439457417	0	0
T1	8061438	340857	0	0
T2	7081224	247279	0	0
T3	660384	15559	0	0
T7	1995384	107763	0	0
T8	34560	622	0	0
T9	1534464	39868	0	0
T10	730488	48687	0	0
T11	270672	18267	0	0
T12	1259400	12707	0	0
T13	172704	3690	0	0
T14	250284	28237	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33766935	0	0
T1	3297861	22298	0	0
T2	7081224	677	0	0
T3	660384	17467	0	0
T7	1995384	7834	0	0
T8	34560	380	0	0
T9	1534464	36355	0	0
T10	730488	6968	0	0
T11	270672	3100	0	0
T12	1259400	49793	0	0
T13	172704	3117	0	0
T14	1877130	44900	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44510	0	21600
T1	366429	14	0	1
T2	295051	0	0	1
T3	55032	182	0	2
T7	166282	0	0	2
T8	2880	1	0	2
T9	127872	70	0	2
T10	60874	1	0	2
T11	22556	0	0	2
T12	104950	769	0	2
T13	14392	7	0	2
T14	125142	183	0	1
T15	0	20	0	0
T16	0	1	0	0
T17	0	2	0	0
T18	0	11	0	0
T19	0	4	0	0
T20	1894	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8794296	8794080	0	0
T2	7081224	7080216	0	0
T3	660384	646488	0	0
T7	1995384	1994448	0	0
T8	34560	33384	0	0
T9	1534464	1529928	0	0
T10	730488	729456	0	0
T11	270672	270000	0	0
T12	1259400	1257816	0	0
T13	172704	171624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7576271	0	0
T1	3297861	8073	0	0
T2	7081224	381	0	0
T3	660384	15068	0	0
T7	1995384	4353	0	0
T8	34560	250	0	0
T9	1534464	31021	0	0
T10	730488	2867	0	0
T11	270672	1359	0	0
T12	1259400	25144	0	0
T13	172704	2730	0	0
T14	1877130	19343	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	854677	0	0
GntImpliesValid_A	401514365	854677	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	854677	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	11729124	0	0
ReadyAndValidImplyGrant_A	401514365	854677	0	0
ReqAndReadyImplyGrant_A	401514365	854677	0	0
ReqImpliesValid_A	401514365	2455128	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	854677	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	11729124	0	0
T1	366429	2046	0	0
T2	295051	153	0	0
T3	27516	1361	0	0
T7	83141	3696	0	0
T8	1440	29	0	0
T9	63936	2591	0	0
T10	30437	2454	0	0
T11	11278	783	0	0
T12	52475	1501	0	0
T13	7196	244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2455128	0	0
T1	366429	738	0	0
T2	295051	68	0	0
T3	27516	3002	0	0
T7	83141	565	0	0
T8	1440	38	0	0
T9	63936	3810	0	0
T10	30437	528	0	0
T11	11278	235	0	0
T12	52475	5151	0	0
T13	7196	327	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854677	0	0
T1	366429	504	0	0
T2	295051	38	0	0
T3	27516	2179	0	0
T7	83141	502	0	0
T8	1440	33	0	0
T9	63936	3199	0	0
T10	30437	335	0	0
T11	11278	115	0	0
T12	52475	3325	0	0
T13	7196	285	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	839274	0	0
GntImpliesValid_A	401514365	839274	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	839274	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	11742714	0	0
ReadyAndValidImplyGrant_A	401514365	839274	0	0
ReqAndReadyImplyGrant_A	401514365	839274	0	0
ReqImpliesValid_A	401514365	2321086	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	839274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	11742714	0	0
T1	366429	4265	0	0
T2	295051	203	0	0
T3	27516	1207	0	0
T7	83141	3634	0	0
T8	1440	24	0	0
T9	63936	2657	0	0
T10	30437	2242	0	0
T11	11278	1007	0	0
T12	52475	1440	0	0
T13	7196	248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2321086	0	0
T1	366429	2612	0	0
T2	295051	71	0	0
T3	27516	1705	0	0
T7	83141	513	0	0
T8	1440	39	0	0
T9	63936	3936	0	0
T10	30437	564	0	0
T11	11278	254	0	0
T12	52475	2306	0	0
T13	7196	355	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	839274	0	0
T1	366429	1204	0	0
T2	295051	55	0	0
T3	27516	1453	0	0
T7	83141	482	0	0
T8	1440	31	0	0
T9	63936	3295	0	0
T10	30437	310	0	0
T11	11278	142	0	0
T12	52475	1872	0	0
T13	7196	301	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	213515	0	0
GntImpliesValid_A	401514365	213515	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	213515	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2870955	0	0
ReadyAndValidImplyGrant_A	401514365	213515	0	0
ReqAndReadyImplyGrant_A	401514365	213515	0	0
ReqImpliesValid_A	401514365	564808	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	213515	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2870955	0	0
T1	366429	1	0	0
T2	295051	50	0	0
T3	27516	286	0	0
T7	83141	813	0	0
T8	1440	8	0	0
T9	63936	1017	0	0
T10	30437	599	0	0
T11	11278	344	0	0
T12	52475	144	0	0
T13	7196	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	564808	0	0
T2	295051	10	0	0
T3	27516	1130	0	0
T7	83141	109	0	0
T8	1440	7	0	0
T9	63936	2128	0	0
T10	30437	135	0	0
T11	11278	75	0	0
T12	52475	142	0	0
T13	7196	63	0	0
T14	125142	722	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213515	0	0
T2	295051	9	0	0
T3	27516	705	0	0
T7	83141	99	0	0
T8	1440	7	0	0
T9	63936	1571	0	0
T10	30437	77	0	0
T11	11278	48	0	0
T12	52475	142	0	0
T13	7196	62	0	0
T14	125142	713	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	221632	0	0
GntImpliesValid_A	401514365	221632	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	221632	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2849707	0	0
ReadyAndValidImplyGrant_A	401514365	221632	0	0
ReqAndReadyImplyGrant_A	401514365	221632	0	0
ReqImpliesValid_A	401514365	632044	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	221632	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2849707	0	0
T1	366429	1	0	0
T2	295051	59	0	0
T3	27516	189	0	0
T7	83141	765	0	0
T8	1440	3	0	0
T9	63936	1049	0	0
T10	30437	566	0	0
T11	11278	249	0	0
T12	52475	348	0	0
T13	7196	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	632044	0	0
T2	295051	16	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1302	0	0
T10	30437	104	0	0
T11	11278	41	0	0
T12	52475	1864	0	0
T13	7196	62	0	0
T14	125142	2121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	221632	0	0
T2	295051	14	0	0
T3	27516	183	0	0
T7	83141	116	0	0
T8	1440	2	0	0
T9	63936	1174	0	0
T10	30437	75	0	0
T11	11278	36	0	0
T12	52475	1105	0	0
T13	7196	62	0	0
T14	125142	1792	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	213275	0	0
GntImpliesValid_A	401514365	213275	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	213275	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	5192875	0	0
ReadyAndValidImplyGrant_A	401514365	213275	0	0
ReqAndReadyImplyGrant_A	401514365	213275	0	0
ReqImpliesValid_A	401514365	1203527	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	213275	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	5192875	0	0
T2	295051	161	0	0
T3	27516	1391	0	0
T7	83141	1156	0	0
T8	1440	134	0	0
T9	63936	3698	0	0
T10	30437	4204	0	0
T11	11278	343	0	0
T12	52475	1504	0	0
T13	7196	499	0	0
T14	125142	8202	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	1203527	0	0
T2	295051	42	0	0
T3	27516	235	0	0
T7	83141	113	0	0
T8	1440	86	0	0
T9	63936	952	0	0
T10	30437	657	0	0
T11	11278	66	0	0
T12	52475	5288	0	0
T13	7196	194	0	0
T14	125142	11621	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	213275	0	0
T2	295051	12	0	0
T3	27516	201	0	0
T7	83141	110	0	0
T8	1440	8	0	0
T9	63936	653	0	0
T10	30437	92	0	0
T11	11278	44	0	0
T12	52475	1167	0	0
T13	7196	90	0	0
T14	125142	1532	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	206241	0	0
GntImpliesValid_A	401514365	206241	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	206241	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	4530743	0	0
ReadyAndValidImplyGrant_A	401514365	206241	0	0
ReqAndReadyImplyGrant_A	401514365	206241	0	0
ReqImpliesValid_A	401514365	1079656	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	206241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	4530743	0	0
T2	295051	76	0	0
T3	27516	1045	0	0
T7	83141	2789	0	0
T8	1440	30	0	0
T9	63936	6736	0	0
T10	30437	660	0	0
T11	11278	267	0	0
T12	52475	1819	0	0
T13	7196	466	0	0
T14	125142	20035	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	1079656	0	0
T2	295051	9	0	0
T3	27516	218	0	0
T7	83141	118	0	0
T8	1440	3	0	0
T9	63936	1327	0	0
T10	30437	104	0	0
T11	11278	54	0	0
T12	52475	9041	0	0
T13	7196	130	0	0
T14	125142	13787	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206241	0	0
T2	295051	9	0	0
T3	27516	208	0	0
T7	83141	111	0	0
T8	1440	3	0	0
T9	63936	644	0	0
T10	30437	75	0	0
T11	11278	41	0	0
T12	52475	1562	0	0
T13	7196	80	0	0
T14	125142	1411	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	201281	0	0
GntImpliesValid_A	401514365	201281	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	201281	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	5241875	0	0
ReadyAndValidImplyGrant_A	401514365	201281	0	0
ReqAndReadyImplyGrant_A	401514365	201281	0	0
ReqImpliesValid_A	401514365	1078265	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	201281	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	5241875	0	0
T1	366429	10202	0	0
T2	295051	63	0	0
T3	27516	2748	0	0
T7	83141	5731	0	0
T8	1440	29	0	0
T9	63936	6209	0	0
T10	30437	973	0	0
T11	11278	436	0	0
T12	52475	765	0	0
T13	7196	410	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	1078265	0	0
T1	366429	4835	0	0
T2	295051	8	0	0
T3	27516	299	0	0
T7	83141	219	0	0
T8	1440	3	0	0
T9	63936	1197	0	0
T10	30437	89	0	0
T11	11278	95	0	0
T12	52475	2902	0	0
T13	7196	109	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	201281	0	0
T1	366429	1021	0	0
T2	295051	8	0	0
T3	27516	208	0	0
T7	83141	134	0	0
T8	1440	3	0	0
T9	63936	638	0	0
T10	30437	64	0	0
T11	11278	40	0	0
T12	52475	647	0	0
T13	7196	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	206581	0	0
GntImpliesValid_A	401514365	206581	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	206581	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	5746144	0	0
ReadyAndValidImplyGrant_A	401514365	206581	0	0
ReqAndReadyImplyGrant_A	401514365	206581	0	0
ReqImpliesValid_A	401514365	1398665	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	206581	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	5746144	0	0
T1	366429	7258	0	0
T2	295051	82	0	0
T3	27516	1599	0	0
T7	83141	1121	0	0
T8	1440	255	0	0
T9	63936	4701	0	0
T10	30437	934	0	0
T11	11278	325	0	0
T12	52475	1578	0	0
T13	7196	657	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	1398665	0	0
T1	366429	3680	0	0
T2	295051	13	0	0
T3	27516	281	0	0
T7	83141	143	0	0
T8	1440	44	0	0
T9	63936	934	0	0
T10	30437	155	0	0
T11	11278	52	0	0
T12	52475	4466	0	0
T13	7196	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	206581	0	0
T1	366429	1006	0	0
T2	295051	13	0	0
T3	27516	196	0	0
T7	83141	127	0	0
T8	1440	10	0	0
T9	63936	636	0	0
T10	30437	85	0	0
T11	11278	37	0	0
T12	52475	1113	0	0
T13	7196	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	205947	0	0
GntImpliesValid_A	401514365	205947	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	205947	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2822150	0	0
ReadyAndValidImplyGrant_A	401514365	205947	0	0
ReqAndReadyImplyGrant_A	401514365	205947	0	0
ReqImpliesValid_A	401514365	581846	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	205947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2822150	0	0
T1	366429	1608	0	0
T2	295051	43	0	0
T3	27516	572	0	0
T7	83141	1049	0	0
T8	1440	5	0	0
T9	63936	1084	0	0
T10	30437	626	0	0
T11	11278	261	0	0
T12	52475	154	0	0
T13	7196	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	581846	0	0
T1	366429	1129	0	0
T2	295051	10	0	0
T3	27516	664	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1283	0	0
T10	30437	117	0	0
T11	11278	52	0	0
T12	52475	152	0	0
T13	7196	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205947	0	0
T1	366429	507	0	0
T2	295051	10	0	0
T3	27516	615	0	0
T7	83141	140	0	0
T8	1440	4	0	0
T9	63936	1182	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	152	0	0
T13	7196	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	218150	0	0
GntImpliesValid_A	401514365	218150	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	218150	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2851351	0	0
ReadyAndValidImplyGrant_A	401514365	218150	0	0
ReqAndReadyImplyGrant_A	401514365	218150	0	0
ReqImpliesValid_A	401514365	579904	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	218150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2851351	0	0
T1	366429	1	0	0
T2	295051	22	0	0
T3	27516	211	0	0
T7	83141	686	0	0
T8	1440	8	0	0
T9	63936	1257	0	0
T10	30437	561	0	0
T11	11278	273	0	0
T12	52475	128	0	0
T13	7196	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	579904	0	0
T2	295051	21	0	0
T3	27516	211	0	0
T7	83141	103	0	0
T8	1440	11	0	0
T9	63936	2040	0	0
T10	30437	121	0	0
T11	11278	40	0	0
T12	52475	1200	0	0
T13	7196	70	0	0
T14	125142	731	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	218150	0	0
T2	295051	11	0	0
T3	27516	208	0	0
T7	83141	98	0	0
T8	1440	9	0	0
T9	63936	1647	0	0
T10	30437	83	0	0
T11	11278	38	0	0
T12	52475	663	0	0
T13	7196	66	0	0
T14	125142	717	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	207377	0	0
GntImpliesValid_A	401514365	207377	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	207377	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2872748	0	0
ReadyAndValidImplyGrant_A	401514365	207377	0	0
ReqAndReadyImplyGrant_A	401514365	207377	0	0
ReqImpliesValid_A	401514365	577010	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	207377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2872748	0	0
T1	366429	1	0	0
T2	295051	22	0	0
T3	27516	216	0	0
T7	83141	912	0	0
T8	1440	8	0	0
T9	63936	634	0	0
T10	30437	674	0	0
T11	11278	321	0	0
T12	52475	148	0	0
T13	7196	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	577010	0	0
T2	295051	14	0	0
T3	27516	218	0	0
T7	83141	126	0	0
T8	1440	9	0	0
T9	63936	677	0	0
T10	30437	99	0	0
T11	11278	71	0	0
T12	52475	982	0	0
T13	7196	84	0	0
T14	125142	1491	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207377	0	0
T2	295051	9	0	0
T3	27516	214	0	0
T7	83141	126	0	0
T8	1440	8	0	0
T9	63936	654	0	0
T10	30437	80	0	0
T11	11278	48	0	0
T12	52475	564	0	0
T13	7196	80	0	0
T14	125142	1236	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	209963	0	0
GntImpliesValid_A	401514365	209963	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	209963	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2930513	0	0
ReadyAndValidImplyGrant_A	401514365	209963	0	0
ReqAndReadyImplyGrant_A	401514365	209963	0	0
ReqImpliesValid_A	401514365	590779	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	209963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2930513	0	0
T1	366429	1	0	0
T2	295051	42	0	0
T3	27516	203	0	0
T7	83141	898	0	0
T8	1440	7	0	0
T9	63936	910	0	0
T10	30437	672	0	0
T11	11278	312	0	0
T12	52475	218	0	0
T13	7196	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	590779	0	0
T2	295051	8	0	0
T3	27516	199	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1483	0	0
T10	30437	121	0	0
T11	11278	65	0	0
T12	52475	1052	0	0
T13	7196	72	0	0
T14	125142	719	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	209963	0	0
T2	295051	8	0	0
T3	27516	198	0	0
T7	83141	131	0	0
T8	1440	6	0	0
T9	63936	1195	0	0
T10	30437	85	0	0
T11	11278	41	0	0
T12	52475	634	0	0
T13	7196	69	0	0
T14	125142	711	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	207390	0	0
GntImpliesValid_A	401514365	207390	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	207390	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2836540	0	0
ReadyAndValidImplyGrant_A	401514365	207390	0	0
ReqAndReadyImplyGrant_A	401514365	207390	0	0
ReqImpliesValid_A	401514365	587075	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	207390	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2836540	0	0
T1	366429	1	0	0
T2	295051	41	0	0
T3	27516	187	0	0
T7	83141	775	0	0
T8	1440	5	0	0
T9	63936	619	0	0
T10	30437	636	0	0
T11	11278	308	0	0
T12	52475	139	0	0
T13	7196	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	587075	0	0
T2	295051	13	0	0
T3	27516	191	0	0
T7	83141	114	0	0
T8	1440	4	0	0
T9	63936	668	0	0
T10	30437	123	0	0
T11	11278	77	0	0
T12	52475	137	0	0
T13	7196	76	0	0
T14	125142	745	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207390	0	0
T2	295051	8	0	0
T3	27516	186	0	0
T7	83141	111	0	0
T8	1440	4	0	0
T9	63936	642	0	0
T10	30437	90	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	71	0	0
T14	125142	733	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	207516	0	0
GntImpliesValid_A	401514365	207516	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	207516	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2820459	0	0
ReadyAndValidImplyGrant_A	401514365	207516	0	0
ReqAndReadyImplyGrant_A	401514365	207516	0	0
ReqImpliesValid_A	401514365	547659	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	207516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2820459	0	0
T1	366429	1	0	0
T2	295051	67	0	0
T3	27516	223	0	0
T7	83141	910	0	0
T8	1440	7	0	0
T9	63936	589	0	0
T10	30437	594	0	0
T11	11278	291	0	0
T12	52475	183	0	0
T13	7196	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	547659	0	0
T2	295051	14	0	0
T3	27516	221	0	0
T7	83141	132	0	0
T8	1440	6	0	0
T9	63936	634	0	0
T10	30437	101	0	0
T11	11278	74	0	0
T12	52475	2115	0	0
T13	7196	64	0	0
T14	125142	3440	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	207516	0	0
T2	295051	12	0	0
T3	27516	219	0	0
T7	83141	129	0	0
T8	1440	6	0	0
T9	63936	610	0	0
T10	30437	80	0	0
T11	11278	36	0	0
T12	52475	1148	0	0
T13	7196	62	0	0
T14	125142	2683	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	211186	0	0
GntImpliesValid_A	401514365	211186	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	211186	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2885832	0	0
ReadyAndValidImplyGrant_A	401514365	211186	0	0
ReqAndReadyImplyGrant_A	401514365	211186	0	0
ReqImpliesValid_A	401514365	568944	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	211186	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2885832	0	0
T1	366429	1	0	0
T2	295051	41	0	0
T3	27516	221	0	0
T7	83141	1138	0	0
T8	1440	12	0	0
T9	63936	1105	0	0
T10	30437	617	0	0
T11	11278	266	0	0
T12	52475	321	0	0
T13	7196	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	568944	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	139	0	0
T8	1440	11	0	0
T9	63936	1364	0	0
T10	30437	101	0	0
T11	11278	53	0	0
T12	52475	1019	0	0
T13	7196	74	0	0
T14	125142	1441	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	211186	0	0
T2	295051	8	0	0
T3	27516	215	0	0
T7	83141	135	0	0
T8	1440	11	0	0
T9	63936	1233	0	0
T10	30437	82	0	0
T11	11278	38	0	0
T12	52475	669	0	0
T13	7196	74	0	0
T14	125142	1302	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	205990	0	0
GntImpliesValid_A	401514365	205990	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	205990	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2851051	0	0
ReadyAndValidImplyGrant_A	401514365	205990	0	0
ReqAndReadyImplyGrant_A	401514365	205990	0	0
ReqImpliesValid_A	401514365	540673	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	205990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2851051	0	0
T1	366429	1	0	0
T2	295051	24	0	0
T3	27516	632	0	0
T7	83141	918	0	0
T8	1440	10	0	0
T9	63936	954	0	0
T10	30437	749	0	0
T11	11278	314	0	0
T12	52475	134	0	0
T13	7196	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	540673	0	0
T2	295051	13	0	0
T3	27516	849	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1457	0	0
T10	30437	178	0	0
T11	11278	45	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	788	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205990	0	0
T2	295051	10	0	0
T3	27516	738	0	0
T7	83141	120	0	0
T8	1440	9	0	0
T9	63936	1204	0	0
T10	30437	96	0	0
T11	11278	44	0	0
T12	52475	132	0	0
T13	7196	65	0	0
T14	125142	772	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	226292	0	0
GntImpliesValid_A	401514365	226292	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	226292	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2938121	0	0
ReadyAndValidImplyGrant_A	401514365	226292	0	0
ReqAndReadyImplyGrant_A	401514365	226292	0	0
ReqImpliesValid_A	401514365	585102	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	226292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2938121	0	0
T1	366429	4816	0	0
T2	295051	36	0	0
T3	27516	642	0	0
T7	83141	1119	0	0
T8	1440	16	0	0
T9	63936	727	0	0
T10	30437	584	0	0
T11	11278	326	0	0
T12	52475	574	0	0
T13	7196	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	585102	0	0
T1	366429	3362	0	0
T2	295051	7	0	0
T3	27516	825	0	0
T7	83141	148	0	0
T8	1440	15	0	0
T9	63936	772	0	0
T10	30437	99	0	0
T11	11278	50	0	0
T12	52475	784	0	0
T13	7196	138	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	226292	0	0
T1	366429	1454	0	0
T2	295051	6	0	0
T3	27516	731	0	0
T7	83141	147	0	0
T8	1440	15	0	0
T9	63936	748	0	0
T10	30437	75	0	0
T11	11278	42	0	0
T12	52475	678	0	0
T13	7196	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T3,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	202299	0	0
GntImpliesValid_A	401514365	202299	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	202299	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2843126	0	0
ReadyAndValidImplyGrant_A	401514365	202299	0	0
ReqAndReadyImplyGrant_A	401514365	202299	0	0
ReqImpliesValid_A	401514365	537626	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	202299	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2843126	0	0
T1	366429	1	0	0
T2	295051	23	0	0
T3	27516	243	0	0
T7	83141	1027	0	0
T8	1440	8	0	0
T9	63936	566	0	0
T10	30437	673	0	0
T11	11278	394	0	0
T12	52475	1055	0	0
T13	7196	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	537626	0	0
T2	295051	8	0	0
T3	27516	245	0	0
T7	83141	137	0	0
T8	1440	7	0	0
T9	63936	595	0	0
T10	30437	123	0	0
T11	11278	87	0	0
T12	52475	2203	0	0
T13	7196	76	0	0
T14	125142	2005	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	202299	0	0
T2	295051	8	0	0
T3	27516	241	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	579	0	0
T10	30437	90	0	0
T11	11278	52	0	0
T12	52475	1628	0	0
T13	7196	71	0	0
T14	125142	1611	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	203543	0	0
GntImpliesValid_A	401514365	203543	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	203543	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2916354	0	0
ReadyAndValidImplyGrant_A	401514365	203543	0	0
ReqAndReadyImplyGrant_A	401514365	203543	0	0
ReqImpliesValid_A	401514365	543806	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	203543	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2916354	0	0
T1	366429	1962	0	0
T2	295051	64	0	0
T3	27516	219	0	0
T7	83141	878	0	0
T8	1440	6	0	0
T9	63936	618	0	0
T10	30437	477	0	0
T11	11278	286	0	0
T12	52475	138	0	0
T13	7196	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	543806	0	0
T1	366429	1174	0	0
T2	295051	22	0	0
T3	27516	213	0	0
T7	83141	126	0	0
T8	1440	7	0	0
T9	63936	663	0	0
T10	30437	73	0	0
T11	11278	54	0	0
T12	52475	138	0	0
T13	7196	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	203543	0	0
T1	366429	556	0	0
T2	295051	12	0	0
T3	27516	213	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	639	0	0
T10	30437	65	0	0
T11	11278	42	0	0
T12	52475	137	0	0
T13	7196	81	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	217257	0	0
GntImpliesValid_A	401514365	217257	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	217257	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2955446	0	0
ReadyAndValidImplyGrant_A	401514365	217257	0	0
ReqAndReadyImplyGrant_A	401514365	217257	0	0
ReqImpliesValid_A	401514365	602918	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	217257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2955446	0	0
T1	366429	1	0	0
T2	295051	60	0	0
T3	27516	416	0	0
T7	83141	875	0	0
T8	1440	3	0	0
T9	63936	617	0	0
T10	30437	682	0	0
T11	11278	292	0	0
T12	52475	153	0	0
T13	7196	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	602918	0	0
T2	295051	16	0	0
T3	27516	716	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	656	0	0
T10	30437	142	0	0
T11	11278	57	0	0
T12	52475	1243	0	0
T13	7196	81	0	0
T14	125142	1684	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	217257	0	0
T2	295051	11	0	0
T3	27516	563	0	0
T7	83141	120	0	0
T8	1440	2	0	0
T9	63936	635	0	0
T10	30437	95	0	0
T11	11278	36	0	0
T12	52475	697	0	0
T13	7196	77	0	0
T14	125142	1208	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T7
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T3,T8,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	219626	0	0
GntImpliesValid_A	401514365	219626	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	219626	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2914485	0	0
ReadyAndValidImplyGrant_A	401514365	219626	0	0
ReqAndReadyImplyGrant_A	401514365	219626	0	0
ReqImpliesValid_A	401514365	603031	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	219626	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2914485	0	0
T1	366429	1	0	0
T2	295051	37	0	0
T3	27516	1531	0	0
T7	83141	819	0	0
T8	1440	6	0	0
T9	63936	589	0	0
T10	30437	549	0	0
T11	11278	311	0	0
T12	52475	134	0	0
T13	7196	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	603031	0	0
T2	295051	7	0	0
T3	27516	2028	0	0
T7	83141	160	0	0
T8	1440	7	0	0
T9	63936	630	0	0
T10	30437	93	0	0
T11	11278	43	0	0
T12	52475	1140	0	0
T13	7196	62	0	0
T14	125142	1552	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	219626	0	0
T2	295051	7	0	0
T3	27516	1777	0	0
T7	83141	125	0	0
T8	1440	6	0	0
T9	63936	608	0	0
T10	30437	67	0	0
T11	11278	40	0	0
T12	52475	636	0	0
T13	7196	62	0	0
T14	125142	1252	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T2,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T8
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	205137	0	0
GntImpliesValid_A	401514365	205137	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	205137	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	2907871	0	0
ReadyAndValidImplyGrant_A	401514365	205137	0	0
ReqAndReadyImplyGrant_A	401514365	205137	0	0
ReqImpliesValid_A	401514365	542959	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	0	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	205137	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2907871	0	0
T1	366429	1	0	0
T2	295051	84	0	0
T3	27516	210	0	0
T7	83141	887	0	0
T8	1440	7	0	0
T9	63936	937	0	0
T10	30437	614	0	0
T11	11278	164	0	0
T12	52475	126	0	0
T13	7196	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	542959	0	0
T2	295051	23	0	0
T3	27516	208	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1358	0	0
T10	30437	125	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	85	0	0
T14	125142	2053	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	205137	0	0
T2	295051	19	0	0
T3	27516	206	0	0
T7	83141	116	0	0
T8	1440	6	0	0
T9	63936	1146	0	0
T10	30437	89	0	0
T11	11278	25	0	0
T12	52475	124	0	0
T13	7196	82	0	0
T14	125142	1670	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	854337	0	0
GntImpliesValid_A	401514365	854337	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	854337	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	11046170	0	0
ReadyAndValidImplyGrant_A	401514365	854337	0	0
ReqAndReadyImplyGrant_A	401514365	854337	0	0
ReqImpliesValid_A	401514365	2250052	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	19627	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	854337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	11046170	0	0
T1	366429	3516	0	0
T2	295051	182	0	0
T3	27516	6	0	0
T7	83141	2851	0	0
T8	1440	1	0	0
T9	63936	3	0	0
T10	30437	1925	0	0
T11	11278	1162	0	0
T12	52475	2	0	0
T13	7196	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	2250052	0	0
T1	366429	2352	0	0
T2	295051	40	0	0
T3	27516	2003	0	0
T7	83141	486	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	520	0	0
T11	11278	310	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	19627	0	900
T1	366429	14	0	1
T2	295051	0	0	1
T3	27516	171	0	1
T7	83141	0	0	1
T8	1440	0	0	1
T9	63936	35	0	1
T10	30437	0	0	1
T11	11278	0	0	1
T12	52475	758	0	1
T13	7196	2	0	1
T14	0	37	0	0
T15	0	8	0	0
T17	0	1	0	0
T18	0	11	0	0
T19	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	854337	0	0
T1	366429	1270	0	0
T2	295051	39	0	0
T3	27516	2003	0	0
T7	83141	453	0	0
T8	1440	26	0	0
T9	63936	3240	0	0
T10	30437	298	0	0
T11	11278	160	0	0
T12	52475	4219	0	0
T13	7196	324	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401514365	401390930	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	401514365	817785	0	0
GntImpliesValid_A	401514365	817785	0	0
GrantKnown_A	401514365	401390930	0	0
IdxKnown_A	401514365	401390930	0	0
IndexIsCorrect_A	401514365	817785	0	0
LockArbDecision_A	401514365	0	0	0
NoReadyValidNoGrant_A	401514365	338161063	0	0
ReadyAndValidImplyGrant_A	401514365	817785	0	0
ReqAndReadyImplyGrant_A	401514365	817785	0	0
ReqImpliesValid_A	401514365	12794372	0	0
ReqStaysHighUntilGranted0_M	401514365	0	0	0
RoundRobin_A	401514365	24883	0	900
ValidKnown_A	401514365	401390930	0	0
gen_data_port_assertion.DataFlow_A	401514365	817785	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	338161063	0	0
T1	366429	305171	0	0
T2	295051	245644	0	0
T3	27516	1	0	0
T7	83141	72316	0	0
T8	1440	1	0	0
T9	63936	1	0	0
T10	30437	25422	0	0
T11	11278	9232	0	0
T12	52475	1	0	0
T13	7196	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	12794372	0	0
T1	366429	2416	0	0
T2	295051	216	0	0
T3	27516	1408	0	0
T7	83141	3640	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	2496	0	0
T11	11278	1125	0	0
T12	52475	1993	0	0
T13	7196	283	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	24883	0	900
T3	27516	11	0	1
T7	83141	0	0	1
T8	1440	1	0	1
T9	63936	35	0	1
T10	30437	1	0	1
T11	11278	0	0	1
T12	52475	11	0	1
T13	7196	5	0	1
T14	125142	146	0	1
T15	0	12	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	1894	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	401390930	0	0
T1	366429	366420	0	0
T2	295051	295009	0	0
T3	27516	26937	0	0
T7	83141	83102	0	0
T8	1440	1391	0	0
T9	63936	63747	0	0
T10	30437	30394	0	0
T11	11278	11250	0	0
T12	52475	52409	0	0
T13	7196	7151	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401514365	817785	0	0
T1	366429	551	0	0
T2	295051	45	0	0
T3	27516	1408	0	0
T7	83141	470	0	0
T8	1440	28	0	0
T9	63936	3249	0	0
T10	30437	297	0	0
T11	11278	134	0	0
T12	52475	1993	0	0
T13	7196	283	0	0