Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1541922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245228

1

T1

160

T2

4

T3

1568

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	606750	1			T1	419		T2	24		T3	3827
values[0x0]	574197	1			T1	420		T2	3		T3	3799
values[0x1]	606203	1			T1	414		T2	14		T3	3862

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1192604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

594546

1

T1

420

T2

16

T3

3811

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28299	1			T1	7		T2	3		T3	321
valid_sources[0x01]	28484	1			T1	19		T2	2		T3	249
valid_sources[0x02]	28276	1			T1	23		T2	1		T3	162
valid_sources[0x03]	27300	1			T1	15		T2	1		T3	123
valid_sources[0x04]	27642	1			T1	19		T3	271		T7	40
valid_sources[0x05]	28534	1			T1	16		T3	181		T7	27
valid_sources[0x06]	28304	1			T1	26		T2	1		T3	112
valid_sources[0x07]	28421	1			T1	25		T3	195		T7	39
valid_sources[0x08]	29481	1			T1	20		T3	204		T7	29
valid_sources[0x09]	28190	1			T1	27		T2	1		T3	191
valid_sources[0x0a]	27762	1			T1	25		T3	99		T7	39
valid_sources[0x0b]	27288	1			T1	25		T3	198		T7	35
valid_sources[0x0c]	27099	1			T1	18		T2	1		T3	147
valid_sources[0x0d]	28728	1			T1	15		T3	122		T7	41
valid_sources[0x0e]	27895	1			T1	14		T3	309		T7	41
valid_sources[0x0f]	27788	1			T1	19		T3	132		T7	28
valid_sources[0x10]	28022	1			T1	28		T3	163		T7	24
valid_sources[0x11]	27852	1			T1	15		T2	1		T3	229
valid_sources[0x12]	27581	1			T1	20		T3	108		T7	34
valid_sources[0x13]	28610	1			T1	9		T3	176		T7	30
valid_sources[0x14]	27797	1			T1	17		T2	1		T3	262
valid_sources[0x15]	27457	1			T1	28		T2	2		T3	137
valid_sources[0x16]	27673	1			T1	12		T3	163		T7	30
valid_sources[0x17]	28369	1			T1	16		T2	1		T3	146
valid_sources[0x18]	27575	1			T1	20		T3	140		T7	33
valid_sources[0x19]	27212	1			T1	23		T3	103		T7	36
valid_sources[0x1a]	28123	1			T1	10		T3	110		T7	29
valid_sources[0x1b]	28685	1			T1	24		T2	1		T3	173
valid_sources[0x1c]	29374	1			T1	23		T2	2		T3	150
valid_sources[0x1d]	27439	1			T1	25		T2	2		T3	182
valid_sources[0x1e]	28120	1			T1	25		T3	203		T7	30
valid_sources[0x1f]	27189	1			T1	17		T2	2		T3	240
valid_sources[0x20]	28603	1			T1	19		T2	1		T3	129

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25920

1

T1

9

T2

3

T3

163

values[0x0]

all_enables

biggest_size

193642

1

T1

133

T3

1256

T7

213

values[0x1]

all_enables

biggest_size

25666

1

T1

18

T2

1

T3

149

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1554296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253814

1

T1

175

T2

3

T3

1626

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619395	1			T1	429		T2	12		T3	3770
values[0x0]	570426	1			T1	417		T2	3		T3	3601
values[0x1]	618289	1			T1	448		T2	15		T3	3857

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1192618	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615492

1

T1

429

T2

11

T3

3861

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27925	1			T1	4		T3	245		T7	34
valid_sources[0x01]	28501	1			T1	14		T2	1		T3	158
valid_sources[0x02]	28478	1			T1	10		T2	1		T3	189
valid_sources[0x03]	27314	1			T1	163		T3	122		T7	15
valid_sources[0x04]	28342	1			T1	2		T3	205		T7	25
valid_sources[0x05]	28417	1			T1	8		T3	145		T7	31
valid_sources[0x06]	28664	1			T1	17		T3	186		T7	21
valid_sources[0x07]	28125	1			T1	3		T3	167		T7	22
valid_sources[0x08]	29112	1			T1	5		T2	1		T3	207
valid_sources[0x09]	28552	1			T1	4		T3	167		T7	32
valid_sources[0x0a]	28397	1			T1	2		T3	162		T7	27
valid_sources[0x0b]	28086	1			T1	7		T2	1		T3	154
valid_sources[0x0c]	27704	1			T1	10		T3	192		T7	40
valid_sources[0x0d]	29099	1			T1	28		T3	166		T7	17
valid_sources[0x0e]	28322	1			T1	17		T3	224		T7	41
valid_sources[0x0f]	27944	1			T1	8		T3	225		T7	21
valid_sources[0x10]	28203	1			T1	8		T3	230		T7	28
valid_sources[0x11]	28601	1			T1	7		T2	1		T3	177
valid_sources[0x12]	28112	1			T1	5		T3	133		T7	54
valid_sources[0x13]	27993	1			T1	16		T3	173		T7	20
valid_sources[0x14]	27968	1			T1	2		T3	185		T7	34
valid_sources[0x15]	28936	1			T1	4		T3	178		T7	23
valid_sources[0x16]	27699	1			T1	27		T3	194		T7	45
valid_sources[0x17]	28173	1			T1	3		T3	167		T7	66
valid_sources[0x18]	28265	1			T1	3		T2	1		T3	122
valid_sources[0x19]	28036	1			T1	3		T3	182		T7	41
valid_sources[0x1a]	28161	1			T1	5		T2	1		T3	175
valid_sources[0x1b]	28749	1			T1	8		T3	170		T7	28
valid_sources[0x1c]	27922	1			T1	19		T2	1		T3	219
valid_sources[0x1d]	28965	1			T1	6		T2	1		T3	123
valid_sources[0x1e]	28596	1			T1	11		T3	167		T7	27
valid_sources[0x1f]	28788	1			T1	7		T2	2		T3	234
valid_sources[0x20]	28455	1			T1	10		T3	140		T7	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26710

1

T1

9

T2

2

T3

155

values[0x0]

all_enables

biggest_size

200624

1

T1

146

T3

1303

T7

237

values[0x1]

all_enables

biggest_size

26480

1

T1

20

T2

1

T3

168

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1552160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246396

1

T1

140

T2

8

T3

1598

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609937	1			T1	350		T2	6		T3	3853
values[0x0]	579150	1			T1	352		T2	8		T3	3791
values[0x1]	609469	1			T1	401		T2	18		T3	3823

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1200475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

598081

1

T1

362

T2

19

T3

3781

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28300	1			T1	23		T3	180		T7	28
valid_sources[0x01]	28135	1			T1	14		T3	153		T7	33
valid_sources[0x02]	27953	1			T1	19		T2	1		T3	177
valid_sources[0x03]	27301	1			T1	12		T3	179		T7	37
valid_sources[0x04]	28599	1			T1	26		T3	216		T7	13
valid_sources[0x05]	28356	1			T1	12		T2	1		T3	166
valid_sources[0x06]	28447	1			T1	14		T2	1		T3	174
valid_sources[0x07]	28260	1			T1	20		T2	1		T3	185
valid_sources[0x08]	27955	1			T1	21		T3	194		T7	19
valid_sources[0x09]	28032	1			T1	12		T3	153		T7	51
valid_sources[0x0a]	27802	1			T1	13		T3	139		T7	41
valid_sources[0x0b]	28168	1			T1	15		T3	177		T7	28
valid_sources[0x0c]	27178	1			T1	12		T3	170		T7	49
valid_sources[0x0d]	28647	1			T1	16		T3	185		T7	33
valid_sources[0x0e]	28964	1			T1	14		T2	2		T3	208
valid_sources[0x0f]	28494	1			T1	16		T3	235		T7	19
valid_sources[0x10]	28257	1			T1	15		T3	142		T7	51
valid_sources[0x11]	28260	1			T1	15		T3	221		T7	26
valid_sources[0x12]	28298	1			T1	16		T3	159		T7	38
valid_sources[0x13]	28110	1			T1	17		T3	134		T7	14
valid_sources[0x14]	27933	1			T1	21		T2	1		T3	212
valid_sources[0x15]	27963	1			T1	17		T3	188		T7	67
valid_sources[0x16]	26926	1			T1	17		T3	177		T7	10
valid_sources[0x17]	28328	1			T1	15		T3	195		T7	35
valid_sources[0x18]	28414	1			T1	20		T2	1		T3	115
valid_sources[0x19]	27662	1			T1	14		T3	163		T7	35
valid_sources[0x1a]	27501	1			T1	20		T3	202		T7	28
valid_sources[0x1b]	27881	1			T1	14		T2	4		T3	159
valid_sources[0x1c]	27649	1			T1	22		T3	153		T7	27
valid_sources[0x1d]	28232	1			T1	16		T2	3		T3	165
valid_sources[0x1e]	28535	1			T1	14		T3	163		T7	30
valid_sources[0x1f]	28003	1			T1	13		T2	2		T3	225
valid_sources[0x20]	28539	1			T1	13		T3	165		T7	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25951

1

T1

16

T3

164

T7

28

values[0x0]

all_enables

biggest_size

194836

1

T1

110

T2

5

T3

1296

values[0x1]

all_enables

biggest_size

25609

1

T1

14

T2

3

T3

138