Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7722818	0	0
GntImpliesValid_A	2147483647	7722818	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7722818	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453217169	0	0
ReadyAndValidImplyGrant_A	2147483647	7722818	0	0
ReqAndReadyImplyGrant_A	2147483647	7722818	0	0
ReqImpliesValid_A	2147483647	34061059	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	47239	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7722818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	123336	122160	0	0
T2	590832	590184	0	0
T3	6962760	6961680	0	0
T7	4853664	4853616	0	0
T8	590808	590568	0	0
T9	13145376	13143936	0	0
T10	41904	40848	0	0
T11	98976	95616	0	0
T12	4365336	4365264	0	0
T13	411792	410088	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	123336	122160	0	0
T2	590832	590184	0	0
T3	6962760	6961680	0	0
T7	4853664	4853616	0	0
T8	590808	590568	0	0
T9	13145376	13143936	0	0
T10	41904	40848	0	0
T11	98976	95616	0	0
T12	4365336	4365264	0	0
T13	411792	410088	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	123336	122160	0	0
T2	590832	590184	0	0
T3	6962760	6961680	0	0
T7	4853664	4853616	0	0
T8	590808	590568	0	0
T9	13145376	13143936	0	0
T10	41904	40848	0	0
T11	98976	95616	0	0
T12	4365336	4365264	0	0
T13	411792	410088	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453217169	0	0
T1	102780	209	0	0
T2	590832	36153	0	0
T3	6962760	438324	0	0
T7	4853664	192826	0	0
T8	590808	2008	0	0
T9	13145376	869050	0	0
T10	41904	669	0	0
T11	98976	6633	0	0
T12	4365336	176693	0	0
T13	411792	13733	0	0
T14	10440	441	0	0
T15	0	193	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34061059	0	0
T1	30834	4698	0	0
T2	590832	5494	0	0
T3	6962760	82146	0	0
T7	4853664	10282	0	0
T8	590808	28325	0	0
T9	13145376	95149	0	0
T10	41904	639	0	0
T11	98976	1005	0	0
T12	4365336	10069	0	0
T13	411792	8575	0	0
T14	46980	302	0	0
T15	0	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47239	0	21600
T1	10278	1169	0	2
T2	49236	0	0	2
T3	580230	14	0	2
T7	404472	0	0	2
T8	49234	786	0	2
T9	1095448	0	0	2
T10	3492	1	0	2
T11	8248	0	0	2
T12	363778	0	0	2
T13	34316	15	0	2
T16	0	1	0	0
T17	0	55	0	0
T18	0	1	0	0
T19	0	11	0	0
T20	0	35	0	0
T21	0	24	0	0
T22	0	655	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	123336	122160	0	0
T2	590832	590184	0	0
T3	6962760	6961680	0	0
T7	4853664	4853616	0	0
T8	590808	590568	0	0
T9	13145376	13143936	0	0
T10	41904	40848	0	0
T11	98976	95616	0	0
T12	4365336	4365264	0	0
T13	411792	410088	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7722818	0	0
T1	30834	3650	0	0
T2	590832	2362	0	0
T3	6962760	30863	0	0
T7	4853664	6091	0	0
T8	590808	14793	0	0
T9	13145376	1211	0	0
T10	41904	574	0	0
T11	98976	388	0	0
T12	4365336	6000	0	0
T13	411792	6428	0	0
T14	46980	256	0	0
T15	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	851204	0	0
GntImpliesValid_A	415148816	851204	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	851204	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	12275008	0	0
ReadyAndValidImplyGrant_A	415148816	851204	0	0
ReqAndReadyImplyGrant_A	415148816	851204	0	0
ReqImpliesValid_A	415148816	2434927	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	851204	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	12275008	0	0
T1	5139	87	0	0
T2	24618	1757	0	0
T3	290115	20644	0	0
T7	202236	2951	0	0
T8	24617	790	0	0
T9	547724	51332	0	0
T10	1746	55	0	0
T11	4124	274	0	0
T12	181889	2758	0	0
T13	17158	496	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2434927	0	0
T1	5139	166	0	0
T2	24618	462	0	0
T3	290115	4328	0	0
T7	202236	915	0	0
T8	24617	1353	0	0
T9	547724	10090	0	0
T10	1746	76	0	0
T11	4124	53	0	0
T12	181889	889	0	0
T13	17158	835	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	851204	0	0
T1	5139	126	0	0
T2	24618	240	0	0
T3	290115	2929	0	0
T7	202236	690	0	0
T8	24617	1071	0	0
T9	547724	159	0	0
T10	1746	65	0	0
T11	4124	34	0	0
T12	181889	664	0	0
T13	17158	665	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	871508	0	0
GntImpliesValid_A	415148816	871508	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	871508	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	12132479	0	0
ReadyAndValidImplyGrant_A	415148816	871508	0	0
ReqAndReadyImplyGrant_A	415148816	871508	0	0
ReqImpliesValid_A	415148816	2458078	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	871508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	12132479	0	0
T1	5139	90	0	0
T2	24618	1783	0	0
T3	290115	21323	0	0
T7	202236	2779	0	0
T8	24617	787	0	0
T9	547724	41333	0	0
T10	1746	52	0	0
T11	4124	270	0	0
T12	181889	2771	0	0
T13	17158	497	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2458078	0	0
T1	5139	165	0	0
T2	24618	489	0	0
T3	290115	4571	0	0
T7	202236	945	0	0
T8	24617	1426	0	0
T9	547724	3827	0	0
T10	1746	65	0	0
T11	4124	54	0	0
T12	181889	898	0	0
T13	17158	792	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	871508	0	0
T1	5139	127	0	0
T2	24618	256	0	0
T3	290115	3046	0	0
T7	202236	680	0	0
T8	24617	1106	0	0
T9	547724	122	0	0
T10	1746	58	0	0
T11	4124	36	0	0
T12	181889	651	0	0
T13	17158	644	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	220713	0	0
GntImpliesValid_A	415148816	220713	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	220713	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	2985576	0	0
ReadyAndValidImplyGrant_A	415148816	220713	0	0
ReqAndReadyImplyGrant_A	415148816	220713	0	0
ReqImpliesValid_A	415148816	580533	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	220713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2985576	0	0
T1	5139	1	0	0
T2	24618	470	0	0
T3	290115	14750	0	0
T7	202236	661	0	0
T8	24617	1	0	0
T9	547724	9709	0	0
T10	1746	17	0	0
T11	4124	17	0	0
T12	181889	828	0	0
T13	17158	170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	580533	0	0
T2	24618	63	0	0
T3	290115	8864	0	0
T7	202236	205	0	0
T8	24617	0	0	0
T9	547724	2717	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	218	0	0
T13	17158	179	0	0
T14	2610	14	0	0
T15	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	220713	0	0
T2	24618	62	0	0
T3	290115	2436	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	16	0	0
T11	4124	1	0	0
T12	181889	172	0	0
T13	17158	174	0	0
T14	2610	14	0	0
T15	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	227958	0	0
GntImpliesValid_A	415148816	227958	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	227958	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3041769	0	0
ReadyAndValidImplyGrant_A	415148816	227958	0	0
ReqAndReadyImplyGrant_A	415148816	227958	0	0
ReqImpliesValid_A	415148816	630395	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	227958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3041769	0	0
T1	5139	1	0	0
T2	24618	510	0	0
T3	290115	6471	0	0
T7	202236	695	0	0
T8	24617	1	0	0
T9	547724	7086	0	0
T10	1746	17	0	0
T11	4124	36	0	0
T12	181889	660	0	0
T13	17158	180	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	630395	0	0
T2	24618	91	0	0
T3	290115	1662	0	0
T7	202236	247	0	0
T8	24617	0	0	0
T9	547724	435	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	212	0	0
T13	17158	195	0	0
T14	2610	15	0	0
T15	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	227958	0	0
T2	24618	65	0	0
T3	290115	1005	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	18	0	0
T11	4124	5	0	0
T12	181889	162	0	0
T13	17158	187	0	0
T14	2610	15	0	0
T15	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	213421	0	0
GntImpliesValid_A	415148816	213421	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	213421	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	5162362	0	0
ReadyAndValidImplyGrant_A	415148816	213421	0	0
ReqAndReadyImplyGrant_A	415148816	213421	0	0
ReqImpliesValid_A	415148816	1088485	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	213421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	5162362	0	0
T2	24618	812	0	0
T3	290115	7667	0	0
T7	202236	1678	0	0
T8	24617	49	0	0
T9	547724	4353	0	0
T10	1746	69	0	0
T11	4124	0	0	0
T12	181889	1706	0	0
T13	17158	990	0	0
T14	2610	100	0	0
T15	0	81	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	1088485	0	0
T2	24618	117	0	0
T3	290115	718	0	0
T7	202236	283	0	0
T8	24617	5188	0	0
T9	547724	22	0	0
T10	1746	23	0	0
T11	4124	0	0	0
T12	181889	284	0	0
T13	17158	281	0	0
T14	2610	32	0	0
T15	0	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	213421	0	0
T2	24618	62	0	0
T3	290115	558	0	0
T7	202236	168	0	0
T8	24617	956	0	0
T9	547724	22	0	0
T10	1746	15	0	0
T11	4124	0	0	0
T12	181889	157	0	0
T13	17158	179	0	0
T14	2610	17	0	0
T15	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	211185	0	0
GntImpliesValid_A	415148816	211185	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	211185	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	4735668	0	0
ReadyAndValidImplyGrant_A	415148816	211185	0	0
ReqAndReadyImplyGrant_A	415148816	211185	0	0
ReqImpliesValid_A	415148816	1106213	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	211185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	4735668	0	0
T2	24618	698	0	0
T3	290115	4102	0	0
T7	202236	758	0	0
T8	24617	0	0	0
T9	547724	9549	0	0
T10	1746	81	0	0
T11	4124	43	0	0
T12	181889	1030	0	0
T13	17158	2881	0	0
T14	2610	98	0	0
T15	0	56	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	1106213	0	0
T2	24618	110	0	0
T3	290115	593	0	0
T7	202236	187	0	0
T8	24617	0	0	0
T9	547724	3060	0	0
T10	1746	45	0	0
T11	4124	5	0	0
T12	181889	237	0	0
T13	17158	581	0	0
T14	2610	12	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	211185	0	0
T2	24618	76	0	0
T3	290115	550	0	0
T7	202236	163	0	0
T8	24617	0	0	0
T9	547724	35	0	0
T10	1746	20	0	0
T11	4124	5	0	0
T12	181889	182	0	0
T13	17158	159	0	0
T14	2610	12	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	205701	0	0
GntImpliesValid_A	415148816	205701	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	205701	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	4951405	0	0
ReadyAndValidImplyGrant_A	415148816	205701	0	0
ReqAndReadyImplyGrant_A	415148816	205701	0	0
ReqImpliesValid_A	415148816	1042297	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	205701	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	4951405	0	0
T2	24618	660	0	0
T3	290115	13501	0	0
T7	202236	1856	0	0
T8	24617	9	0	0
T9	547724	8732	0	0
T10	1746	56	0	0
T11	4124	1575	0	0
T12	181889	1087	0	0
T13	17158	1134	0	0
T14	2610	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	1042297	0	0
T2	24618	123	0	0
T3	290115	997	0	0
T7	202236	383	0	0
T8	24617	2053	0	0
T9	547724	1049	0	0
T10	1746	11	0	0
T11	4124	583	0	0
T12	181889	231	0	0
T13	17158	332	0	0
T14	2610	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205701	0	0
T2	24618	82	0	0
T3	290115	537	0	0
T7	202236	173	0	0
T8	24617	460	0	0
T9	547724	31	0	0
T10	1746	11	0	0
T11	4124	170	0	0
T12	181889	177	0	0
T13	17158	185	0	0
T14	2610	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	212776	0	0
GntImpliesValid_A	415148816	212776	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	212776	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	5305156	0	0
ReadyAndValidImplyGrant_A	415148816	212776	0	0
ReqAndReadyImplyGrant_A	415148816	212776	0	0
ReqImpliesValid_A	415148816	1315662	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	212776	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	5305156	0	0
T2	24618	485	0	0
T3	290115	4895	0	0
T7	202236	1037	0	0
T8	24617	0	0	0
T9	547724	56164	0	0
T10	1746	73	0	0
T11	4124	89	0	0
T12	181889	2253	0	0
T13	17158	4828	0	0
T14	2610	120	0	0
T15	0	56	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	1315662	0	0
T2	24618	81	0	0
T3	290115	673	0	0
T7	202236	229	0	0
T8	24617	0	0	0
T9	547724	573	0	0
T10	1746	21	0	0
T11	4124	7	0	0
T12	181889	294	0	0
T13	17158	1210	0	0
T14	2610	30	0	0
T15	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	212776	0	0
T2	24618	64	0	0
T3	290115	574	0	0
T7	202236	172	0	0
T8	24617	0	0	0
T9	547724	32	0	0
T10	1746	16	0	0
T11	4124	7	0	0
T12	181889	172	0	0
T13	17158	198	0	0
T14	2610	18	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	209684	0	0
GntImpliesValid_A	415148816	209684	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	209684	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	2985552	0	0
ReadyAndValidImplyGrant_A	415148816	209684	0	0
ReqAndReadyImplyGrant_A	415148816	209684	0	0
ReqImpliesValid_A	415148816	579827	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	209684	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2985552	0	0
T1	5139	2	0	0
T2	24618	649	0	0
T3	290115	4506	0	0
T7	202236	551	0	0
T8	24617	1	0	0
T9	547724	9723	0	0
T10	1746	18	0	0
T11	4124	29	0	0
T12	181889	701	0	0
T13	17158	197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	579827	0	0
T1	5139	1015	0	0
T2	24618	148	0	0
T3	290115	683	0	0
T7	202236	167	0	0
T8	24617	0	0	0
T9	547724	313	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	198	0	0
T13	17158	214	0	0
T14	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209684	0	0
T1	5139	508	0	0
T2	24618	81	0	0
T3	290115	575	0	0
T7	202236	141	0	0
T8	24617	0	0	0
T9	547724	33	0	0
T10	1746	17	0	0
T11	4124	3	0	0
T12	181889	162	0	0
T13	17158	205	0	0
T14	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	206721	0	0
GntImpliesValid_A	415148816	206721	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	206721	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3029430	0	0
ReadyAndValidImplyGrant_A	415148816	206721	0	0
ReqAndReadyImplyGrant_A	415148816	206721	0	0
ReqImpliesValid_A	415148816	546398	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	206721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3029430	0	0
T1	5139	1	0	0
T2	24618	461	0	0
T3	290115	8056	0	0
T7	202236	633	0	0
T8	24617	1	0	0
T9	547724	12901	0	0
T10	1746	15	0	0
T11	4124	41	0	0
T12	181889	723	0	0
T13	17158	184	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	546398	0	0
T2	24618	86	0	0
T3	290115	1970	0	0
T7	202236	219	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	188	0	0
T13	17158	195	0	0
T14	2610	13	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	206721	0	0
T2	24618	68	0	0
T3	290115	1076	0	0
T7	202236	159	0	0
T8	24617	0	0	0
T9	547724	34	0	0
T10	1746	14	0	0
T11	4124	5	0	0
T12	181889	166	0	0
T13	17158	189	0	0
T14	2610	13	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	215391	0	0
GntImpliesValid_A	415148816	215391	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	215391	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3008144	0	0
ReadyAndValidImplyGrant_A	415148816	215391	0	0
ReqAndReadyImplyGrant_A	415148816	215391	0	0
ReqImpliesValid_A	415148816	600674	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	215391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3008144	0	0
T1	5139	1	0	0
T2	24618	642	0	0
T3	290115	6945	0	0
T7	202236	722	0	0
T8	24617	8	0	0
T9	547724	9140	0	0
T10	1746	12	0	0
T11	4124	36	0	0
T12	181889	730	0	0
T13	17158	191	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	600674	0	0
T2	24618	125	0	0
T3	290115	1719	0	0
T7	202236	201	0	0
T8	24617	1939	0	0
T9	547724	473	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	205	0	0
T13	17158	220	0	0
T14	2610	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215391	0	0
T2	24618	85	0	0
T3	290115	1051	0	0
T7	202236	165	0	0
T8	24617	973	0	0
T9	547724	27	0	0
T10	1746	11	0	0
T11	4124	3	0	0
T12	181889	168	0	0
T13	17158	205	0	0
T14	2610	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	209545	0	0
GntImpliesValid_A	415148816	209545	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	209545	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3031902	0	0
ReadyAndValidImplyGrant_A	415148816	209545	0	0
ReqAndReadyImplyGrant_A	415148816	209545	0	0
ReqImpliesValid_A	415148816	571414	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	209545	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3031902	0	0
T1	5139	1	0	0
T2	24618	473	0	0
T3	290115	14000	0	0
T7	202236	766	0	0
T8	24617	51	0	0
T9	547724	9181	0	0
T10	1746	23	0	0
T11	4124	27	0	0
T12	181889	771	0	0
T13	17158	183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	571414	0	0
T2	24618	101	0	0
T3	290115	4970	0	0
T7	202236	223	0	0
T8	24617	880	0	0
T9	547724	1786	0	0
T10	1746	24	0	0
T11	4124	2	0	0
T12	181889	216	0	0
T13	17158	190	0	0
T14	2610	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	209545	0	0
T2	24618	59	0	0
T3	290115	2027	0	0
T7	202236	179	0	0
T8	24617	465	0	0
T9	547724	29	0	0
T10	1746	23	0	0
T11	4124	2	0	0
T12	181889	176	0	0
T13	17158	186	0	0
T14	2610	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	207419	0	0
GntImpliesValid_A	415148816	207419	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	207419	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3019559	0	0
ReadyAndValidImplyGrant_A	415148816	207419	0	0
ReqAndReadyImplyGrant_A	415148816	207419	0	0
ReqImpliesValid_A	415148816	549249	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	207419	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3019559	0	0
T1	5139	1	0	0
T2	24618	398	0	0
T3	290115	4123	0	0
T7	202236	709	0	0
T8	24617	74	0	0
T9	547724	11187	0	0
T10	1746	16	0	0
T11	4124	53	0	0
T12	181889	708	0	0
T13	17158	161	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	549249	0	0
T2	24618	125	0	0
T3	290115	572	0	0
T7	202236	186	0	0
T8	24617	947	0	0
T9	547724	1408	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	173	0	0
T13	17158	174	0	0
T14	2610	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	207419	0	0
T2	24618	68	0	0
T3	290115	538	0	0
T7	202236	165	0	0
T8	24617	510	0	0
T9	547724	38	0	0
T10	1746	15	0	0
T11	4124	4	0	0
T12	181889	160	0	0
T13	17158	167	0	0
T14	2610	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	221013	0	0
GntImpliesValid_A	415148816	221013	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	221013	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3078815	0	0
ReadyAndValidImplyGrant_A	415148816	221013	0	0
ReqAndReadyImplyGrant_A	415148816	221013	0	0
ReqImpliesValid_A	415148816	620442	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	221013	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3078815	0	0
T1	5139	1	0	0
T2	24618	434	0	0
T3	290115	7925	0	0
T7	202236	695	0	0
T8	24617	38	0	0
T9	547724	15170	0	0
T10	1746	12	0	0
T11	4124	51	0	0
T12	181889	829	0	0
T13	17158	187	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	620442	0	0
T2	24618	71	0	0
T3	290115	2082	0	0
T7	202236	199	0	0
T8	24617	2123	0	0
T9	547724	130	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	223	0	0
T13	17158	198	0	0
T14	2610	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	221013	0	0
T2	24618	58	0	0
T3	290115	1055	0	0
T7	202236	165	0	0
T8	24617	1080	0	0
T9	547724	42	0	0
T10	1746	11	0	0
T11	4124	7	0	0
T12	181889	191	0	0
T13	17158	192	0	0
T14	2610	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	215759	0	0
GntImpliesValid_A	415148816	215759	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	215759	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	2971239	0	0
ReadyAndValidImplyGrant_A	415148816	215759	0	0
ReqAndReadyImplyGrant_A	415148816	215759	0	0
ReqImpliesValid_A	415148816	558078	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	215759	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2971239	0	0
T1	5139	1	0	0
T2	24618	517	0	0
T3	290115	6563	0	0
T7	202236	719	0	0
T8	24617	4	0	0
T9	547724	9719	0	0
T10	1746	13	0	0
T11	4124	23	0	0
T12	181889	814	0	0
T13	17158	172	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	558078	0	0
T2	24618	100	0	0
T3	290115	1700	0	0
T7	202236	191	0	0
T8	24617	825	0	0
T9	547724	920	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	222	0	0
T13	17158	203	0	0
T14	2610	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	215759	0	0
T2	24618	72	0	0
T3	290115	993	0	0
T7	202236	152	0	0
T8	24617	414	0	0
T9	547724	29	0	0
T10	1746	12	0	0
T11	4124	2	0	0
T12	181889	173	0	0
T13	17158	187	0	0
T14	2610	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	202600	0	0
GntImpliesValid_A	415148816	202600	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	202600	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3000115	0	0
ReadyAndValidImplyGrant_A	415148816	202600	0	0
ReqAndReadyImplyGrant_A	415148816	202600	0	0
ReqImpliesValid_A	415148816	548475	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	202600	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3000115	0	0
T1	5139	14	0	0
T2	24618	536	0	0
T3	290115	7356	0	0
T7	202236	652	0	0
T8	24617	105	0	0
T9	547724	8360	0	0
T10	1746	18	0	0
T11	4124	47	0	0
T12	181889	649	0	0
T13	17158	183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	548475	0	0
T1	5139	939	0	0
T2	24618	73	0	0
T3	290115	1858	0	0
T7	202236	172	0	0
T8	24617	1960	0	0
T9	547724	291	0	0
T10	1746	19	0	0
T11	4124	7	0	0
T12	181889	176	0	0
T13	17158	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	202600	0	0
T1	5139	476	0	0
T2	24618	68	0	0
T3	290115	1010	0	0
T7	202236	151	0	0
T8	24617	1032	0	0
T9	547724	29	0	0
T10	1746	18	0	0
T11	4124	7	0	0
T12	181889	154	0	0
T13	17158	188	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	236238	0	0
GntImpliesValid_A	415148816	236238	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	236238	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3129456	0	0
ReadyAndValidImplyGrant_A	415148816	236238	0	0
ReqAndReadyImplyGrant_A	415148816	236238	0	0
ReqImpliesValid_A	415148816	621653	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	236238	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3129456	0	0
T1	5139	1	0	0
T2	24618	470	0	0
T3	290115	4722	0	0
T7	202236	708	0	0
T8	24617	1	0	0
T9	547724	6275	0	0
T10	1746	31	0	0
T11	4124	73	0	0
T12	181889	779	0	0
T13	17158	182	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	621653	0	0
T2	24618	94	0	0
T3	290115	726	0	0
T7	202236	219	0	0
T8	24617	0	0	0
T9	547724	437	0	0
T10	1746	34	0	0
T11	4124	6	0	0
T12	181889	211	0	0
T13	17158	205	0	0
T14	2610	12	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	236238	0	0
T2	24618	69	0	0
T3	290115	643	0	0
T7	202236	170	0	0
T8	24617	0	0	0
T9	547724	24	0	0
T10	1746	32	0	0
T11	4124	6	0	0
T12	181889	178	0	0
T13	17158	193	0	0
T14	2610	11	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	205409	0	0
GntImpliesValid_A	415148816	205409	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	205409	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	2994696	0	0
ReadyAndValidImplyGrant_A	415148816	205409	0	0
ReqAndReadyImplyGrant_A	415148816	205409	0	0
ReqImpliesValid_A	415148816	526774	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	205409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2994696	0	0
T1	5139	1	0	0
T2	24618	486	0	0
T3	290115	4214	0	0
T7	202236	721	0	0
T8	24617	39	0	0
T9	547724	14992	0	0
T10	1746	13	0	0
T11	4124	43	0	0
T12	181889	821	0	0
T13	17158	183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	526774	0	0
T2	24618	76	0	0
T3	290115	607	0	0
T7	202236	243	0	0
T8	24617	1960	0	0
T9	547724	218	0	0
T10	1746	14	0	0
T11	4124	4	0	0
T12	181889	205	0	0
T13	17158	202	0	0
T14	2610	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	205409	0	0
T2	24618	68	0	0
T3	290115	548	0	0
T7	202236	169	0	0
T8	24617	999	0	0
T9	547724	39	0	0
T10	1746	13	0	0
T11	4124	4	0	0
T12	181889	174	0	0
T13	17158	192	0	0
T14	2610	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	218652	0	0
GntImpliesValid_A	415148816	218652	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	218652	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3068751	0	0
ReadyAndValidImplyGrant_A	415148816	218652	0	0
ReqAndReadyImplyGrant_A	415148816	218652	0	0
ReqImpliesValid_A	415148816	560568	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	218652	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3068751	0	0
T1	5139	1	0	0
T2	24618	621	0	0
T3	290115	4192	0	0
T7	202236	777	0	0
T8	24617	6	0	0
T9	547724	11641	0	0
T10	1746	23	0	0
T11	4124	39	0	0
T12	181889	693	0	0
T13	17158	173	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	560568	0	0
T2	24618	132	0	0
T3	290115	610	0	0
T7	202236	197	0	0
T8	24617	1843	0	0
T9	547724	714	0	0
T10	1746	24	0	0
T11	4124	3	0	0
T12	181889	201	0	0
T13	17158	192	0	0
T14	2610	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	218652	0	0
T2	24618	75	0	0
T3	290115	554	0	0
T7	202236	164	0	0
T8	24617	924	0	0
T9	547724	30	0	0
T10	1746	23	0	0
T11	4124	3	0	0
T12	181889	166	0	0
T13	17158	182	0	0
T14	2610	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	216418	0	0
GntImpliesValid_A	415148816	216418	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	216418	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3074057	0	0
ReadyAndValidImplyGrant_A	415148816	216418	0	0
ReqAndReadyImplyGrant_A	415148816	216418	0	0
ReqImpliesValid_A	415148816	537080	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	216418	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3074057	0	0
T1	5139	1	0	0
T2	24618	505	0	0
T3	290115	4299	0	0
T7	202236	819	0	0
T8	24617	1	0	0
T9	547724	6468	0	0
T10	1746	20	0	0
T11	4124	38	0	0
T12	181889	547	0	0
T13	17158	175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	537080	0	0
T2	24618	107	0	0
T3	290115	648	0	0
T7	202236	231	0	0
T8	24617	0	0	0
T9	547724	1271	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	171	0	0
T13	17158	186	0	0
T14	2610	18	0	0
T15	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	216418	0	0
T2	24618	71	0	0
T3	290115	569	0	0
T7	202236	191	0	0
T8	24617	0	0	0
T9	547724	26	0	0
T10	1746	19	0	0
T11	4124	5	0	0
T12	181889	127	0	0
T13	17158	180	0	0
T14	2610	16	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	219052	0	0
GntImpliesValid_A	415148816	219052	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	219052	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	3093043	0	0
ReadyAndValidImplyGrant_A	415148816	219052	0	0
ReqAndReadyImplyGrant_A	415148816	219052	0	0
ReqImpliesValid_A	415148816	558631	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	219052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	3093043	0	0
T1	5139	1	0	0
T2	24618	466	0	0
T3	290115	4214	0	0
T7	202236	723	0	0
T8	24617	1	0	0
T9	547724	13175	0	0
T10	1746	18	0	0
T11	4124	74	0	0
T12	181889	769	0	0
T13	17158	187	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	558631	0	0
T2	24618	92	0	0
T3	290115	632	0	0
T7	202236	233	0	0
T8	24617	0	0	0
T9	547724	727	0	0
T10	1746	19	0	0
T11	4124	8	0	0
T12	181889	212	0	0
T13	17158	206	0	0
T14	2610	6	0	0
T15	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	219052	0	0
T2	24618	60	0	0
T3	290115	549	0	0
T7	202236	190	0	0
T8	24617	0	0	0
T9	547724	41	0	0
T10	1746	18	0	0
T11	4124	8	0	0
T12	181889	166	0	0
T13	17158	196	0	0
T14	2610	6	0	0
T15	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	197530	0	0
GntImpliesValid_A	415148816	197530	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	197530	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	2981513	0	0
ReadyAndValidImplyGrant_A	415148816	197530	0	0
ReqAndReadyImplyGrant_A	415148816	197530	0	0
ReqImpliesValid_A	415148816	483934	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	0	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	197530	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2981513	0	0
T1	5139	1	0	0
T2	24618	427	0	0
T3	290115	4359	0	0
T7	202236	740	0	0
T8	24617	39	0	0
T9	547724	9465	0	0
T10	1746	15	0	0
T11	4124	9	0	0
T12	181889	670	0	0
T13	17158	197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	483934	0	0
T2	24618	65	0	0
T3	290115	609	0	0
T7	202236	187	0	0
T8	24617	2088	0	0
T9	547724	204	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	177	0	0
T13	17158	228	0	0
T14	2610	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	197530	0	0
T2	24618	57	0	0
T3	290115	565	0	0
T7	202236	169	0	0
T8	24617	1063	0	0
T9	547724	32	0	0
T10	1746	14	0	0
T11	4124	1	0	0
T12	181889	154	0	0
T13	17158	212	0	0
T14	2610	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	881352	0	0
GntImpliesValid_A	415148816	881352	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	881352	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	11482801	0	0
ReadyAndValidImplyGrant_A	415148816	881352	0	0
ReqAndReadyImplyGrant_A	415148816	881352	0	0
ReqImpliesValid_A	415148816	2370183	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	19266	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	881352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	11482801	0	0
T1	5139	1	0	0
T2	24618	1452	0	0
T3	290115	22561	0	0
T7	202236	2327	0	0
T8	24617	1	0	0
T9	547724	42581	0	0
T10	1746	1	0	0
T11	4124	265	0	0
T12	181889	2111	0	0
T13	17158	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	2370183	0	0
T1	5139	868	0	0
T2	24618	387	0	0
T3	290115	9962	0	0
T7	202236	869	0	0
T8	24617	1852	0	0
T9	547724	8544	0	0
T10	1746	59	0	0
T11	4124	61	0	0
T12	181889	826	0	0
T13	17158	693	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	19266	0	900
T1	5139	282	0	1
T2	24618	0	0	1
T3	290115	9	0	1
T7	202236	0	0	1
T8	24617	300	0	1
T9	547724	0	0	1
T10	1746	0	0	1
T11	4124	0	0	1
T12	181889	0	0	1
T13	17158	7	0	1
T17	0	55	0	0
T18	0	1	0	0
T19	0	5	0	0
T20	0	16	0	0
T21	0	5	0	0
T22	0	420	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	881352	0	0
T1	5139	868	0	0
T2	24618	244	0	0
T3	290115	3822	0	0
T7	202236	668	0	0
T8	24617	1852	0	0
T9	547724	146	0	0
T10	1746	59	0	0
T11	4124	45	0	0
T12	181889	635	0	0
T13	17158	693	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415148816	415027262	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	415148816	845569	0	0
GntImpliesValid_A	415148816	845569	0	0
GrantKnown_A	415148816	415027262	0	0
IdxKnown_A	415148816	415027262	0	0
IndexIsCorrect_A	415148816	845569	0	0
LockArbDecision_A	415148816	0	0	0
NoReadyValidNoGrant_A	415148816	348678673	0	0
ReadyAndValidImplyGrant_A	415148816	845569	0	0
ReqAndReadyImplyGrant_A	415148816	845569	0	0
ReqImpliesValid_A	415148816	13171089	0	0
ReqStaysHighUntilGranted0_M	415148816	0	0	0
RoundRobin_A	415148816	27973	0	900
ValidKnown_A	415148816	415027262	0	0
gen_data_port_assertion.DataFlow_A	415148816	845569	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	348678673	0	0
T1	5139	1	0	0
T2	24618	20441	0	0
T3	290115	236936	0	0
T7	202236	168149	0	0
T8	24617	1	0	0
T9	547724	490814	0	0
T10	1746	1	0	0
T11	4124	3481	0	0
T12	181889	151285	0	0
T13	17158	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	13171089	0	0
T1	5139	1545	0	0
T2	24618	2176	0	0
T3	290115	30392	0	0
T7	202236	3151	0	0
T8	24617	1888	0	0
T9	547724	55906	0	0
T10	1746	56	0	0
T11	4124	176	0	0
T12	181889	3202	0	0
T13	17158	670	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	27973	0	900
T1	5139	887	0	1
T2	24618	0	0	1
T3	290115	5	0	1
T7	202236	0	0	1
T8	24617	486	0	1
T9	547724	0	0	1
T10	1746	1	0	1
T11	4124	0	0	1
T12	181889	0	0	1
T13	17158	8	0	1
T16	0	1	0	0
T19	0	6	0	0
T20	0	19	0	0
T21	0	19	0	0
T22	0	235	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	415027262	0	0
T1	5139	5090	0	0
T2	24618	24591	0	0
T3	290115	290070	0	0
T7	202236	202234	0	0
T8	24617	24607	0	0
T9	547724	547664	0	0
T10	1746	1702	0	0
T11	4124	3984	0	0
T12	181889	181886	0	0
T13	17158	17087	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415148816	845569	0	0
T1	5139	1545	0	0
T2	24618	252	0	0
T3	290115	3653	0	0
T7	202236	710	0	0
T8	24617	1888	0	0
T9	547724	150	0	0
T10	1746	56	0	0
T11	4124	25	0	0
T12	181889	713	0	0
T13	17158	670	0	0