Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1523093 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 242606 1 T1 239 T2 262 T3 12


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 599623 1 T1 444 T2 594 T3 49
values[0x0] 568398 1 T1 533 T2 583 T3 49
values[0x1] 597678 1 T1 471 T2 605 T3 44


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1177979 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 587720 1 T1 490 T2 615 T3 40


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27493 1 T1 16 T2 23 T3 7
valid_sources[0x01] 26964 1 T1 25 T2 21 T3 1
valid_sources[0x02] 27687 1 T1 30 T2 34 T3 4
valid_sources[0x03] 27772 1 T1 17 T2 26 T3 1
valid_sources[0x04] 27123 1 T1 21 T2 16 T3 2
valid_sources[0x05] 27985 1 T1 15 T2 23 T3 10
valid_sources[0x06] 28388 1 T1 26 T2 20 T3 2
valid_sources[0x07] 27956 1 T1 28 T2 33 T3 2
valid_sources[0x08] 27116 1 T1 29 T2 29 T3 1
valid_sources[0x09] 27047 1 T1 27 T2 30 T3 7
valid_sources[0x0a] 28081 1 T1 26 T2 16 T3 2
valid_sources[0x0b] 26780 1 T1 24 T2 33 T7 121
valid_sources[0x0c] 27642 1 T1 19 T2 28 T7 64
valid_sources[0x0d] 26704 1 T1 23 T2 33 T3 2
valid_sources[0x0e] 27427 1 T1 27 T2 25 T3 2
valid_sources[0x0f] 27247 1 T1 16 T2 32 T7 68
valid_sources[0x10] 28370 1 T1 28 T2 31 T7 108
valid_sources[0x11] 27303 1 T1 22 T2 34 T7 69
valid_sources[0x12] 28183 1 T1 14 T2 21 T7 127
valid_sources[0x13] 27098 1 T1 20 T2 24 T3 6
valid_sources[0x14] 28200 1 T1 21 T2 23 T3 2
valid_sources[0x15] 27533 1 T1 26 T2 22 T3 1
valid_sources[0x16] 27018 1 T1 18 T2 38 T3 1
valid_sources[0x17] 27687 1 T1 28 T2 21 T3 2
valid_sources[0x18] 27562 1 T1 33 T2 25 T3 2
valid_sources[0x19] 27752 1 T1 19 T2 33 T7 40
valid_sources[0x1a] 27693 1 T1 22 T2 25 T7 65
valid_sources[0x1b] 27195 1 T1 25 T2 19 T3 3
valid_sources[0x1c] 28199 1 T1 19 T2 30 T3 1
valid_sources[0x1d] 27155 1 T1 20 T2 28 T7 99
valid_sources[0x1e] 27180 1 T1 38 T2 34 T7 83
valid_sources[0x1f] 27425 1 T1 26 T2 26 T7 54
valid_sources[0x20] 27894 1 T1 19 T2 34 T3 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25312 1 T1 19 T2 29 T7 86
values[0x0] all_enables biggest_size 192048 1 T1 199 T2 200 T3 12
values[0x1] all_enables biggest_size 25246 1 T1 21 T2 33 T7 65


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1533904 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 250119 1 T1 191 T2 253 T3 25


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 610280 1 T1 479 T2 620 T3 60
values[0x0] 563921 1 T1 490 T2 567 T3 61
values[0x1] 609822 1 T1 503 T2 600 T3 55


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1178211 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605812 1 T1 457 T2 608 T3 56


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28749 1 T1 22 T2 21 T3 1
valid_sources[0x01] 27611 1 T1 26 T2 48 T3 6
valid_sources[0x02] 27850 1 T1 25 T2 13 T3 7
valid_sources[0x03] 27962 1 T1 22 T2 21 T3 4
valid_sources[0x04] 27608 1 T1 21 T2 20 T3 7
valid_sources[0x05] 28208 1 T1 31 T2 18 T3 1
valid_sources[0x06] 28599 1 T1 17 T2 27 T3 6
valid_sources[0x07] 28362 1 T1 37 T2 18 T7 50
valid_sources[0x08] 27807 1 T1 15 T2 37 T3 2
valid_sources[0x09] 28085 1 T1 28 T2 22 T3 4
valid_sources[0x0a] 27458 1 T1 23 T2 24 T3 3
valid_sources[0x0b] 26893 1 T1 18 T2 17 T3 2
valid_sources[0x0c] 27587 1 T1 20 T2 10 T3 4
valid_sources[0x0d] 27650 1 T1 20 T2 47 T7 86
valid_sources[0x0e] 27688 1 T1 19 T2 19 T3 3
valid_sources[0x0f] 27628 1 T1 21 T2 22 T3 5
valid_sources[0x10] 27522 1 T1 25 T2 28 T3 1
valid_sources[0x11] 27653 1 T1 15 T2 8 T3 1
valid_sources[0x12] 28497 1 T1 25 T2 9 T3 3
valid_sources[0x13] 27750 1 T1 22 T2 52 T3 4
valid_sources[0x14] 28068 1 T1 25 T2 13 T7 62
valid_sources[0x15] 27797 1 T1 20 T2 26 T3 1
valid_sources[0x16] 27862 1 T1 24 T2 48 T3 3
valid_sources[0x17] 27212 1 T1 26 T2 39 T7 77
valid_sources[0x18] 27719 1 T1 23 T2 23 T3 2
valid_sources[0x19] 27600 1 T1 15 T2 38 T3 1
valid_sources[0x1a] 28110 1 T1 33 T2 18 T3 4
valid_sources[0x1b] 27843 1 T1 17 T2 6 T3 3
valid_sources[0x1c] 26959 1 T1 35 T2 27 T3 2
valid_sources[0x1d] 27581 1 T1 33 T2 46 T3 3
valid_sources[0x1e] 28240 1 T1 30 T2 32 T3 3
valid_sources[0x1f] 27721 1 T1 20 T2 39 T3 1
valid_sources[0x20] 27962 1 T1 18 T2 29 T3 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26125 1 T1 15 T2 29 T3 3
values[0x0] all_enables biggest_size 197713 1 T1 159 T2 204 T3 19
values[0x1] all_enables biggest_size 26281 1 T1 17 T2 20 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1533457 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 243573 1 T1 195 T2 256 T3 17


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 603807 1 T1 483 T2 588 T3 43
values[0x0] 571445 1 T1 442 T2 551 T3 41
values[0x1] 601778 1 T1 486 T2 537 T3 41


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1185087 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 591943 1 T1 466 T2 590 T3 38


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27448 1 T1 21 T2 47 T7 91
valid_sources[0x01] 27454 1 T1 22 T2 7 T3 4
valid_sources[0x02] 28138 1 T1 17 T2 11 T3 1
valid_sources[0x03] 27731 1 T1 22 T3 1 T7 66
valid_sources[0x04] 27960 1 T1 25 T7 62 T11 17
valid_sources[0x05] 27855 1 T1 25 T2 63 T3 1
valid_sources[0x06] 28391 1 T1 25 T2 14 T3 3
valid_sources[0x07] 28015 1 T1 29 T2 23 T3 1
valid_sources[0x08] 27637 1 T1 22 T2 19 T7 89
valid_sources[0x09] 27909 1 T1 21 T2 14 T3 6
valid_sources[0x0a] 27426 1 T1 21 T2 50 T7 99
valid_sources[0x0b] 28157 1 T1 17 T2 22 T3 3
valid_sources[0x0c] 27684 1 T1 22 T3 1 T7 99
valid_sources[0x0d] 26764 1 T1 13 T2 50 T3 1
valid_sources[0x0e] 27694 1 T1 23 T2 26 T3 2
valid_sources[0x0f] 26840 1 T1 20 T2 37 T7 33
valid_sources[0x10] 27516 1 T1 28 T2 13 T3 4
valid_sources[0x11] 28054 1 T1 22 T2 56 T3 5
valid_sources[0x12] 27853 1 T1 17 T2 15 T3 1
valid_sources[0x13] 27688 1 T1 22 T2 13 T7 57
valid_sources[0x14] 28127 1 T1 20 T2 20 T3 4
valid_sources[0x15] 27297 1 T1 18 T2 4 T7 106
valid_sources[0x16] 27951 1 T1 26 T2 19 T3 1
valid_sources[0x17] 27489 1 T1 8 T2 34 T3 1
valid_sources[0x18] 27642 1 T1 28 T2 11 T3 1
valid_sources[0x19] 27385 1 T1 16 T2 38 T3 1
valid_sources[0x1a] 27447 1 T1 22 T2 36 T3 2
valid_sources[0x1b] 27945 1 T1 27 T2 33 T3 4
valid_sources[0x1c] 27923 1 T1 24 T2 17 T3 1
valid_sources[0x1d] 28239 1 T1 26 T2 64 T3 5
valid_sources[0x1e] 26688 1 T1 15 T2 6 T3 4
valid_sources[0x1f] 27982 1 T1 18 T2 39 T7 87
valid_sources[0x20] 28227 1 T1 23 T2 64 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25435 1 T1 18 T2 19 T3 1
values[0x0] all_enables biggest_size 192742 1 T1 158 T2 211 T3 15
values[0x1] all_enables biggest_size 25396 1 T1 19 T2 26 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%