Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7508825	0	0
GntImpliesValid_A	2147483647	7508825	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7508825	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	426639363	0	0
ReadyAndValidImplyGrant_A	2147483647	7508825	0	0
ReqAndReadyImplyGrant_A	2147483647	7508825	0	0
ReqImpliesValid_A	2147483647	32440543	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51383	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7508825	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2651616	2651592	0	0
T2	195936	195360	0	0
T3	6482160	6481008	0	0
T7	4622496	4620912	0	0
T8	10467144	10466400	0	0
T9	59976	58632	0	0
T10	47016	45720	0	0
T11	12731832	12731496	0	0
T12	1089600	1087152	0	0
T13	7349592	7346952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2651616	2651592	0	0
T2	195936	195360	0	0
T3	6482160	6481008	0	0
T7	4622496	4620912	0	0
T8	10467144	10466400	0	0
T9	59976	58632	0	0
T10	47016	45720	0	0
T11	12731832	12731496	0	0
T12	1089600	1087152	0	0
T13	7349592	7346952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2651616	2651592	0	0
T2	195936	195360	0	0
T3	6482160	6481008	0	0
T7	4622496	4620912	0	0
T8	10467144	10466400	0	0
T9	59976	58632	0	0
T10	47016	45720	0	0
T11	12731832	12731496	0	0
T12	1089600	1087152	0	0
T13	7349592	7346952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426639363	0	0
T1	2651616	934516	0	0
T2	195936	5521	0	0
T3	6482160	226389	0	0
T7	4622496	282655	0	0
T8	10467144	544683	0	0
T9	59976	732	0	0
T10	47016	524	0	0
T11	12731832	647912	0	0
T12	1089600	29976	0	0
T13	7349592	430024	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32440543	0	0
T1	2651616	7054	0	0
T2	195936	6007	0	0
T3	6482160	775	0	0
T7	4622496	45670	0	0
T8	10467144	29072	0	0
T9	59976	573	0	0
T10	47016	435	0	0
T11	12731832	24319	0	0
T12	1089600	22752	0	0
T13	7349592	95734	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51383	0	21600
T2	16328	22	0	2
T3	540180	0	0	2
T7	385208	3	0	2
T8	872262	0	0	2
T9	4998	0	0	2
T10	3918	0	0	2
T11	1060986	0	0	2
T12	90800	365	0	2
T13	612466	3	0	2
T14	666650	1	0	2
T15	0	57	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	13	0	0
T20	0	3	0	0
T21	0	7	0	0
T22	0	54	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2651616	2651592	0	0
T2	195936	195360	0	0
T3	6482160	6481008	0	0
T7	4622496	4620912	0	0
T8	10467144	10466400	0	0
T9	59976	58632	0	0
T10	47016	45720	0	0
T11	12731832	12731496	0	0
T12	1089600	1087152	0	0
T13	7349592	7346952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7508825	0	0
T1	2651616	4330	0	0
T2	195936	5244	0	0
T3	6482160	443	0	0
T7	4622496	16388	0	0
T8	10467144	514	0	0
T9	59976	504	0	0
T10	47016	409	0	0
T11	12731832	525	0	0
T12	1089600	19944	0	0
T13	7349592	29981	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	836525	0	0
GntImpliesValid_A	393792490	836525	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	836525	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	11232239	0	0
ReadyAndValidImplyGrant_A	393792490	836525	0	0
ReqAndReadyImplyGrant_A	393792490	836525	0	0
ReqImpliesValid_A	393792490	2359535	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	836525	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	11232239	0	0
T1	110484	2046	0	0
T2	8164	435	0	0
T3	270090	246	0	0
T7	192604	16917	0	0
T8	436131	20121	0	0
T9	2499	49	0	0
T10	1959	38	0	0
T11	530493	17868	0	0
T12	45400	1637	0	0
T13	306233	22089	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2359535	0	0
T1	110484	620	0	0
T2	8164	728	0	0
T3	270090	73	0	0
T7	192604	5746	0	0
T8	436131	123	0	0
T9	2499	72	0	0
T10	1959	47	0	0
T11	530493	802	0	0
T12	45400	2255	0	0
T13	306233	4487	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	836525	0	0
T1	110484	488	0	0
T2	8164	581	0	0
T3	270090	64	0	0
T7	192604	2397	0	0
T8	436131	58	0	0
T9	2499	60	0	0
T10	1959	42	0	0
T11	530493	55	0	0
T12	45400	1945	0	0
T13	306233	2920	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	835116	0	0
GntImpliesValid_A	393792490	835116	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	835116	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	11305419	0	0
ReadyAndValidImplyGrant_A	393792490	835116	0	0
ReqAndReadyImplyGrant_A	393792490	835116	0	0
ReqImpliesValid_A	393792490	2322434	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	835116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	11305419	0	0
T1	110484	1966	0	0
T2	8164	442	0	0
T3	270090	266	0	0
T7	192604	11852	0	0
T8	436131	16823	0	0
T9	2499	41	0	0
T10	1959	46	0	0
T11	530493	19044	0	0
T12	45400	1687	0	0
T13	306233	21520	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2322434	0	0
T1	110484	686	0	0
T2	8164	751	0	0
T3	270090	95	0	0
T7	192604	2248	0	0
T8	436131	2644	0	0
T9	2499	64	0	0
T10	1959	65	0	0
T11	530493	3144	0	0
T12	45400	2261	0	0
T13	306233	4658	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	835116	0	0
T1	110484	485	0	0
T2	8164	596	0	0
T3	270090	65	0	0
T7	192604	1596	0	0
T8	436131	58	0	0
T9	2499	52	0	0
T10	1959	55	0	0
T11	530493	67	0	0
T12	45400	1973	0	0
T13	306233	3076	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	198787	0	0
GntImpliesValid_A	393792490	198787	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	198787	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2796070	0	0
ReadyAndValidImplyGrant_A	393792490	198787	0	0
ReqAndReadyImplyGrant_A	393792490	198787	0	0
ReqImpliesValid_A	393792490	546803	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	198787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2796070	0	0
T1	110484	518	0	0
T2	8164	138	0	0
T3	270090	54	0	0
T7	192604	5361	0	0
T8	436131	4158	0	0
T9	2499	19	0	0
T10	1959	14	0	0
T11	530493	3837	0	0
T12	45400	489	0	0
T13	306233	3775	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	546803	0	0
T1	110484	163	0	0
T2	8164	153	0	0
T3	270090	46	0	0
T7	192604	2479	0	0
T8	436131	686	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	66	0	0
T12	45400	507	0	0
T13	306233	546	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	198787	0	0
T1	110484	135	0	0
T2	8164	145	0	0
T3	270090	16	0	0
T7	192604	847	0	0
T8	436131	12	0	0
T9	2499	18	0	0
T10	1959	13	0	0
T11	530493	12	0	0
T12	45400	497	0	0
T13	306233	479	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	211316	0	0
GntImpliesValid_A	393792490	211316	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	211316	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2842019	0	0
ReadyAndValidImplyGrant_A	393792490	211316	0	0
ReqAndReadyImplyGrant_A	393792490	211316	0	0
ReqImpliesValid_A	393792490	562052	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	211316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2842019	0	0
T1	110484	543	0	0
T2	8164	129	0	0
T3	270090	59	0	0
T7	192604	2485	0	0
T8	436131	5362	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	4621	0	0
T12	45400	466	0	0
T13	306233	6138	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	562052	0	0
T1	110484	180	0	0
T2	8164	146	0	0
T3	270090	14	0	0
T7	192604	325	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	146	0	0
T12	45400	486	0	0
T13	306233	4199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	211316	0	0
T1	110484	137	0	0
T2	8164	137	0	0
T3	270090	14	0	0
T7	192604	303	0	0
T8	436131	14	0	0
T9	2499	5	0	0
T10	1959	7	0	0
T11	530493	16	0	0
T12	45400	475	0	0
T13	306233	1062	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	196923	0	0
GntImpliesValid_A	393792490	196923	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	196923	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	5283184	0	0
ReadyAndValidImplyGrant_A	393792490	196923	0	0
ReqAndReadyImplyGrant_A	393792490	196923	0	0
ReqImpliesValid_A	393792490	1173275	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	196923	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	5283184	0	0
T1	110484	646	0	0
T2	8164	551	0	0
T3	270090	102	0	0
T7	192604	8179	0	0
T8	436131	1717	0	0
T9	2499	121	0	0
T10	1959	81	0	0
T11	530493	539	0	0
T12	45400	3204	0	0
T13	306233	6327	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	1173275	0	0
T1	110484	138	0	0
T2	8164	252	0	0
T3	270090	12	0	0
T7	192604	3092	0	0
T8	436131	173	0	0
T9	2499	33	0	0
T10	1959	19	0	0
T11	530493	8	0	0
T12	45400	723	0	0
T13	306233	5472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196923	0	0
T1	110484	111	0	0
T2	8164	149	0	0
T3	270090	11	0	0
T7	192604	729	0	0
T8	436131	11	0	0
T9	2499	23	0	0
T10	1959	14	0	0
T11	530493	8	0	0
T12	45400	524	0	0
T13	306233	1095	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	196576	0	0
GntImpliesValid_A	393792490	196576	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	196576	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	4660047	0	0
ReadyAndValidImplyGrant_A	393792490	196576	0	0
ReqAndReadyImplyGrant_A	393792490	196576	0	0
ReqImpliesValid_A	393792490	964670	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	196576	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	4660047	0	0
T1	110484	1064	0	0
T2	8164	569	0	0
T3	270090	63	0	0
T7	192604	3578	0	0
T8	436131	1709	0	0
T9	2499	88	0	0
T10	1959	102	0	0
T11	530493	2970	0	0
T12	45400	2444	0	0
T13	306233	4499	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	964670	0	0
T1	110484	119	0	0
T2	8164	192	0	0
T3	270090	25	0	0
T7	192604	418	0	0
T8	436131	8	0	0
T9	2499	20	0	0
T10	1959	12	0	0
T11	530493	125	0	0
T12	45400	641	0	0
T13	306233	558	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	196576	0	0
T1	110484	105	0	0
T2	8164	128	0	0
T3	270090	10	0	0
T7	192604	322	0	0
T8	436131	8	0	0
T9	2499	11	0	0
T10	1959	12	0	0
T11	530493	22	0	0
T12	45400	485	0	0
T13	306233	510	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	209465	0	0
GntImpliesValid_A	393792490	209465	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	209465	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	4181823	0	0
ReadyAndValidImplyGrant_A	393792490	209465	0	0
ReqAndReadyImplyGrant_A	393792490	209465	0	0
ReqImpliesValid_A	393792490	1024904	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	209465	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	4181823	0	0
T1	110484	589	0	0
T2	8164	513	0	0
T3	270090	164	0	0
T7	192604	5015	0	0
T8	436131	7811	0	0
T9	2499	167	0	0
T10	1959	51	0	0
T11	530493	1516	0	0
T12	45400	2748	0	0
T13	306233	5302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	1024904	0	0
T1	110484	184	0	0
T2	8164	199	0	0
T3	270090	29	0	0
T7	192604	461	0	0
T8	436131	14	0	0
T9	2499	26	0	0
T10	1959	17	0	0
T11	530493	206	0	0
T12	45400	565	0	0
T13	306233	742	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209465	0	0
T1	110484	125	0	0
T2	8164	137	0	0
T3	270090	7	0	0
T7	192604	341	0	0
T8	436131	13	0	0
T9	2499	16	0	0
T10	1959	12	0	0
T11	530493	19	0	0
T12	45400	435	0	0
T13	306233	509	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	207612	0	0
GntImpliesValid_A	393792490	207612	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	207612	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	4651006	0	0
ReadyAndValidImplyGrant_A	393792490	207612	0	0
ReqAndReadyImplyGrant_A	393792490	207612	0	0
ReqImpliesValid_A	393792490	1096255	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	207612	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	4651006	0	0
T1	110484	517	0	0
T2	8164	799	0	0
T3	270090	109	0	0
T7	192604	15306	0	0
T8	436131	2733	0	0
T9	2499	42	0	0
T10	1959	39	0	0
T11	530493	2872	0	0
T12	45400	10095	0	0
T13	306233	5901	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	1096255	0	0
T1	110484	142	0	0
T2	8164	192	0	0
T3	270090	15	0	0
T7	192604	7390	0	0
T8	436131	11	0	0
T9	2499	19	0	0
T10	1959	8	0	0
T11	530493	94	0	0
T12	45400	1651	0	0
T13	306233	5057	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	207612	0	0
T1	110484	121	0	0
T2	8164	116	0	0
T3	270090	10	0	0
T7	192604	1197	0	0
T8	436131	11	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	457	0	0
T13	306233	1006	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	205882	0	0
GntImpliesValid_A	393792490	205882	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	205882	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2760467	0	0
ReadyAndValidImplyGrant_A	393792490	205882	0	0
ReqAndReadyImplyGrant_A	393792490	205882	0	0
ReqImpliesValid_A	393792490	562678	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	205882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2760467	0	0
T1	110484	464	0	0
T2	8164	139	0	0
T3	270090	36	0	0
T7	192604	2321	0	0
T8	436131	3956	0	0
T9	2499	25	0	0
T10	1959	11	0	0
T11	530493	5159	0	0
T12	45400	609	0	0
T13	306233	5752	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	562678	0	0
T1	110484	143	0	0
T2	8164	152	0	0
T3	270090	12	0	0
T7	192604	381	0	0
T8	436131	97	0	0
T9	2499	26	0	0
T10	1959	10	0	0
T11	530493	599	0	0
T12	45400	1155	0	0
T13	306233	4711	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205882	0	0
T1	110484	120	0	0
T2	8164	145	0	0
T3	270090	12	0	0
T7	192604	328	0	0
T8	436131	10	0	0
T9	2499	25	0	0
T10	1959	10	0	0
T11	530493	15	0	0
T12	45400	881	0	0
T13	306233	1437	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	204316	0	0
GntImpliesValid_A	393792490	204316	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	204316	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2775750	0	0
ReadyAndValidImplyGrant_A	393792490	204316	0	0
ReqAndReadyImplyGrant_A	393792490	204316	0	0
ReqImpliesValid_A	393792490	528580	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	204316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2775750	0	0
T1	110484	464	0	0
T2	8164	110	0	0
T3	270090	74	0	0
T7	192604	2800	0	0
T8	436131	3813	0	0
T9	2499	19	0	0
T10	1959	12	0	0
T11	530493	4941	0	0
T12	45400	502	0	0
T13	306233	6096	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	528580	0	0
T1	110484	117	0	0
T2	8164	129	0	0
T3	270090	16	0	0
T7	192604	415	0	0
T8	436131	314	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	542	0	0
T13	306233	8288	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	204316	0	0
T1	110484	110	0	0
T2	8164	119	0	0
T3	270090	16	0	0
T7	192604	349	0	0
T8	436131	13	0	0
T9	2499	18	0	0
T10	1959	11	0	0
T11	530493	18	0	0
T12	45400	521	0	0
T13	306233	1371	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	212828	0	0
GntImpliesValid_A	393792490	212828	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	212828	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2839310	0	0
ReadyAndValidImplyGrant_A	393792490	212828	0	0
ReqAndReadyImplyGrant_A	393792490	212828	0	0
ReqImpliesValid_A	393792490	568334	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	212828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2839310	0	0
T1	110484	509	0	0
T2	8164	128	0	0
T3	270090	50	0	0
T7	192604	2396	0	0
T8	436131	6459	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	3450	0	0
T12	45400	473	0	0
T13	306233	6546	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	568334	0	0
T1	110484	160	0	0
T2	8164	145	0	0
T3	270090	18	0	0
T7	192604	365	0	0
T8	436131	461	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	489	0	0
T13	306233	3359	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	212828	0	0
T1	110484	126	0	0
T2	8164	136	0	0
T3	270090	13	0	0
T7	192604	314	0	0
T8	436131	20	0	0
T9	2499	12	0	0
T10	1959	8	0	0
T11	530493	11	0	0
T12	45400	480	0	0
T13	306233	1043	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	209237	0	0
GntImpliesValid_A	393792490	209237	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	209237	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2782195	0	0
ReadyAndValidImplyGrant_A	393792490	209237	0	0
ReqAndReadyImplyGrant_A	393792490	209237	0	0
ReqImpliesValid_A	393792490	517000	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	209237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2782195	0	0
T1	110484	509	0	0
T2	8164	143	0	0
T3	270090	56	0	0
T7	192604	5941	0	0
T8	436131	3499	0	0
T9	2499	17	0	0
T10	1959	11	0	0
T11	530493	3373	0	0
T12	45400	450	0	0
T13	306233	6062	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	517000	0	0
T1	110484	146	0	0
T2	8164	164	0	0
T3	270090	13	0	0
T7	192604	2477	0	0
T8	436131	11	0	0
T9	2499	18	0	0
T10	1959	10	0	0
T11	530493	20	0	0
T12	45400	464	0	0
T13	306233	2766	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209237	0	0
T1	110484	120	0	0
T2	8164	153	0	0
T3	270090	13	0	0
T7	192604	876	0	0
T8	436131	11	0	0
T9	2499	17	0	0
T10	1959	10	0	0
T11	530493	10	0	0
T12	45400	456	0	0
T13	306233	939	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	216256	0	0
GntImpliesValid_A	393792490	216256	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	216256	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2753113	0	0
ReadyAndValidImplyGrant_A	393792490	216256	0	0
ReqAndReadyImplyGrant_A	393792490	216256	0	0
ReqImpliesValid_A	393792490	583403	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	216256	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2753113	0	0
T1	110484	559	0	0
T2	8164	130	0	0
T3	270090	27	0	0
T7	192604	2136	0	0
T8	436131	5267	0	0
T9	2499	7	0	0
T10	1959	9	0	0
T11	530493	4408	0	0
T12	45400	472	0	0
T13	306233	5411	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	583403	0	0
T1	110484	165	0	0
T2	8164	155	0	0
T3	270090	5	0	0
T7	192604	341	0	0
T8	436131	223	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	486	0	0
T13	306233	2099	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	216256	0	0
T1	110484	140	0	0
T2	8164	142	0	0
T3	270090	5	0	0
T7	192604	283	0	0
T8	436131	20	0	0
T9	2499	6	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	478	0	0
T13	306233	963	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	205664	0	0
GntImpliesValid_A	393792490	205664	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	205664	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2821500	0	0
ReadyAndValidImplyGrant_A	393792490	205664	0	0
ReqAndReadyImplyGrant_A	393792490	205664	0	0
ReqImpliesValid_A	393792490	533514	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	205664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2821500	0	0
T1	110484	421	0	0
T2	8164	137	0	0
T3	270090	32	0	0
T7	192604	2091	0	0
T8	436131	6578	0	0
T9	2499	17	0	0
T10	1959	9	0	0
T11	530493	5031	0	0
T12	45400	455	0	0
T13	306233	3988	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	533514	0	0
T1	110484	132	0	0
T2	8164	150	0	0
T3	270090	6	0	0
T7	192604	356	0	0
T8	436131	266	0	0
T9	2499	18	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	471	0	0
T13	306233	694	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	205664	0	0
T1	110484	110	0	0
T2	8164	143	0	0
T3	270090	6	0	0
T7	192604	287	0	0
T8	436131	17	0	0
T9	2499	17	0	0
T10	1959	8	0	0
T11	530493	12	0	0
T12	45400	462	0	0
T13	306233	504	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	210018	0	0
GntImpliesValid_A	393792490	210018	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	210018	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2803222	0	0
ReadyAndValidImplyGrant_A	393792490	210018	0	0
ReqAndReadyImplyGrant_A	393792490	210018	0	0
ReqImpliesValid_A	393792490	562942	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	210018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2803222	0	0
T1	110484	472	0	0
T2	8164	127	0	0
T3	270090	41	0	0
T7	192604	2295	0	0
T8	436131	5174	0	0
T9	2499	12	0	0
T10	1959	13	0	0
T11	530493	3604	0	0
T12	45400	452	0	0
T13	306233	3814	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	562942	0	0
T1	110484	121	0	0
T2	8164	144	0	0
T3	270090	10	0	0
T7	192604	339	0	0
T8	436131	16	0	0
T9	2499	13	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	480	0	0
T13	306233	605	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	210018	0	0
T1	110484	119	0	0
T2	8164	135	0	0
T3	270090	10	0	0
T7	192604	304	0	0
T8	436131	16	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	9	0	0
T12	45400	465	0	0
T13	306233	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	206031	0	0
GntImpliesValid_A	393792490	206031	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	206031	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2775834	0	0
ReadyAndValidImplyGrant_A	393792490	206031	0	0
ReqAndReadyImplyGrant_A	393792490	206031	0	0
ReqImpliesValid_A	393792490	514314	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	206031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2775834	0	0
T1	110484	454	0	0
T2	8164	137	0	0
T3	270090	40	0	0
T7	192604	2669	0	0
T8	436131	3204	0	0
T9	2499	10	0	0
T10	1959	7	0	0
T11	530493	5115	0	0
T12	45400	467	0	0
T13	306233	5091	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	514314	0	0
T1	110484	158	0	0
T2	8164	166	0	0
T3	270090	14	0	0
T7	192604	444	0	0
T8	436131	436	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	497	0	0
T13	306233	2273	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	206031	0	0
T1	110484	120	0	0
T2	8164	151	0	0
T3	270090	13	0	0
T7	192604	345	0	0
T8	436131	13	0	0
T9	2499	9	0	0
T10	1959	6	0	0
T11	530493	15	0	0
T12	45400	481	0	0
T13	306233	987	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	215322	0	0
GntImpliesValid_A	393792490	215322	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	215322	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2775122	0	0
ReadyAndValidImplyGrant_A	393792490	215322	0	0
ReqAndReadyImplyGrant_A	393792490	215322	0	0
ReqImpliesValid_A	393792490	527824	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	215322	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2775122	0	0
T1	110484	470	0	0
T2	8164	137	0	0
T3	270090	51	0	0
T7	192604	4622	0	0
T8	436131	4997	0	0
T9	2499	12	0	0
T10	1959	12	0	0
T11	530493	3959	0	0
T12	45400	575	0	0
T13	306233	3786	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	527824	0	0
T1	110484	113	0	0
T2	8164	156	0	0
T3	270090	9	0	0
T7	192604	1522	0	0
T8	436131	854	0	0
T9	2499	13	0	0
T10	1959	11	0	0
T11	530493	239	0	0
T12	45400	615	0	0
T13	306233	585	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	215322	0	0
T1	110484	103	0	0
T2	8164	146	0	0
T3	270090	9	0	0
T7	192604	742	0	0
T8	436131	19	0	0
T9	2499	12	0	0
T10	1959	11	0	0
T11	530493	16	0	0
T12	45400	594	0	0
T13	306233	509	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	214570	0	0
GntImpliesValid_A	393792490	214570	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	214570	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2777961	0	0
ReadyAndValidImplyGrant_A	393792490	214570	0	0
ReqAndReadyImplyGrant_A	393792490	214570	0	0
ReqImpliesValid_A	393792490	602373	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	214570	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2777961	0	0
T1	110484	475	0	0
T2	8164	145	0	0
T3	270090	59	0	0
T7	192604	2369	0	0
T8	436131	5317	0	0
T9	2499	14	0	0
T10	1959	12	0	0
T11	530493	4533	0	0
T12	45400	467	0	0
T13	306233	3846	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	602373	0	0
T1	110484	137	0	0
T2	8164	156	0	0
T3	270090	14	0	0
T7	192604	326	0	0
T8	436131	16	0	0
T9	2499	17	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	489	0	0
T13	306233	640	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	214570	0	0
T1	110484	110	0	0
T2	8164	150	0	0
T3	270090	14	0	0
T7	192604	305	0	0
T8	436131	16	0	0
T9	2499	15	0	0
T10	1959	11	0	0
T11	530493	12	0	0
T12	45400	477	0	0
T13	306233	518	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	201438	0	0
GntImpliesValid_A	393792490	201438	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	201438	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2731489	0	0
ReadyAndValidImplyGrant_A	393792490	201438	0	0
ReqAndReadyImplyGrant_A	393792490	201438	0	0
ReqImpliesValid_A	393792490	534695	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	201438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2731489	0	0
T1	110484	550	0	0
T2	8164	168	0	0
T3	270090	49	0	0
T7	192604	2471	0	0
T8	436131	7179	0	0
T9	2499	11	0	0
T10	1959	10	0	0
T11	530493	5299	0	0
T12	45400	499	0	0
T13	306233	8652	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	534695	0	0
T1	110484	139	0	0
T2	8164	185	0	0
T3	270090	10	0	0
T7	192604	342	0	0
T8	436131	481	0	0
T9	2499	10	0	0
T10	1959	11	0	0
T11	530493	401	0	0
T12	45400	527	0	0
T13	306233	6607	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	201438	0	0
T1	110484	121	0	0
T2	8164	176	0	0
T3	270090	10	0	0
T7	192604	321	0	0
T8	436131	18	0	0
T9	2499	10	0	0
T10	1959	10	0	0
T11	530493	24	0	0
T12	45400	512	0	0
T13	306233	1566	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	219327	0	0
GntImpliesValid_A	393792490	219327	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	219327	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2822031	0	0
ReadyAndValidImplyGrant_A	393792490	219327	0	0
ReqAndReadyImplyGrant_A	393792490	219327	0	0
ReqImpliesValid_A	393792490	630614	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	219327	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2822031	0	0
T1	110484	481	0	0
T2	8164	148	0	0
T3	270090	24	0	0
T7	192604	2551	0	0
T8	436131	4432	0	0
T9	2499	11	0	0
T10	1959	9	0	0
T11	530493	4070	0	0
T12	45400	823	0	0
T13	306233	3936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	630614	0	0
T1	110484	146	0	0
T2	8164	171	0	0
T3	270090	8	0	0
T7	192604	394	0	0
T8	436131	364	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	654	0	0
T12	45400	963	0	0
T13	306233	593	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	219327	0	0
T1	110484	114	0	0
T2	8164	159	0	0
T3	270090	8	0	0
T7	192604	334	0	0
T8	436131	19	0	0
T9	2499	10	0	0
T10	1959	8	0	0
T11	530493	15	0	0
T12	45400	892	0	0
T13	306233	497	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	200147	0	0
GntImpliesValid_A	393792490	200147	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	200147	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2744799	0	0
ReadyAndValidImplyGrant_A	393792490	200147	0	0
ReqAndReadyImplyGrant_A	393792490	200147	0	0
ReqImpliesValid_A	393792490	521755	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	200147	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2744799	0	0
T1	110484	574	0	0
T2	8164	144	0	0
T3	270090	36	0	0
T7	192604	2385	0	0
T8	436131	3384	0	0
T9	2499	15	0	0
T10	1959	9	0	0
T11	530493	4899	0	0
T12	45400	474	0	0
T13	306233	9535	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	521755	0	0
T1	110484	177	0	0
T2	8164	173	0	0
T3	270090	12	0	0
T7	192604	360	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	506	0	0
T13	306233	5831	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	200147	0	0
T1	110484	133	0	0
T2	8164	158	0	0
T3	270090	7	0	0
T7	192604	315	0	0
T8	436131	12	0	0
T9	2499	14	0	0
T10	1959	8	0	0
T11	530493	17	0	0
T12	45400	489	0	0
T13	306233	1532	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	209376	0	0
GntImpliesValid_A	393792490	209376	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	209376	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	2757830	0	0
ReadyAndValidImplyGrant_A	393792490	209376	0	0
ReqAndReadyImplyGrant_A	393792490	209376	0	0
ReqImpliesValid_A	393792490	553921	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	0	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	209376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2757830	0	0
T1	110484	476	0	0
T2	8164	150	0	0
T3	270090	52	0	0
T7	192604	2240	0	0
T8	436131	5801	0	0
T9	2499	14	0	0
T10	1959	10	0	0
T11	530493	3462	0	0
T12	45400	485	0	0
T13	306233	6531	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	553921	0	0
T1	110484	131	0	0
T2	8164	161	0	0
T3	270090	10	0	0
T7	192604	364	0	0
T8	436131	39	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	511	0	0
T13	306233	2472	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	209376	0	0
T1	110484	109	0	0
T2	8164	155	0	0
T3	270090	10	0	0
T7	192604	327	0	0
T8	436131	18	0	0
T9	2499	13	0	0
T10	1959	9	0	0
T11	530493	9	0	0
T12	45400	497	0	0
T13	306233	936	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	838997	0	0
GntImpliesValid_A	393792490	838997	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	838997	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	10623865	0	0
ReadyAndValidImplyGrant_A	393792490	838997	0	0
ReqAndReadyImplyGrant_A	393792490	838997	0	0
ReqImpliesValid_A	393792490	2185586	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	19135	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	838997	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	10623865	0	0
T1	110484	1581	0	0
T2	8164	1	0	0
T3	270090	183	0	0
T7	192604	10783	0	0
T8	436131	12680	0	0
T9	2499	1	0	0
T10	1959	1	0	0
T11	530493	20369	0	0
T12	45400	2	0	0
T13	306233	18409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	2185586	0	0
T1	110484	678	0	0
T2	8164	602	0	0
T3	270090	84	0	0
T7	192604	2376	0	0
T8	436131	378	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	1225	0	0
T12	45400	2784	0	0
T13	306233	4346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	19135	0	900
T2	8164	9	0	1
T3	270090	0	0	1
T7	192604	0	0	1
T8	436131	0	0	1
T9	2499	0	0	1
T10	1959	0	0	1
T11	530493	0	0	1
T12	45400	122	0	1
T13	306233	1	0	1
T14	333325	1	0	1
T15	0	28	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T21	0	6	0	0
T22	0	54	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	838997	0	0
T1	110484	485	0	0
T2	8164	602	0	0
T3	270090	55	0	0
T7	192604	1642	0	0
T8	436131	46	0	0
T9	2499	59	0	0
T10	1959	53	0	0
T11	530493	61	0	0
T12	45400	2784	0	0
T13	306233	3020	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393792490	393664526	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	393792490	847096	0	0
GntImpliesValid_A	393792490	847096	0	0
GrantKnown_A	393792490	393664526	0	0
IdxKnown_A	393792490	393664526	0	0
IndexIsCorrect_A	393792490	847096	0	0
LockArbDecision_A	393792490	0	0	0
NoReadyValidNoGrant_A	393792490	330143068	0	0
ReadyAndValidImplyGrant_A	393792490	847096	0	0
ReqAndReadyImplyGrant_A	393792490	847096	0	0
ReqImpliesValid_A	393792490	12463082	0	0
ReqStaysHighUntilGranted0_M	393792490	0	0	0
RoundRobin_A	393792490	32248	0	900
ValidKnown_A	393792490	393664526	0	0
gen_data_port_assertion.DataFlow_A	393792490	847096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	330143068	0	0
T1	110484	918168	0	0
T2	8164	1	0	0
T3	270090	224516	0	0
T7	192604	163892	0	0
T8	436131	402509	0	0
T9	2499	1	0	0
T10	1959	1	0	0
T11	530493	512973	0	0
T12	45400	1	0	0
T13	306233	257018	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	12463082	0	0
T1	110484	2159	0	0
T2	8164	585	0	0
T3	270090	225	0	0
T7	192604	12709	0	0
T8	436131	21431	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	16475	0	0
T12	45400	2684	0	0
T13	306233	24146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	32248	0	900
T2	8164	13	0	1
T3	270090	0	0	1
T7	192604	3	0	1
T8	436131	0	0	1
T9	2499	0	0	1
T10	1959	0	0	1
T11	530493	0	0	1
T12	45400	243	0	1
T13	306233	2	0	1
T14	333325	0	0	1
T15	0	29	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	9	0	0
T20	0	2	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	393664526	0	0
T1	110484	110483	0	0
T2	8164	8140	0	0
T3	270090	270042	0	0
T7	192604	192538	0	0
T8	436131	436100	0	0
T9	2499	2443	0	0
T10	1959	1905	0	0
T11	530493	530479	0	0
T12	45400	45298	0	0
T13	306233	306123	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393792490	847096	0	0
T1	110484	483	0	0
T2	8164	585	0	0
T3	270090	45	0	0
T7	192604	1584	0	0
T8	436131	61	0	0
T9	2499	60	0	0
T10	1959	63	0	0
T11	530493	55	0	0
T12	45400	2684	0	0
T13	306233	2980	0	0