Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1514062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241079

1

T1

110

T2

558

T3

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	595793	1			T1	267		T2	1364		T3	313
values[0x0]	563789	1			T1	286		T2	1346		T3	276
values[0x1]	595559	1			T1	276		T2	1459		T3	283

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

584552

1

T1

259

T2

1356

T3

267

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27222	1			T2	65		T3	14		T7	16
valid_sources[0x01]	27048	1			T1	22		T2	56		T3	14
valid_sources[0x02]	26717	1			T1	20		T2	61		T3	9
valid_sources[0x03]	27998	1			T1	16		T2	63		T3	18
valid_sources[0x04]	27802	1			T1	11		T2	68		T3	13
valid_sources[0x05]	27959	1			T1	1		T2	58		T3	15
valid_sources[0x06]	28722	1			T2	73		T3	16		T9	7
valid_sources[0x07]	28329	1			T1	31		T2	54		T3	15
valid_sources[0x08]	28201	1			T1	20		T2	77		T3	10
valid_sources[0x09]	27642	1			T1	15		T2	71		T3	13
valid_sources[0x0a]	27100	1			T1	30		T2	65		T3	13
valid_sources[0x0b]	27294	1			T1	50		T2	80		T3	9
valid_sources[0x0c]	26415	1			T2	61		T3	19		T7	21
valid_sources[0x0d]	27780	1			T2	68		T3	13		T7	5
valid_sources[0x0e]	27666	1			T1	10		T2	69		T3	10
valid_sources[0x0f]	27434	1			T1	12		T2	70		T3	8
valid_sources[0x10]	27691	1			T1	14		T2	76		T3	16
valid_sources[0x11]	26886	1			T1	15		T2	47		T3	12
valid_sources[0x12]	27496	1			T1	14		T2	60		T3	9
valid_sources[0x13]	28458	1			T1	7		T2	60		T3	19
valid_sources[0x14]	27570	1			T1	7		T2	59		T3	22
valid_sources[0x15]	27204	1			T1	3		T2	80		T3	10
valid_sources[0x16]	27745	1			T1	10		T2	60		T3	12
valid_sources[0x17]	26862	1			T1	72		T2	51		T3	12
valid_sources[0x18]	27561	1			T2	75		T3	22		T8	3
valid_sources[0x19]	27290	1			T1	15		T2	71		T3	11
valid_sources[0x1a]	26792	1			T1	19		T2	73		T3	24
valid_sources[0x1b]	26421	1			T2	63		T3	8		T9	9
valid_sources[0x1c]	27990	1			T1	14		T2	56		T3	10
valid_sources[0x1d]	26679	1			T1	17		T2	57		T3	17
valid_sources[0x1e]	28894	1			T1	10		T2	66		T3	4
valid_sources[0x1f]	27262	1			T2	58		T3	21		T7	19
valid_sources[0x20]	26940	1			T2	54		T3	12		T7	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25711

1

T1

13

T2

56

T3

15

values[0x0]

all_enables

biggest_size

190176

1

T1

82

T2

427

T3

87

values[0x1]

all_enables

biggest_size

25192

1

T1

15

T2

75

T3

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1519329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246710

1

T1

103

T2

574

T3

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	605572	1			T1	341		T2	1393		T3	209
values[0x0]	555651	1			T1	273		T2	1349		T3	219
values[0x1]	604816	1			T1	306		T2	1427		T3	246

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1166910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599129

1

T1

284

T2

1402

T3

246

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27253	1			T1	10		T2	57		T3	19
valid_sources[0x01]	27509	1			T1	17		T2	57		T3	9
valid_sources[0x02]	27081	1			T1	7		T2	73		T3	13
valid_sources[0x03]	27806	1			T1	14		T2	66		T3	12
valid_sources[0x04]	27666	1			T1	9		T2	76		T3	3
valid_sources[0x05]	27729	1			T1	7		T2	62		T3	9
valid_sources[0x06]	27915	1			T1	19		T2	56		T3	5
valid_sources[0x07]	27349	1			T1	21		T2	57		T3	8
valid_sources[0x08]	28080	1			T1	14		T2	50		T3	9
valid_sources[0x09]	27358	1			T1	17		T2	53		T3	9
valid_sources[0x0a]	27589	1			T1	18		T2	68		T3	7
valid_sources[0x0b]	28135	1			T1	18		T2	62		T3	10
valid_sources[0x0c]	27715	1			T1	12		T2	62		T3	10
valid_sources[0x0d]	28356	1			T1	10		T2	73		T3	11
valid_sources[0x0e]	27777	1			T1	21		T2	59		T3	14
valid_sources[0x0f]	27159	1			T1	11		T2	63		T3	16
valid_sources[0x10]	27177	1			T1	16		T2	66		T3	9
valid_sources[0x11]	27394	1			T1	14		T2	44		T3	5
valid_sources[0x12]	26668	1			T1	14		T2	57		T3	7
valid_sources[0x13]	27806	1			T1	11		T2	73		T3	6
valid_sources[0x14]	27877	1			T1	13		T2	64		T3	14
valid_sources[0x15]	27818	1			T1	16		T2	63		T3	13
valid_sources[0x16]	28042	1			T1	19		T2	52		T3	5
valid_sources[0x17]	27513	1			T1	10		T2	71		T3	4
valid_sources[0x18]	27353	1			T1	18		T2	82		T3	18
valid_sources[0x19]	27376	1			T1	27		T2	58		T3	7
valid_sources[0x1a]	27405	1			T1	13		T2	95		T3	15
valid_sources[0x1b]	27076	1			T1	9		T2	53		T3	8
valid_sources[0x1c]	27845	1			T1	8		T2	69		T3	13
valid_sources[0x1d]	27829	1			T1	11		T2	87		T3	5
valid_sources[0x1e]	28429	1			T1	9		T2	91		T3	8
valid_sources[0x1f]	27248	1			T1	18		T2	70		T3	10
valid_sources[0x20]	27006	1			T1	18		T2	68		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26291

1

T1

8

T2

53

T3

10

values[0x0]

all_enables

biggest_size

194457

1

T1

84

T2

459

T3

81

values[0x1]

all_enables

biggest_size

25962

1

T1

11

T2

62

T3

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1522883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242733

1

T1

130

T2

579

T3

111

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599914	1			T1	339		T2	1499		T3	279
values[0x0]	567572	1			T1	350		T2	1436		T3	249
values[0x1]	598130	1			T1	351		T2	1483		T3	279

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177155	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

588461

1

T1

320

T2

1398

T3

286

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26977	1			T1	6		T2	76		T3	6
valid_sources[0x01]	27960	1			T1	6		T2	76		T3	10
valid_sources[0x02]	27491	1			T1	10		T2	81		T3	14
valid_sources[0x03]	27915	1			T1	30		T2	60		T9	15
valid_sources[0x04]	27162	1			T1	12		T2	71		T3	6
valid_sources[0x05]	27645	1			T1	21		T2	73		T7	19
valid_sources[0x06]	27990	1			T1	2		T2	68		T3	9
valid_sources[0x07]	28011	1			T1	17		T2	67		T3	9
valid_sources[0x08]	27709	1			T1	1		T2	54		T3	13
valid_sources[0x09]	27462	1			T1	14		T2	65		T3	2
valid_sources[0x0a]	27702	1			T1	13		T2	70		T3	6
valid_sources[0x0b]	28042	1			T1	16		T2	69		T3	14
valid_sources[0x0c]	27366	1			T1	12		T2	72		T3	5
valid_sources[0x0d]	27372	1			T1	15		T2	67		T7	7
valid_sources[0x0e]	28311	1			T1	13		T2	58		T3	12
valid_sources[0x0f]	27195	1			T1	31		T2	69		T3	6
valid_sources[0x10]	27711	1			T1	28		T2	64		T3	12
valid_sources[0x11]	26217	1			T1	11		T2	73		T3	26
valid_sources[0x12]	27300	1			T1	21		T2	67		T3	19
valid_sources[0x13]	27314	1			T1	34		T2	81		T7	38
valid_sources[0x14]	27831	1			T1	15		T2	71		T3	10
valid_sources[0x15]	28207	1			T1	11		T2	68		T3	4
valid_sources[0x16]	27931	1			T1	50		T2	65		T3	7
valid_sources[0x17]	28800	1			T1	5		T2	70		T9	9
valid_sources[0x18]	27711	1			T1	10		T2	63		T9	5
valid_sources[0x19]	27571	1			T1	19		T2	70		T3	18
valid_sources[0x1a]	27736	1			T1	29		T2	63		T3	23
valid_sources[0x1b]	27084	1			T1	21		T2	70		T3	64
valid_sources[0x1c]	28083	1			T1	3		T2	64		T3	16
valid_sources[0x1d]	27467	1			T1	27		T2	74		T9	7
valid_sources[0x1e]	27723	1			T1	32		T2	68		T3	21
valid_sources[0x1f]	28233	1			T1	19		T2	74		T3	21
valid_sources[0x20]	26781	1			T1	13		T2	75		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25838

1

T1

12

T2

54

T3

16

values[0x0]

all_enables

biggest_size

191455

1

T1

105

T2

462

T3

86

values[0x1]

all_enables

biggest_size

25440

1

T1

13

T2

63

T3

9