Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7793633	0	0
GntImpliesValid_A	2147483647	7793633	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7793633	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	495353056	0	0
ReadyAndValidImplyGrant_A	2147483647	7793633	0	0
ReqAndReadyImplyGrant_A	2147483647	7793633	0	0
ReqImpliesValid_A	2147483647	36768806	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42577	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7793633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	600288	598800	0	0
T2	11942592	11942448	0	0
T3	20049888	20049288	0	0
T7	1156008	1154088	0	0
T8	335280	334896	0	0
T9	12320568	12313464	0	0
T10	192240	190560	0	0
T11	6252552	6252432	0	0
T12	553200	552984	0	0
T13	45552	44856	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	600288	598800	0	0
T2	11942592	11942448	0	0
T3	20049888	20049288	0	0
T7	1156008	1154088	0	0
T8	335280	334896	0	0
T9	12320568	12313464	0	0
T10	192240	190560	0	0
T11	6252552	6252432	0	0
T12	553200	552984	0	0
T13	45552	44856	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	600288	598800	0	0
T2	11942592	11942448	0	0
T3	20049888	20049288	0	0
T7	1156008	1154088	0	0
T8	335280	334896	0	0
T9	12320568	12313464	0	0
T10	192240	190560	0	0
T11	6252552	6252432	0	0
T12	553200	552984	0	0
T13	45552	44856	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	495353056	0	0
T1	600288	41342	0	0
T2	11942592	460419	0	0
T3	20049888	1422466	0	0
T7	1156008	62210	0	0
T8	335280	17852	0	0
T9	12320568	710718	0	0
T10	192240	4538	0	0
T11	6252552	253355	0	0
T12	553200	1780	0	0
T13	45552	542	0	0
T14	0	12	0	0
T15	0	516	0	0
T16	0	3167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36768806	0	0
T1	600288	6788	0	0
T2	11942592	30686	0	0
T3	20049888	111849	0	0
T7	1156008	4623	0	0
T8	335280	1972	0	0
T9	12320568	150640	0	0
T10	192240	2237	0	0
T11	6252552	14279	0	0
T12	553200	27230	0	0
T13	45552	449	0	0
T14	0	12728	0	0
T15	0	928	0	0
T16	0	1175	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42577	0	21600
T9	1026714	29	0	2
T10	16020	7	0	2
T11	521046	0	0	2
T12	46100	0	0	2
T13	3796	0	0	2
T14	50584	457	0	2
T15	144002	0	0	2
T16	35162	24	0	2
T17	0	17	0	0
T18	0	1	0	0
T19	0	62	0	0
T20	0	48	0	0
T21	0	1619	0	0
T22	0	26	0	0
T23	0	10	0	0
T24	0	31	0	0
T25	0	9	0	0
T26	40784	0	0	2
T27	41242	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	600288	598800	0	0
T2	11942592	11942448	0	0
T3	20049888	20049288	0	0
T7	1156008	1154088	0	0
T8	335280	334896	0	0
T9	12320568	12313464	0	0
T10	192240	190560	0	0
T11	6252552	6252432	0	0
T12	553200	552984	0	0
T13	45552	44856	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7793633	0	0
T1	600288	2787	0	0
T2	11942592	12752	0	0
T3	20049888	2353	0	0
T7	1156008	2674	0	0
T8	335280	940	0	0
T9	12320568	42637	0	0
T10	192240	2155	0	0
T11	6252552	8598	0	0
T12	553200	12330	0	0
T13	45552	397	0	0
T14	0	3865	0	0
T15	0	874	0	0
T16	0	702	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	875931	0	0
GntImpliesValid_A	452192522	875931	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	875931	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	13265327	0	0
ReadyAndValidImplyGrant_A	452192522	875931	0	0
ReqAndReadyImplyGrant_A	452192522	875931	0	0
ReqImpliesValid_A	452192522	2664393	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	875931	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	13265327	0	0
T1	25012	2197	0	0
T2	497608	4364	0	0
T3	835412	85151	0	0
T7	48167	2009	0	0
T8	13970	676	0	0
T9	513357	30445	0	0
T10	8010	248	0	0
T11	260523	3758	0	0
T12	23050	720	0	0
T13	1898	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	2664393	0	0
T1	25012	599	0	0
T2	497608	1569	0	0
T3	835412	7471	0	0
T7	48167	306	0	0
T8	13970	134	0	0
T9	513357	6677	0	0
T10	8010	253	0	0
T11	260523	1196	0	0
T12	23050	1265	0	0
T13	1898	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	875931	0	0
T1	25012	321	0	0
T2	497608	1088	0	0
T3	835412	234	0	0
T7	48167	278	0	0
T8	13970	93	0	0
T9	513357	4070	0	0
T10	8010	250	0	0
T11	260523	906	0	0
T12	23050	992	0	0
T13	1898	43	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	876455	0	0
GntImpliesValid_A	452192522	876455	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	876455	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	13062878	0	0
ReadyAndValidImplyGrant_A	452192522	876455	0	0
ReqAndReadyImplyGrant_A	452192522	876455	0	0
ReqImpliesValid_A	452192522	2675977	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	876455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	13062878	0	0
T1	25012	2347	0	0
T2	497608	4324	0	0
T3	835412	83073	0	0
T7	48167	2387	0	0
T8	13970	801	0	0
T9	513357	31379	0	0
T10	8010	236	0	0
T11	260523	4005	0	0
T12	23050	712	0	0
T13	1898	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	2675977	0	0
T1	25012	642	0	0
T2	497608	1414	0	0
T3	835412	7645	0	0
T7	48167	322	0	0
T8	13970	136	0	0
T9	513357	8147	0	0
T10	8010	243	0	0
T11	260523	1306	0	0
T12	23050	2647	0	0
T13	1898	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	876455	0	0
T1	25012	323	0	0
T2	497608	1014	0	0
T3	835412	241	0	0
T7	48167	303	0	0
T8	13970	106	0	0
T9	513357	4744	0	0
T10	8010	239	0	0
T11	260523	932	0	0
T12	23050	1679	0	0
T13	1898	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	224182	0	0
GntImpliesValid_A	452192522	224182	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	224182	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3320237	0	0
ReadyAndValidImplyGrant_A	452192522	224182	0	0
ReqAndReadyImplyGrant_A	452192522	224182	0	0
ReqImpliesValid_A	452192522	661296	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	224182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3320237	0	0
T1	25012	757	0	0
T2	497608	3548	0	0
T3	835412	21852	0	0
T7	48167	546	0	0
T8	13970	193	0	0
T9	513357	8309	0	0
T10	8010	71	0	0
T11	260523	947	0	0
T12	23050	1	0	0
T13	1898	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	661296	0	0
T1	25012	135	0	0
T2	497608	2401	0	0
T3	835412	540	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	9475	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224182	0	0
T1	25012	91	0	0
T2	497608	1026	0	0
T3	835412	63	0	0
T7	48167	75	0	0
T8	13970	25	0	0
T9	513357	1774	0	0
T10	8010	70	0	0
T11	260523	220	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	218688	0	0
GntImpliesValid_A	452192522	218688	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	218688	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3451242	0	0
ReadyAndValidImplyGrant_A	452192522	218688	0	0
ReqAndReadyImplyGrant_A	452192522	218688	0	0
ReqImpliesValid_A	452192522	615035	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	218688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3451242	0	0
T1	25012	596	0	0
T2	497608	1	0	0
T3	835412	24250	0	0
T7	48167	584	0	0
T8	13970	138	0	0
T9	513357	5356	0	0
T10	8010	54	0	0
T11	260523	977	0	0
T12	23050	1	0	0
T13	1898	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	615035	0	0
T1	25012	101	0	0
T2	497608	0	0	0
T3	835412	1841	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	799	0	0
T10	8010	53	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	247	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218688	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	65	0	0
T7	48167	71	0	0
T8	13970	27	0	0
T9	513357	667	0	0
T10	8010	53	0	0
T11	260523	242	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	100	0	0
T16	0	236	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	210575	0	0
GntImpliesValid_A	452192522	210575	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	210575	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	6120901	0	0
ReadyAndValidImplyGrant_A	452192522	210575	0	0
ReqAndReadyImplyGrant_A	452192522	210575	0	0
ReqImpliesValid_A	452192522	1373671	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	210575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	6120901	0	0
T1	25012	1409	0	0
T2	497608	0	0	0
T3	835412	11081	0	0
T7	48167	850	0	0
T8	13970	144	0	0
T9	513357	24970	0	0
T10	8010	985	0	0
T11	260523	2311	0	0
T12	23050	0	0	0
T13	1898	46	0	0
T15	0	516	0	0
T16	0	3167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	1373671	0	0
T1	25012	179	0	0
T2	497608	0	0	0
T3	835412	588	0	0
T7	48167	77	0	0
T8	13970	20	0	0
T9	513357	7501	0	0
T10	8010	82	0	0
T11	260523	414	0	0
T12	23050	0	0	0
T13	1898	13	0	0
T15	0	112	0	0
T16	0	674	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	210575	0	0
T1	25012	76	0	0
T2	497608	0	0	0
T3	835412	69	0	0
T7	48167	74	0	0
T8	13970	20	0	0
T9	513357	1263	0	0
T10	8010	58	0	0
T11	260523	249	0	0
T12	23050	0	0	0
T13	1898	9	0	0
T15	0	112	0	0
T16	0	221	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	218100	0	0
GntImpliesValid_A	452192522	218100	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	218100	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	5635570	0	0
ReadyAndValidImplyGrant_A	452192522	218100	0	0
ReqAndReadyImplyGrant_A	452192522	218100	0	0
ReqImpliesValid_A	452192522	1273184	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	218100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	5635570	0	0
T1	25012	1251	0	0
T2	497608	2432	0	0
T3	835412	24514	0	0
T7	48167	1795	0	0
T8	13970	123	0	0
T9	513357	18781	0	0
T10	8010	438	0	0
T11	260523	3217	0	0
T12	23050	0	0	0
T13	1898	83	0	0
T14	0	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	1273184	0	0
T1	25012	146	0	0
T2	497608	1504	0	0
T3	835412	1111	0	0
T7	48167	108	0	0
T8	13970	20	0	0
T9	513357	21836	0	0
T10	8010	75	0	0
T11	260523	524	0	0
T12	23050	0	0	0
T13	1898	28	0	0
T14	0	4361	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	218100	0	0
T1	25012	92	0	0
T2	497608	443	0	0
T3	835412	78	0	0
T7	48167	93	0	0
T8	13970	19	0	0
T9	513357	2191	0	0
T10	8010	73	0	0
T11	260523	272	0	0
T12	23050	0	0	0
T13	1898	12	0	0
T14	0	507	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	207357	0	0
GntImpliesValid_A	452192522	207357	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	207357	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	6061953	0	0
ReadyAndValidImplyGrant_A	452192522	207357	0	0
ReqAndReadyImplyGrant_A	452192522	207357	0	0
ReqImpliesValid_A	452192522	1150654	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	207357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	6061953	0	0
T1	25012	1167	0	0
T2	497608	5790	0	0
T3	835412	16062	0	0
T7	48167	1039	0	0
T8	13970	129	0	0
T9	513357	17124	0	0
T10	8010	1283	0	0
T11	260523	2234	0	0
T12	23050	140	0	0
T13	1898	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	1150654	0	0
T1	25012	150	0	0
T2	497608	2622	0	0
T3	835412	625	0	0
T7	48167	80	0	0
T8	13970	26	0	0
T9	513357	1594	0	0
T10	8010	109	0	0
T11	260523	375	0	0
T12	23050	6877	0	0
T13	1898	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	207357	0	0
T1	25012	71	0	0
T2	497608	492	0	0
T3	835412	62	0	0
T7	48167	72	0	0
T8	13970	26	0	0
T9	513357	709	0	0
T10	8010	70	0	0
T11	260523	251	0	0
T12	23050	1563	0	0
T13	1898	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	213827	0	0
GntImpliesValid_A	452192522	213827	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	213827	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	5697419	0	0
ReadyAndValidImplyGrant_A	452192522	213827	0	0
ReqAndReadyImplyGrant_A	452192522	213827	0	0
ReqImpliesValid_A	452192522	1232716	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	213827	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	5697419	0	0
T1	25012	1407	0	0
T2	497608	0	0	0
T3	835412	9622	0	0
T7	48167	950	0	0
T8	13970	185	0	0
T9	513357	10353	0	0
T10	8010	380	0	0
T11	260523	1750	0	0
T12	23050	8	0	0
T13	1898	46	0	0
T14	0	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	1232716	0	0
T1	25012	310	0	0
T2	497608	0	0	0
T3	835412	481	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	1158	0	0
T10	8010	70	0	0
T11	260523	350	0	0
T12	23050	3365	0	0
T13	1898	19	0	0
T14	0	2602	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	213827	0	0
T1	25012	90	0	0
T2	497608	0	0	0
T3	835412	83	0	0
T7	48167	63	0	0
T8	13970	31	0	0
T9	513357	761	0	0
T10	8010	68	0	0
T11	260523	250	0	0
T12	23050	467	0	0
T13	1898	10	0	0
T14	0	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	203582	0	0
GntImpliesValid_A	452192522	203582	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	203582	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3234420	0	0
ReadyAndValidImplyGrant_A	452192522	203582	0	0
ReqAndReadyImplyGrant_A	452192522	203582	0	0
ReqImpliesValid_A	452192522	563571	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	203582	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3234420	0	0
T1	25012	572	0	0
T2	497608	1	0	0
T3	835412	20921	0	0
T7	48167	498	0	0
T8	13970	229	0	0
T9	513357	5411	0	0
T10	8010	58	0	0
T11	260523	1001	0	0
T12	23050	2	0	0
T13	1898	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	563571	0	0
T1	25012	131	0	0
T2	497608	0	0	0
T3	835412	1492	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	812	0	0
T10	8010	57	0	0
T11	260523	249	0	0
T12	23050	1039	0	0
T13	1898	13	0	0
T15	0	124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	203582	0	0
T1	25012	82	0	0
T2	497608	0	0	0
T3	835412	66	0	0
T7	48167	68	0	0
T8	13970	27	0	0
T9	513357	694	0	0
T10	8010	57	0	0
T11	260523	222	0	0
T12	23050	520	0	0
T13	1898	12	0	0
T15	0	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	211220	0	0
GntImpliesValid_A	452192522	211220	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	211220	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3236666	0	0
ReadyAndValidImplyGrant_A	452192522	211220	0	0
ReqAndReadyImplyGrant_A	452192522	211220	0	0
ReqImpliesValid_A	452192522	585097	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	211220	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3236666	0	0
T1	25012	432	0	0
T2	497608	4708	0	0
T3	835412	25182	0	0
T7	48167	571	0	0
T8	13970	133	0	0
T9	513357	5233	0	0
T10	8010	59	0	0
T11	260523	980	0	0
T12	23050	49	0	0
T13	1898	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	585097	0	0
T1	25012	95	0	0
T2	497608	3342	0	0
T3	835412	1908	0	0
T7	48167	78	0	0
T8	13970	36	0	0
T9	513357	804	0	0
T10	8010	60	0	0
T11	260523	272	0	0
T12	23050	986	0	0
T13	1898	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	211220	0	0
T1	25012	59	0	0
T2	497608	1426	0	0
T3	835412	77	0	0
T7	48167	76	0	0
T8	13970	20	0	0
T9	513357	673	0	0
T10	8010	59	0	0
T11	260523	241	0	0
T12	23050	517	0	0
T13	1898	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	212125	0	0
GntImpliesValid_A	452192522	212125	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	212125	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3324745	0	0
ReadyAndValidImplyGrant_A	452192522	212125	0	0
ReqAndReadyImplyGrant_A	452192522	212125	0	0
ReqImpliesValid_A	452192522	607628	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	212125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3324745	0	0
T1	25012	577	0	0
T2	497608	1	0	0
T3	835412	16599	0	0
T7	48167	678	0	0
T8	13970	245	0	0
T9	513357	6370	0	0
T10	8010	68	0	0
T11	260523	942	0	0
T12	23050	1	0	0
T13	1898	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	607628	0	0
T1	25012	144	0	0
T2	497608	0	0	0
T3	835412	1163	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	3100	0	0
T10	8010	67	0	0
T11	260523	301	0	0
T12	23050	0	0	0
T13	1898	20	0	0
T15	0	110	0	0
T16	0	254	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212125	0	0
T1	25012	92	0	0
T2	497608	0	0	0
T3	835412	64	0	0
T7	48167	84	0	0
T8	13970	26	0	0
T9	513357	1243	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	18	0	0
T15	0	103	0	0
T16	0	245	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	212394	0	0
GntImpliesValid_A	452192522	212394	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	212394	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3281491	0	0
ReadyAndValidImplyGrant_A	452192522	212394	0	0
ReqAndReadyImplyGrant_A	452192522	212394	0	0
ReqImpliesValid_A	452192522	562729	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	212394	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3281491	0	0
T1	25012	630	0	0
T2	497608	1	0	0
T3	835412	28151	0	0
T7	48167	577	0	0
T8	13970	182	0	0
T9	513357	11455	0	0
T10	8010	62	0	0
T11	260523	1078	0	0
T12	23050	2	0	0
T13	1898	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	562729	0	0
T1	25012	144	0	0
T2	497608	0	0	0
T3	835412	3449	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	5070	0	0
T10	8010	61	0	0
T11	260523	293	0	0
T12	23050	949	0	0
T13	1898	8	0	0
T15	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	212394	0	0
T1	25012	80	0	0
T2	497608	0	0	0
T3	835412	81	0	0
T7	48167	77	0	0
T8	13970	29	0	0
T9	513357	2180	0	0
T10	8010	61	0	0
T11	260523	235	0	0
T12	23050	475	0	0
T13	1898	8	0	0
T15	0	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	198783	0	0
GntImpliesValid_A	452192522	198783	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	198783	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3193136	0	0
ReadyAndValidImplyGrant_A	452192522	198783	0	0
ReqAndReadyImplyGrant_A	452192522	198783	0	0
ReqImpliesValid_A	452192522	535110	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	198783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3193136	0	0
T1	25012	446	0	0
T2	497608	3802	0	0
T3	835412	24301	0	0
T7	48167	620	0	0
T8	13970	168	0	0
T9	513357	5423	0	0
T10	8010	44	0	0
T11	260523	1079	0	0
T12	23050	64	0	0
T13	1898	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	535110	0	0
T1	25012	53	0	0
T2	497608	2410	0	0
T3	835412	57	0	0
T7	48167	85	0	0
T8	13970	23	0	0
T9	513357	869	0	0
T10	8010	43	0	0
T11	260523	362	0	0
T12	23050	965	0	0
T13	1898	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	198783	0	0
T1	25012	53	0	0
T2	497608	1085	0	0
T3	835412	57	0	0
T7	48167	81	0	0
T8	13970	23	0	0
T9	513357	731	0	0
T10	8010	43	0	0
T11	260523	265	0	0
T12	23050	514	0	0
T13	1898	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	217505	0	0
GntImpliesValid_A	452192522	217505	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	217505	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3314385	0	0
ReadyAndValidImplyGrant_A	452192522	217505	0	0
ReqAndReadyImplyGrant_A	452192522	217505	0	0
ReqImpliesValid_A	452192522	608518	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	217505	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3314385	0	0
T1	25012	786	0	0
T2	497608	1572	0	0
T3	835412	21029	0	0
T7	48167	471	0	0
T8	13970	263	0	0
T9	513357	6905	0	0
T10	8010	48	0	0
T11	260523	1073	0	0
T12	23050	2	0	0
T13	1898	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	608518	0	0
T1	25012	163	0	0
T2	497608	1093	0	0
T3	835412	1119	0	0
T7	48167	75	0	0
T8	13970	42	0	0
T9	513357	5712	0	0
T10	8010	49	0	0
T11	260523	282	0	0
T12	23050	919	0	0
T13	1898	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	217505	0	0
T1	25012	106	0	0
T2	497608	479	0	0
T3	835412	71	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	1260	0	0
T10	8010	48	0	0
T11	260523	245	0	0
T12	23050	460	0	0
T13	1898	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	221757	0	0
GntImpliesValid_A	452192522	221757	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	221757	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3284795	0	0
ReadyAndValidImplyGrant_A	452192522	221757	0	0
ReqAndReadyImplyGrant_A	452192522	221757	0	0
ReqImpliesValid_A	452192522	579451	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	221757	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3284795	0	0
T1	25012	476	0	0
T2	497608	3358	0	0
T3	835412	28205	0	0
T7	48167	587	0	0
T8	13970	235	0	0
T9	513357	8764	0	0
T10	8010	66	0	0
T11	260523	976	0	0
T12	23050	19	0	0
T13	1898	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	579451	0	0
T1	25012	87	0	0
T2	497608	2216	0	0
T3	835412	1479	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	2728	0	0
T10	8010	65	0	0
T11	260523	324	0	0
T12	23050	2042	0	0
T13	1898	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221757	0	0
T1	25012	64	0	0
T2	497608	998	0	0
T3	835412	80	0	0
T7	48167	73	0	0
T8	13970	28	0	0
T9	513357	1231	0	0
T10	8010	65	0	0
T11	260523	240	0	0
T12	23050	1030	0	0
T13	1898	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	215448	0	0
GntImpliesValid_A	452192522	215448	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	215448	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3227728	0	0
ReadyAndValidImplyGrant_A	452192522	215448	0	0
ReqAndReadyImplyGrant_A	452192522	215448	0	0
ReqImpliesValid_A	452192522	574531	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	215448	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3227728	0	0
T1	25012	593	0	0
T2	497608	1770	0	0
T3	835412	25670	0	0
T7	48167	456	0	0
T8	13970	175	0	0
T9	513357	8363	0	0
T10	8010	68	0	0
T11	260523	922	0	0
T12	23050	1	0	0
T13	1898	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	574531	0	0
T1	25012	93	0	0
T2	497608	1175	0	0
T3	835412	1424	0	0
T7	48167	85	0	0
T8	13970	27	0	0
T9	513357	1998	0	0
T10	8010	67	0	0
T11	260523	255	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	1001	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	215448	0	0
T1	25012	76	0	0
T2	497608	522	0	0
T3	835412	71	0	0
T7	48167	72	0	0
T8	13970	27	0	0
T9	513357	1242	0	0
T10	8010	67	0	0
T11	260523	226	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T14	0	501	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	245649	0	0
GntImpliesValid_A	452192522	245649	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	245649	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3427702	0	0
ReadyAndValidImplyGrant_A	452192522	245649	0	0
ReqAndReadyImplyGrant_A	452192522	245649	0	0
ReqImpliesValid_A	452192522	677110	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	245649	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3427702	0	0
T1	25012	586	0	0
T2	497608	1898	0	0
T3	835412	23692	0	0
T7	48167	576	0	0
T8	13970	361	0	0
T9	513357	11646	0	0
T10	8010	63	0	0
T11	260523	979	0	0
T12	23050	2	0	0
T13	1898	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	677110	0	0
T1	25012	87	0	0
T2	497608	1288	0	0
T3	835412	1347	0	0
T7	48167	79	0	0
T8	13970	45	0	0
T9	513357	4708	0	0
T10	8010	64	0	0
T11	260523	285	0	0
T12	23050	1115	0	0
T13	1898	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	245649	0	0
T1	25012	74	0	0
T2	497608	538	0	0
T3	835412	71	0	0
T7	48167	79	0	0
T8	13970	41	0	0
T9	513357	1738	0	0
T10	8010	63	0	0
T11	260523	231	0	0
T12	23050	558	0	0
T13	1898	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	224578	0	0
GntImpliesValid_A	452192522	224578	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	224578	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3318669	0	0
ReadyAndValidImplyGrant_A	452192522	224578	0	0
ReqAndReadyImplyGrant_A	452192522	224578	0	0
ReqImpliesValid_A	452192522	642279	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	224578	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3318669	0	0
T1	25012	534	0	0
T2	497608	1	0	0
T3	835412	27587	0	0
T7	48167	643	0	0
T8	13970	179	0	0
T9	513357	8640	0	0
T10	8010	63	0	0
T11	260523	1020	0	0
T12	23050	49	0	0
T13	1898	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	642279	0	0
T1	25012	84	0	0
T2	497608	0	0	0
T3	835412	1650	0	0
T7	48167	91	0	0
T8	13970	24	0	0
T9	513357	1972	0	0
T10	8010	66	0	0
T11	260523	290	0	0
T12	23050	2098	0	0
T13	1898	8	0	0
T14	0	955	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	224578	0	0
T1	25012	74	0	0
T2	497608	0	0	0
T3	835412	85	0	0
T7	48167	83	0	0
T8	13970	24	0	0
T9	513357	1259	0	0
T10	8010	64	0	0
T11	260523	240	0	0
T12	23050	1073	0	0
T13	1898	8	0	0
T14	0	500	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	199914	0	0
GntImpliesValid_A	452192522	199914	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	199914	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3256553	0	0
ReadyAndValidImplyGrant_A	452192522	199914	0	0
ReqAndReadyImplyGrant_A	452192522	199914	0	0
ReqImpliesValid_A	452192522	583012	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	199914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3256553	0	0
T1	25012	557	0	0
T2	497608	1806	0	0
T3	835412	27860	0	0
T7	48167	684	0	0
T8	13970	149	0	0
T9	513357	5526	0	0
T10	8010	57	0	0
T11	260523	1054	0	0
T12	23050	1	0	0
T13	1898	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	583012	0	0
T1	25012	81	0	0
T2	497608	1222	0	0
T3	835412	1462	0	0
T7	48167	82	0	0
T8	13970	56	0	0
T9	513357	964	0	0
T10	8010	58	0	0
T11	260523	297	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	199914	0	0
T1	25012	71	0	0
T2	497608	523	0	0
T3	835412	81	0	0
T7	48167	82	0	0
T8	13970	29	0	0
T9	513357	746	0	0
T10	8010	57	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	10	0	0
T15	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	221014	0	0
GntImpliesValid_A	452192522	221014	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	221014	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3320257	0	0
ReadyAndValidImplyGrant_A	452192522	221014	0	0
ReqAndReadyImplyGrant_A	452192522	221014	0	0
ReqImpliesValid_A	452192522	589801	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	221014	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3320257	0	0
T1	25012	503	0	0
T2	497608	1698	0	0
T3	835412	26658	0	0
T7	48167	596	0	0
T8	13970	234	0	0
T9	513357	5473	0	0
T10	8010	64	0	0
T11	260523	991	0	0
T12	23050	1	0	0
T13	1898	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	589801	0	0
T1	25012	108	0	0
T2	497608	1237	0	0
T3	835412	628	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	821	0	0
T10	8010	63	0	0
T11	260523	258	0	0
T12	23050	0	0	0
T13	1898	20	0	0
T14	0	2656	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221014	0	0
T1	25012	72	0	0
T2	497608	533	0	0
T3	835412	69	0	0
T7	48167	75	0	0
T8	13970	31	0	0
T9	513357	714	0	0
T10	8010	63	0	0
T11	260523	218	0	0
T12	23050	0	0	0
T13	1898	19	0	0
T14	0	1332	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	214761	0	0
GntImpliesValid_A	452192522	214761	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	214761	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3295380	0	0
ReadyAndValidImplyGrant_A	452192522	214761	0	0
ReqAndReadyImplyGrant_A	452192522	214761	0	0
ReqImpliesValid_A	452192522	602624	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	214761	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3295380	0	0
T1	25012	519	0	0
T2	497608	1	0	0
T3	835412	27158	0	0
T7	48167	445	0	0
T8	13970	126	0	0
T9	513357	5360	0	0
T10	8010	62	0	0
T11	260523	1250	0	0
T12	23050	1	0	0
T13	1898	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	602624	0	0
T1	25012	77	0	0
T2	497608	0	0	0
T3	835412	2334	0	0
T7	48167	77	0	0
T8	13970	19	0	0
T9	513357	812	0	0
T10	8010	63	0	0
T11	260523	325	0	0
T12	23050	0	0	0
T13	1898	17	0	0
T14	0	1153	0	0
T15	0	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	214761	0	0
T1	25012	68	0	0
T2	497608	0	0	0
T3	835412	82	0	0
T7	48167	68	0	0
T8	13970	19	0	0
T9	513357	704	0	0
T10	8010	62	0	0
T11	260523	285	0	0
T12	23050	0	0	0
T13	1898	15	0	0
T14	0	577	0	0
T15	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	221721	0	0
GntImpliesValid_A	452192522	221721	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	221721	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	3342622	0	0
ReadyAndValidImplyGrant_A	452192522	221721	0	0
ReqAndReadyImplyGrant_A	452192522	221721	0	0
ReqImpliesValid_A	452192522	625304	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	0	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	221721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	3342622	0	0
T1	25012	575	0	0
T2	497608	1710	0	0
T3	835412	17378	0	0
T7	48167	714	0	0
T8	13970	204	0	0
T9	513357	8911	0	0
T10	8010	59	0	0
T11	260523	938	0	0
T12	23050	2	0	0
T13	1898	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	625304	0	0
T1	25012	112	0	0
T2	497608	1247	0	0
T3	835412	548	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	6962	0	0
T10	8010	60	0	0
T11	260523	293	0	0
T12	23050	963	0	0
T13	1898	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	221721	0	0
T1	25012	71	0	0
T2	497608	519	0	0
T3	835412	57	0	0
T7	48167	79	0	0
T8	13970	25	0	0
T9	513357	1617	0	0
T10	8010	59	0	0
T11	260523	243	0	0
T12	23050	482	0	0
T13	1898	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	864403	0	0
GntImpliesValid_A	452192522	864403	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	864403	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	12324001	0	0
ReadyAndValidImplyGrant_A	452192522	864403	0	0
ReqAndReadyImplyGrant_A	452192522	864403	0	0
ReqImpliesValid_A	452192522	2424543	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	18406	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	864403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	12324001	0	0
T1	25012	1928	0	0
T2	497608	3312	0	0
T3	835412	75560	0	0
T7	48167	2047	0	0
T8	13970	752	0	0
T9	513357	31683	0	0
T10	8010	1	0	0
T11	260523	3116	0	0
T12	23050	1	0	0
T13	1898	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	2424543	0	0
T1	25012	514	0	0
T2	497608	1274	0	0
T3	835412	6497	0	0
T7	48167	319	0	0
T8	13970	172	0	0
T9	513357	13379	0	0
T10	8010	210	0	0
T11	260523	1193	0	0
T12	23050	956	0	0
T13	1898	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	18406	0	900
T9	513357	13	0	1
T10	8010	2	0	1
T11	260523	0	0	1
T12	23050	0	0	1
T13	1898	0	0	1
T14	25292	0	0	1
T15	72001	0	0	1
T16	17581	11	0	1
T17	0	6	0	0
T20	0	15	0	0
T21	0	1541	0	0
T22	0	12	0	0
T23	0	10	0	0
T24	0	31	0	0
T25	0	9	0	0
T26	20392	0	0	1
T27	20621	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	864403	0	0
T1	25012	304	0	0
T2	497608	1014	0	0
T3	835412	252	0	0
T7	48167	302	0	0
T8	13970	108	0	0
T9	513357	5329	0	0
T10	8010	210	0	0
T11	260523	949	0	0
T12	23050	956	0	0
T13	1898	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	452192522	452072681	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	452192522	863664	0	0
GntImpliesValid_A	452192522	863664	0	0
GrantKnown_A	452192522	452072681	0	0
IdxKnown_A	452192522	452072681	0	0
IndexIsCorrect_A	452192522	863664	0	0
LockArbDecision_A	452192522	0	0	0
NoReadyValidNoGrant_A	452192522	380354979	0	0
ReadyAndValidImplyGrant_A	452192522	863664	0	0
ReqAndReadyImplyGrant_A	452192522	863664	0	0
ReqImpliesValid_A	452192522	14360572	0	0
ReqStaysHighUntilGranted0_M	452192522	0	0	0
RoundRobin_A	452192522	24171	0	900
ValidKnown_A	452192522	452072681	0	0
gen_data_port_assertion.DataFlow_A	452192522	863664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	380354979	0	0
T1	25012	20497	0	0
T2	497608	414321	0	0
T3	835412	730910	0	0
T7	48167	41887	0	0
T8	13970	11828	0	0
T9	513357	428838	0	0
T10	8010	1	0	0
T11	260523	216757	0	0
T12	23050	1	0	0
T13	1898	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	14360572	0	0
T1	25012	2553	0	0
T2	497608	4672	0	0
T3	835412	64990	0	0
T7	48167	2094	0	0
T8	13970	943	0	0
T9	513357	42742	0	0
T10	8010	229	0	0
T11	260523	4299	0	0
T12	23050	1044	0	0
T13	1898	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	24171	0	900
T9	513357	16	0	1
T10	8010	5	0	1
T11	260523	0	0	1
T12	23050	0	0	1
T13	1898	0	0	1
T14	25292	457	0	1
T15	72001	0	0	1
T16	17581	13	0	1
T17	0	11	0	0
T18	0	1	0	0
T19	0	62	0	0
T20	0	33	0	0
T21	0	78	0	0
T22	0	14	0	0
T26	20392	0	0	1
T27	20621	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	452072681	0	0
T1	25012	24950	0	0
T2	497608	497602	0	0
T3	835412	835387	0	0
T7	48167	48087	0	0
T8	13970	13954	0	0
T9	513357	513061	0	0
T10	8010	7940	0	0
T11	260523	260518	0	0
T12	23050	23041	0	0
T13	1898	1869	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452192522	863664	0	0
T1	25012	297	0	0
T2	497608	1052	0	0
T3	835412	194	0	0
T7	48167	271	0	0
T8	13970	105	0	0
T9	513357	5097	0	0
T10	8010	229	0	0
T11	260523	952	0	0
T12	23050	1044	0	0
T13	1898	50	0	0