Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1625823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258154

1

T1

61

T2

266

T3

280

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640147	1			T1	151		T2	694		T3	639
values[0x0]	604833	1			T1	158		T2	703		T3	643
values[0x1]	638997	1			T1	164		T2	732		T3	666

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1256474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

627503

1

T1

164

T2

671

T3

679

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29606	1			T1	8		T2	108		T3	19
valid_sources[0x01]	28923	1			T1	6		T2	13		T3	37
valid_sources[0x02]	29608	1			T1	6		T3	36		T7	61
valid_sources[0x03]	29745	1			T1	5		T2	8		T3	28
valid_sources[0x04]	30823	1			T1	5		T2	3		T3	41
valid_sources[0x05]	30088	1			T1	10		T2	27		T3	28
valid_sources[0x06]	28894	1			T1	5		T3	25		T7	51
valid_sources[0x07]	29935	1			T1	5		T2	30		T3	23
valid_sources[0x08]	29672	1			T1	8		T2	18		T3	26
valid_sources[0x09]	28943	1			T1	4		T3	15		T7	42
valid_sources[0x0a]	29612	1			T1	6		T2	94		T3	37
valid_sources[0x0b]	30357	1			T1	6		T3	20		T7	50
valid_sources[0x0c]	29664	1			T1	7		T3	28		T7	34
valid_sources[0x0d]	29565	1			T1	13		T2	45		T3	22
valid_sources[0x0e]	30172	1			T1	5		T2	47		T3	38
valid_sources[0x0f]	28766	1			T1	11		T2	42		T3	24
valid_sources[0x10]	28624	1			T1	6		T3	23		T7	50
valid_sources[0x11]	28820	1			T1	8		T2	21		T3	36
valid_sources[0x12]	28936	1			T1	6		T3	45		T7	57
valid_sources[0x13]	29060	1			T1	5		T2	139		T3	43
valid_sources[0x14]	28531	1			T1	11		T2	12		T3	37
valid_sources[0x15]	29240	1			T1	5		T2	80		T3	39
valid_sources[0x16]	29304	1			T1	4		T2	23		T3	23
valid_sources[0x17]	28993	1			T1	10		T3	33		T7	35
valid_sources[0x18]	30661	1			T1	10		T2	44		T3	33
valid_sources[0x19]	29625	1			T1	3		T2	19		T3	32
valid_sources[0x1a]	29509	1			T1	10		T3	35		T7	39
valid_sources[0x1b]	29868	1			T1	5		T3	38		T7	55
valid_sources[0x1c]	29298	1			T1	9		T2	57		T3	26
valid_sources[0x1d]	29163	1			T1	13		T2	82		T3	38
valid_sources[0x1e]	29299	1			T1	12		T2	24		T3	18
valid_sources[0x1f]	29448	1			T1	4		T2	13		T3	29
valid_sources[0x20]	29288	1			T1	9		T3	29		T7	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27438

1

T1

6

T2

27

T3

33

values[0x0]

all_enables

biggest_size

203744

1

T1

49

T2

214

T3

216

values[0x1]

all_enables

biggest_size

26972

1

T1

6

T2

25

T3

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1636817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266265

1

T1

67

T2

366

T3

283

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	651015	1			T1	142		T2	781		T3	719
values[0x0]	600727	1			T1	148		T2	769		T3	677
values[0x1]	651340	1			T1	170		T2	780		T3	733

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

647119

1

T1

162

T2

805

T3

722

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30225	1			T1	4		T3	25		T7	43
valid_sources[0x01]	29884	1			T1	5		T2	43		T3	22
valid_sources[0x02]	30251	1			T1	9		T2	69		T3	36
valid_sources[0x03]	30002	1			T1	12		T2	89		T3	32
valid_sources[0x04]	30095	1			T1	5		T2	82		T3	34
valid_sources[0x05]	29891	1			T1	2		T2	20		T3	35
valid_sources[0x06]	29525	1			T1	8		T2	14		T3	33
valid_sources[0x07]	30439	1			T1	9		T2	11		T3	42
valid_sources[0x08]	29225	1			T1	7		T2	23		T3	37
valid_sources[0x09]	29675	1			T1	7		T2	34		T3	31
valid_sources[0x0a]	29554	1			T1	3		T2	17		T3	32
valid_sources[0x0b]	29711	1			T1	2		T2	23		T3	28
valid_sources[0x0c]	29560	1			T1	9		T2	22		T3	27
valid_sources[0x0d]	30136	1			T1	6		T2	44		T3	32
valid_sources[0x0e]	29807	1			T1	11		T2	10		T3	33
valid_sources[0x0f]	29003	1			T1	5		T2	81		T3	36
valid_sources[0x10]	29011	1			T1	10		T2	23		T3	33
valid_sources[0x11]	29550	1			T1	1		T2	21		T3	26
valid_sources[0x12]	30091	1			T1	9		T2	95		T3	25
valid_sources[0x13]	29375	1			T1	5		T2	63		T3	42
valid_sources[0x14]	29959	1			T1	2		T2	79		T3	31
valid_sources[0x15]	29958	1			T1	9		T2	54		T3	39
valid_sources[0x16]	30008	1			T1	13		T2	25		T3	41
valid_sources[0x17]	29196	1			T1	7		T2	43		T3	34
valid_sources[0x18]	30884	1			T1	4		T2	33		T3	27
valid_sources[0x19]	29708	1			T1	7		T2	18		T3	36
valid_sources[0x1a]	29389	1			T1	10		T2	54		T3	36
valid_sources[0x1b]	29947	1			T1	8		T2	97		T3	29
valid_sources[0x1c]	29371	1			T1	4		T2	37		T3	33
valid_sources[0x1d]	29562	1			T1	10		T2	88		T3	29
valid_sources[0x1e]	29187	1			T1	5		T2	30		T3	43
valid_sources[0x1f]	29995	1			T1	5		T2	28		T3	26
valid_sources[0x20]	29580	1			T1	12		T2	15		T3	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27982

1

T1

3

T2

31

T3

30

values[0x0]

all_enables

biggest_size

210466

1

T1

59

T2

293

T3

226

values[0x1]

all_enables

biggest_size

27817

1

T1

5

T2

42

T3

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1637531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262016

1

T1

67

T2

315

T3

270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	645084	1			T1	171		T2	685		T3	647
values[0x0]	610348	1			T1	181		T2	738		T3	619
values[0x1]	644115	1			T1	157		T2	753		T3	648

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1264975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634572

1

T1

149

T2

735

T3

685

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29576	1			T1	11		T2	27		T3	32
valid_sources[0x01]	29360	1			T1	8		T2	29		T3	31
valid_sources[0x02]	29800	1			T1	9		T2	61		T3	25
valid_sources[0x03]	29983	1			T1	13		T2	22		T3	28
valid_sources[0x04]	29959	1			T1	5		T2	34		T3	20
valid_sources[0x05]	30935	1			T1	8		T2	38		T3	26
valid_sources[0x06]	29658	1			T1	6		T2	34		T3	25
valid_sources[0x07]	29709	1			T1	11		T2	40		T3	32
valid_sources[0x08]	30471	1			T1	5		T2	35		T3	30
valid_sources[0x09]	29912	1			T1	8		T2	28		T3	22
valid_sources[0x0a]	29488	1			T1	10		T2	46		T3	35
valid_sources[0x0b]	29732	1			T1	8		T2	32		T3	22
valid_sources[0x0c]	29898	1			T1	5		T2	33		T3	26
valid_sources[0x0d]	30192	1			T1	7		T2	30		T3	30
valid_sources[0x0e]	29887	1			T1	8		T2	43		T3	24
valid_sources[0x0f]	28976	1			T1	7		T2	46		T3	33
valid_sources[0x10]	30056	1			T1	5		T2	44		T3	27
valid_sources[0x11]	29313	1			T1	8		T2	47		T3	29
valid_sources[0x12]	29645	1			T1	4		T2	30		T3	30
valid_sources[0x13]	29323	1			T1	8		T2	23		T3	37
valid_sources[0x14]	30201	1			T1	8		T2	29		T3	27
valid_sources[0x15]	29675	1			T1	4		T2	37		T3	31
valid_sources[0x16]	29089	1			T1	9		T2	44		T3	42
valid_sources[0x17]	29378	1			T1	8		T2	33		T3	23
valid_sources[0x18]	29661	1			T1	17		T2	27		T3	28
valid_sources[0x19]	29202	1			T1	11		T2	49		T3	29
valid_sources[0x1a]	29044	1			T1	7		T2	36		T3	29
valid_sources[0x1b]	30871	1			T1	8		T2	27		T3	41
valid_sources[0x1c]	29276	1			T1	4		T2	34		T3	28
valid_sources[0x1d]	29119	1			T1	5		T2	21		T3	42
valid_sources[0x1e]	29600	1			T1	15		T2	25		T3	25
valid_sources[0x1f]	30006	1			T1	8		T2	38		T3	41
valid_sources[0x20]	29744	1			T1	9		T2	21		T3	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27660

1

T1

5

T2

28

T3

36

values[0x0]

all_enables

biggest_size

207035

1

T1

56

T2

264

T3

209

values[0x1]

all_enables

biggest_size

27321

1

T1

6

T2

23

T3

25