Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	8315224	0	0
GntImpliesValid_A	2147483647	8315224	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8315224	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	478121745	0	0
ReadyAndValidImplyGrant_A	2147483647	8315224	0	0
ReqAndReadyImplyGrant_A	2147483647	8315224	0	0
ReqImpliesValid_A	2147483647	34359076	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48338	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8315224	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	384624	384000	0	0
T2	1198104	1196424	0	0
T3	6677160	6677064	0	0
T7	4882392	4882296	0	0
T8	319944	318312	0	0
T9	12711456	12709896	0	0
T10	3947328	3947280	0	0
T11	40632	40392	0	0
T12	48600	47520	0	0
T13	205560	205032	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	384624	384000	0	0
T2	1198104	1196424	0	0
T3	6677160	6677064	0	0
T7	4882392	4882296	0	0
T8	319944	318312	0	0
T9	12711456	12709896	0	0
T10	3947328	3947280	0	0
T11	40632	40392	0	0
T12	48600	47520	0	0
T13	205560	205032	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	384624	384000	0	0
T2	1198104	1196424	0	0
T3	6677160	6677064	0	0
T7	4882392	4882296	0	0
T8	319944	318312	0	0
T9	12711456	12709896	0	0
T10	3947328	3947280	0	0
T11	40632	40392	0	0
T12	48600	47520	0	0
T13	205560	205032	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	478121745	0	0
T1	320520	17868	0	0
T2	1198104	68097	0	0
T3	6677160	2152447	0	0
T7	4882392	209099	0	0
T8	319944	7707	0	0
T9	12711456	445500	0	0
T10	3947328	1286740	0	0
T11	40632	529	0	0
T12	48600	558	0	0
T13	205560	5922	0	0
T14	125052	4277	0	0
T15	0	3409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34359076	0	0
T1	80130	5226	0	0
T2	1198104	7224	0	0
T3	6677160	368011	0	0
T7	4882392	13946	0	0
T8	319944	5529	0	0
T9	12711456	3618	0	0
T10	3947328	241903	0	0
T11	40632	468	0	0
T12	48600	486	0	0
T13	205560	5710	0	0
T14	593997	2350	0	0
T15	0	3010	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48338	0	21576
T1	16026	45	0	1
T2	49921	0	0	1
T3	278215	0	0	1
T7	203433	0	0	1
T8	26662	17	0	2
T9	1059288	0	0	2
T10	328944	0	0	2
T11	3386	0	0	2
T12	4050	0	0	2
T13	17130	13	0	2
T14	31263	2	0	1
T15	37921	0	0	1
T16	438247	23	0	1
T17	241908	3	0	1
T18	0	31	0	0
T19	0	5	0	0
T20	0	342	0	0
T21	0	2	0	0
T22	0	28	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	384624	384000	0	0
T2	1198104	1196424	0	0
T3	6677160	6677064	0	0
T7	4882392	4882296	0	0
T8	319944	318312	0	0
T9	12711456	12709896	0	0
T10	3947328	3947280	0	0
T11	40632	40392	0	0
T12	48600	47520	0	0
T13	205560	205032	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8315224	0	0
T1	80130	1440	0	0
T2	1198104	3405	0	0
T3	6677160	5989	0	0
T7	4882392	8283	0	0
T8	319944	4712	0	0
T9	12711456	1539	0	0
T10	3947328	4127	0	0
T11	40632	414	0	0
T12	48600	419	0	0
T13	205560	4866	0	0
T14	593997	1624	0	0
T15	0	2087	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	914295	0	0
GntImpliesValid_A	443603072	914295	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	914295	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	12115173	0	0
ReadyAndValidImplyGrant_A	443603072	914295	0	0
ReqAndReadyImplyGrant_A	443603072	914295	0	0
ReqImpliesValid_A	443603072	2432300	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	914295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	12115173	0	0
T1	16026	521	0	0
T2	49921	2832	0	0
T3	278215	228360	0	0
T7	203433	3659	0	0
T8	13331	467	0	0
T9	529644	586	0	0
T10	164472	147251	0	0
T11	1693	37	0	0
T12	2025	43	0	0
T13	8565	399	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2432300	0	0
T1	16026	116	0	0
T2	49921	601	0	0
T3	278215	31825	0	0
T7	203433	1311	0	0
T8	13331	592	0	0
T9	529644	215	0	0
T10	164472	12471	0	0
T11	1693	60	0	0
T12	2025	68	0	0
T13	8565	668	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	914295	0	0
T1	16026	69	0	0
T2	49921	392	0	0
T3	278215	723	0	0
T7	203433	913	0	0
T8	13331	529	0	0
T9	529644	147	0	0
T10	164472	453	0	0
T11	1693	48	0	0
T12	2025	55	0	0
T13	8565	533	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	931042	0	0
GntImpliesValid_A	443603072	931042	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	931042	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	12178303	0	0
ReadyAndValidImplyGrant_A	443603072	931042	0	0
ReqAndReadyImplyGrant_A	443603072	931042	0	0
ReqImpliesValid_A	443603072	2527342	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	931042	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	12178303	0	0
T1	16026	491	0	0
T2	49921	2854	0	0
T3	278215	183261	0	0
T7	203433	3816	0	0
T8	13331	425	0	0
T9	529644	623	0	0
T10	164472	147664	0	0
T11	1693	35	0	0
T12	2025	38	0	0
T13	8565	394	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2527342	0	0
T1	16026	93	0	0
T2	49921	597	0	0
T3	278215	20476	0	0
T7	203433	1250	0	0
T8	13331	580	0	0
T9	529644	225	0	0
T10	164472	14530	0	0
T11	1693	58	0	0
T12	2025	75	0	0
T13	8565	637	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	931042	0	0
T1	16026	61	0	0
T2	49921	387	0	0
T3	278215	653	0	0
T7	203433	918	0	0
T8	13331	502	0	0
T9	529644	163	0	0
T10	164472	450	0	0
T11	1693	46	0	0
T12	2025	56	0	0
T13	8565	515	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	224719	0	0
GntImpliesValid_A	443603072	224719	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	224719	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	2974917	0	0
ReadyAndValidImplyGrant_A	443603072	224719	0	0
ReqAndReadyImplyGrant_A	443603072	224719	0	0
ReqImpliesValid_A	443603072	546404	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	224719	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2974917	0	0
T1	16026	1	0	0
T2	49921	549	0	0
T3	278215	44028	0	0
T7	203433	925	0	0
T8	13331	114	0	0
T9	529644	1455	0	0
T10	164472	36325	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	131	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	546404	0	0
T2	49921	116	0	0
T3	278215	3103	0	0
T7	203433	278	0	0
T8	13331	115	0	0
T9	529644	1180	0	0
T10	164472	3379	0	0
T11	1693	10	0	0
T12	2025	10	0	0
T13	8565	146	0	0
T14	31263	142	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	224719	0	0
T2	49921	81	0	0
T3	278215	139	0	0
T7	203433	236	0	0
T8	13331	114	0	0
T9	529644	458	0	0
T10	164472	119	0	0
T11	1693	10	0	0
T12	2025	9	0	0
T13	8565	138	0	0
T14	31263	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	237710	0	0
GntImpliesValid_A	443603072	237710	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	237710	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3115015	0	0
ReadyAndValidImplyGrant_A	443603072	237710	0	0
ReqAndReadyImplyGrant_A	443603072	237710	0	0
ReqImpliesValid_A	443603072	619718	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	237710	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3115015	0	0
T1	16026	1336	0	0
T2	49921	687	0	0
T3	278215	45834	0	0
T7	203433	990	0	0
T8	13331	128	0	0
T9	529644	1	0	0
T10	164472	42273	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	127	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	619718	0	0
T1	16026	2186	0	0
T2	49921	89	0	0
T3	278215	2536	0	0
T7	203433	250	0	0
T8	13331	145	0	0
T9	529644	0	0	0
T10	164472	1934	0	0
T11	1693	14	0	0
T12	2025	18	0	0
T13	8565	142	0	0
T14	0	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237710	0	0
T1	16026	535	0	0
T2	49921	84	0	0
T3	278215	151	0	0
T7	203433	225	0	0
T8	13331	136	0	0
T9	529644	0	0	0
T10	164472	122	0	0
T11	1693	13	0	0
T12	2025	18	0	0
T13	8565	134	0	0
T14	0	83	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	234375	0	0
GntImpliesValid_A	443603072	234375	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	234375	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	5194648	0	0
ReadyAndValidImplyGrant_A	443603072	234375	0	0
ReqAndReadyImplyGrant_A	443603072	234375	0	0
ReqImpliesValid_A	443603072	1196905	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	234375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	5194648	0	0
T2	49921	2095	0	0
T3	278215	77476	0	0
T7	203433	6277	0	0
T8	13331	1398	0	0
T9	529644	0	0	0
T10	164472	15843	0	0
T11	1693	84	0	0
T12	2025	57	0	0
T13	8565	718	0	0
T14	31263	838	0	0
T15	0	861	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	1196905	0	0
T2	49921	351	0	0
T3	278215	2377	0	0
T7	203433	750	0	0
T8	13331	377	0	0
T9	529644	0	0	0
T10	164472	496	0	0
T11	1693	21	0	0
T12	2025	28	0	0
T13	8565	224	0	0
T14	31263	154	0	0
T15	0	237	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234375	0	0
T2	49921	123	0	0
T3	278215	166	0	0
T7	203433	240	0	0
T8	13331	137	0	0
T9	529644	0	0	0
T10	164472	118	0	0
T11	1693	14	0	0
T12	2025	12	0	0
T13	8565	133	0	0
T14	31263	86	0	0
T15	0	150	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	238164	0	0
GntImpliesValid_A	443603072	238164	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	238164	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	5715165	0	0
ReadyAndValidImplyGrant_A	443603072	238164	0	0
ReqAndReadyImplyGrant_A	443603072	238164	0	0
ReqImpliesValid_A	443603072	1230018	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	238164	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	5715165	0	0
T2	49921	1304	0	0
T3	278215	89357	0	0
T7	203433	2647	0	0
T8	13331	727	0	0
T9	529644	0	0	0
T10	164472	57532	0	0
T11	1693	45	0	0
T12	2025	50	0	0
T13	8565	556	0	0
T14	31263	519	0	0
T15	0	1020	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	1230018	0	0
T2	49921	145	0	0
T3	278215	2996	0	0
T7	203433	364	0	0
T8	13331	166	0	0
T9	529644	0	0	0
T10	164472	2534	0	0
T11	1693	12	0	0
T12	2025	14	0	0
T13	8565	188	0	0
T14	31263	124	0	0
T15	0	177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	238164	0	0
T2	49921	105	0	0
T3	278215	156	0	0
T7	203433	224	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	140	0	0
T14	31263	84	0	0
T15	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	228666	0	0
GntImpliesValid_A	443603072	228666	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	228666	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	6107304	0	0
ReadyAndValidImplyGrant_A	443603072	228666	0	0
ReqAndReadyImplyGrant_A	443603072	228666	0	0
ReqImpliesValid_A	443603072	1183988	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	228666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	6107304	0	0
T2	49921	1192	0	0
T3	278215	236038	0	0
T7	203433	3586	0	0
T8	13331	1939	0	0
T9	529644	0	0	0
T10	164472	12950	0	0
T11	1693	51	0	0
T12	2025	56	0	0
T13	8565	676	0	0
T14	31263	1527	0	0
T15	0	718	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	1183988	0	0
T2	49921	91	0	0
T3	278215	25640	0	0
T7	203433	433	0	0
T8	13331	375	0	0
T9	529644	0	0	0
T10	164472	574	0	0
T11	1693	20	0	0
T12	2025	9	0	0
T13	8565	274	0	0
T14	31263	262	0	0
T15	0	147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228666	0	0
T2	49921	86	0	0
T3	278215	176	0	0
T7	203433	216	0	0
T8	13331	135	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	11	0	0
T12	2025	9	0	0
T13	8565	164	0	0
T14	31263	86	0	0
T15	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	227651	0	0
GntImpliesValid_A	443603072	227651	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	227651	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	4910226	0	0
ReadyAndValidImplyGrant_A	443603072	227651	0	0
ReqAndReadyImplyGrant_A	443603072	227651	0	0
ReqImpliesValid_A	443603072	1041800	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	227651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	4910226	0	0
T2	49921	1293	0	0
T3	278215	44189	0	0
T7	203433	1505	0	0
T8	13331	738	0	0
T9	529644	0	0	0
T10	164472	12098	0	0
T11	1693	63	0	0
T12	2025	113	0	0
T13	8565	1094	0	0
T14	31263	1393	0	0
T15	0	810	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	1041800	0	0
T2	49921	123	0	0
T3	278215	927	0	0
T7	203433	314	0	0
T8	13331	221	0	0
T9	529644	0	0	0
T10	164472	197	0	0
T11	1693	23	0	0
T12	2025	21	0	0
T13	8565	337	0	0
T14	31263	170	0	0
T15	0	166	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227651	0	0
T2	49921	88	0	0
T3	278215	165	0	0
T7	203433	221	0	0
T8	13331	148	0	0
T9	529644	0	0	0
T10	164472	130	0	0
T11	1693	13	0	0
T12	2025	12	0	0
T13	8565	120	0	0
T14	31263	82	0	0
T15	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	223151	0	0
GntImpliesValid_A	443603072	223151	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	223151	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3046247	0	0
ReadyAndValidImplyGrant_A	443603072	223151	0	0
ReqAndReadyImplyGrant_A	443603072	223151	0	0
ReqImpliesValid_A	443603072	560232	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	223151	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3046247	0	0
T1	16026	1	0	0
T2	49921	675	0	0
T3	278215	50471	0	0
T7	203433	1030	0	0
T8	13331	144	0	0
T9	529644	1	0	0
T10	164472	40403	0	0
T11	1693	19	0	0
T12	2025	13	0	0
T13	8565	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	560232	0	0
T2	49921	118	0	0
T3	278215	4998	0	0
T7	203433	341	0	0
T8	13331	163	0	0
T9	529644	0	0	0
T10	164472	2612	0	0
T11	1693	18	0	0
T12	2025	14	0	0
T13	8565	129	0	0
T14	31263	85	0	0
T15	0	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223151	0	0
T2	49921	89	0	0
T3	278215	152	0	0
T7	203433	251	0	0
T8	13331	153	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	18	0	0
T12	2025	13	0	0
T13	8565	122	0	0
T14	31263	76	0	0
T15	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	230340	0	0
GntImpliesValid_A	443603072	230340	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	230340	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3007686	0	0
ReadyAndValidImplyGrant_A	443603072	230340	0	0
ReqAndReadyImplyGrant_A	443603072	230340	0	0
ReqImpliesValid_A	443603072	586127	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	230340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3007686	0	0
T1	16026	1	0	0
T2	49921	861	0	0
T3	278215	59586	0	0
T7	203433	914	0	0
T8	13331	115	0	0
T9	529644	1	0	0
T10	164472	36825	0	0
T11	1693	13	0	0
T12	2025	16	0	0
T13	8565	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	586127	0	0
T2	49921	169	0	0
T3	278215	4472	0	0
T7	203433	261	0	0
T8	13331	122	0	0
T9	529644	0	0	0
T10	164472	1527	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	128	0	0
T14	31263	108	0	0
T15	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	230340	0	0
T2	49921	107	0	0
T3	278215	178	0	0
T7	203433	223	0	0
T8	13331	118	0	0
T9	529644	0	0	0
T10	164472	109	0	0
T11	1693	12	0	0
T12	2025	15	0	0
T13	8565	125	0	0
T14	31263	88	0	0
T15	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	228499	0	0
GntImpliesValid_A	443603072	228499	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	228499	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3083882	0	0
ReadyAndValidImplyGrant_A	443603072	228499	0	0
ReqAndReadyImplyGrant_A	443603072	228499	0	0
ReqImpliesValid_A	443603072	561679	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	228499	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3083882	0	0
T1	16026	1	0	0
T2	49921	656	0	0
T3	278215	49740	0	0
T7	203433	993	0	0
T8	13331	127	0	0
T9	529644	1	0	0
T10	164472	46471	0	0
T11	1693	12	0	0
T12	2025	12	0	0
T13	8565	125	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	561679	0	0
T2	49921	104	0	0
T3	278215	2039	0	0
T7	203433	274	0	0
T8	13331	132	0	0
T9	529644	0	0	0
T10	164472	1538	0	0
T11	1693	13	0	0
T12	2025	11	0	0
T13	8565	136	0	0
T14	31263	118	0	0
T15	0	221	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	228499	0	0
T2	49921	90	0	0
T3	278215	167	0	0
T7	203433	235	0	0
T8	13331	129	0	0
T9	529644	0	0	0
T10	164472	131	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	130	0	0
T14	31263	88	0	0
T15	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	223103	0	0
GntImpliesValid_A	443603072	223103	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	223103	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	2998609	0	0
ReadyAndValidImplyGrant_A	443603072	223103	0	0
ReqAndReadyImplyGrant_A	443603072	223103	0	0
ReqImpliesValid_A	443603072	549284	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	223103	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2998609	0	0
T1	16026	1	0	0
T2	49921	608	0	0
T3	278215	48470	0	0
T7	203433	858	0	0
T8	13331	122	0	0
T9	529644	1	0	0
T10	164472	42882	0	0
T11	1693	14	0	0
T12	2025	20	0	0
T13	8565	128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	549284	0	0
T2	49921	82	0	0
T3	278215	4915	0	0
T7	203433	243	0	0
T8	13331	139	0	0
T9	529644	0	0	0
T10	164472	3492	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	149	0	0
T14	31263	94	0	0
T15	0	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	223103	0	0
T2	49921	81	0	0
T3	278215	157	0	0
T7	203433	215	0	0
T8	13331	130	0	0
T9	529644	0	0	0
T10	164472	126	0	0
T11	1693	13	0	0
T12	2025	19	0	0
T13	8565	138	0	0
T14	31263	77	0	0
T15	0	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	227483	0	0
GntImpliesValid_A	443603072	227483	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	227483	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3041062	0	0
ReadyAndValidImplyGrant_A	443603072	227483	0	0
ReqAndReadyImplyGrant_A	443603072	227483	0	0
ReqImpliesValid_A	443603072	544378	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	227483	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3041062	0	0
T1	16026	1	0	0
T2	49921	748	0	0
T3	278215	52346	0	0
T7	203433	1011	0	0
T8	13331	128	0	0
T9	529644	1677	0	0
T10	164472	35708	0	0
T11	1693	11	0	0
T12	2025	8	0	0
T13	8565	139	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	544378	0	0
T2	49921	113	0	0
T3	278215	1471	0	0
T7	203433	258	0	0
T8	13331	149	0	0
T9	529644	1136	0	0
T10	164472	1955	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	146	0	0
T14	31263	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	227483	0	0
T2	49921	96	0	0
T3	278215	157	0	0
T7	203433	219	0	0
T8	13331	138	0	0
T9	529644	490	0	0
T10	164472	103	0	0
T11	1693	10	0	0
T12	2025	7	0	0
T13	8565	142	0	0
T14	31263	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	234439	0	0
GntImpliesValid_A	443603072	234439	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	234439	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3052558	0	0
ReadyAndValidImplyGrant_A	443603072	234439	0	0
ReqAndReadyImplyGrant_A	443603072	234439	0	0
ReqImpliesValid_A	443603072	614419	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	234439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3052558	0	0
T1	16026	1	0	0
T2	49921	678	0	0
T3	278215	37333	0	0
T7	203433	890	0	0
T8	13331	119	0	0
T9	529644	1	0	0
T10	164472	43992	0	0
T11	1693	9	0	0
T12	2025	10	0	0
T13	8565	126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	614419	0	0
T2	49921	108	0	0
T3	278215	1259	0	0
T7	203433	251	0	0
T8	13331	128	0	0
T9	529644	0	0	0
T10	164472	2475	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	139	0	0
T14	31263	104	0	0
T15	0	192	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234439	0	0
T2	49921	83	0	0
T3	278215	116	0	0
T7	203433	222	0	0
T8	13331	123	0	0
T9	529644	0	0	0
T10	164472	135	0	0
T11	1693	8	0	0
T12	2025	9	0	0
T13	8565	132	0	0
T14	31263	79	0	0
T15	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	225221	0	0
GntImpliesValid_A	443603072	225221	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	225221	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3045474	0	0
ReadyAndValidImplyGrant_A	443603072	225221	0	0
ReqAndReadyImplyGrant_A	443603072	225221	0	0
ReqImpliesValid_A	443603072	539076	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	225221	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3045474	0	0
T1	16026	1	0	0
T2	49921	527	0	0
T3	278215	55166	0	0
T7	203433	1007	0	0
T8	13331	123	0	0
T9	529644	1	0	0
T10	164472	38889	0	0
T11	1693	11	0	0
T12	2025	12	0	0
T13	8565	140	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	539076	0	0
T2	49921	74	0	0
T3	278215	3925	0	0
T7	203433	347	0	0
T8	13331	132	0	0
T9	529644	0	0	0
T10	164472	2795	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	149	0	0
T14	31263	82	0	0
T15	0	203	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225221	0	0
T2	49921	72	0	0
T3	278215	174	0	0
T7	203433	249	0	0
T8	13331	127	0	0
T9	529644	0	0	0
T10	164472	113	0	0
T11	1693	10	0	0
T12	2025	11	0	0
T13	8565	144	0	0
T14	31263	73	0	0
T15	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	231559	0	0
GntImpliesValid_A	443603072	231559	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	231559	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3087376	0	0
ReadyAndValidImplyGrant_A	443603072	231559	0	0
ReqAndReadyImplyGrant_A	443603072	231559	0	0
ReqImpliesValid_A	443603072	599946	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	231559	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3087376	0	0
T1	16026	1	0	0
T2	49921	632	0	0
T3	278215	49529	0	0
T7	203433	885	0	0
T8	13331	114	0	0
T9	529644	1	0	0
T10	164472	35688	0	0
T11	1693	13	0	0
T12	2025	11	0	0
T13	8565	118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	599946	0	0
T2	49921	110	0	0
T3	278215	1568	0	0
T7	203433	246	0	0
T8	13331	125	0	0
T9	529644	0	0	0
T10	164472	3527	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	135	0	0
T14	31263	101	0	0
T15	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	231559	0	0
T2	49921	86	0	0
T3	278215	151	0	0
T7	203433	214	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	10	0	0
T13	8565	126	0	0
T14	31263	79	0	0
T15	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	249436	0	0
GntImpliesValid_A	443603072	249436	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	249436	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3102045	0	0
ReadyAndValidImplyGrant_A	443603072	249436	0	0
ReqAndReadyImplyGrant_A	443603072	249436	0	0
ReqImpliesValid_A	443603072	610626	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	249436	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3102045	0	0
T1	16026	1	0	0
T2	49921	1323	0	0
T3	278215	50313	0	0
T7	203433	983	0	0
T8	13331	189	0	0
T9	529644	1	0	0
T10	164472	34171	0	0
T11	1693	17	0	0
T12	2025	5	0	0
T13	8565	134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	610626	0	0
T2	49921	219	0	0
T3	278215	3327	0	0
T7	203433	254	0	0
T8	13331	206	0	0
T9	529644	0	0	0
T10	164472	2718	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	161	0	0
T14	31263	118	0	0
T15	0	141	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	249436	0	0
T2	49921	166	0	0
T3	278215	182	0	0
T7	203433	229	0	0
T8	13331	197	0	0
T9	529644	0	0	0
T10	164472	107	0	0
T11	1693	16	0	0
T12	2025	7	0	0
T13	8565	147	0	0
T14	31263	87	0	0
T15	0	119	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	225987	0	0
GntImpliesValid_A	443603072	225987	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	225987	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3034027	0	0
ReadyAndValidImplyGrant_A	443603072	225987	0	0
ReqAndReadyImplyGrant_A	443603072	225987	0	0
ReqImpliesValid_A	443603072	545183	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	225987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3034027	0	0
T1	16026	1	0	0
T2	49921	705	0	0
T3	278215	55308	0	0
T7	203433	965	0	0
T8	13331	138	0	0
T9	529644	1	0	0
T10	164472	35490	0	0
T11	1693	12	0	0
T12	2025	11	0	0
T13	8565	142	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	545183	0	0
T2	49921	140	0	0
T3	278215	2927	0	0
T7	203433	266	0	0
T8	13331	139	0	0
T9	529644	0	0	0
T10	164472	648	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	165	0	0
T14	31263	115	0	0
T15	0	196	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	225987	0	0
T2	49921	94	0	0
T3	278215	167	0	0
T7	203433	224	0	0
T8	13331	138	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	11	0	0
T12	2025	10	0	0
T13	8565	153	0	0
T14	31263	82	0	0
T15	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	235791	0	0
GntImpliesValid_A	443603072	235791	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	235791	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3011392	0	0
ReadyAndValidImplyGrant_A	443603072	235791	0	0
ReqAndReadyImplyGrant_A	443603072	235791	0	0
ReqImpliesValid_A	443603072	582158	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	235791	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3011392	0	0
T1	16026	1	0	0
T2	49921	672	0	0
T3	278215	49607	0	0
T7	203433	984	0	0
T8	13331	98	0	0
T9	529644	1	0	0
T10	164472	37410	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	582158	0	0
T2	49921	96	0	0
T3	278215	2786	0	0
T7	203433	256	0	0
T8	13331	103	0	0
T9	529644	0	0	0
T10	164472	4969	0	0
T11	1693	13	0	0
T12	2025	21	0	0
T13	8565	147	0	0
T14	31263	112	0	0
T15	0	152	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	235791	0	0
T2	49921	85	0	0
T3	278215	161	0	0
T7	203433	229	0	0
T8	13331	100	0	0
T9	529644	0	0	0
T10	164472	115	0	0
T11	1693	12	0	0
T12	2025	20	0	0
T13	8565	140	0	0
T14	31263	90	0	0
T15	0	124	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	237327	0	0
GntImpliesValid_A	443603072	237327	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	237327	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	2963781	0	0
ReadyAndValidImplyGrant_A	443603072	237327	0	0
ReqAndReadyImplyGrant_A	443603072	237327	0	0
ReqImpliesValid_A	443603072	601094	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	237327	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2963781	0	0
T1	16026	1	0	0
T2	49921	708	0	0
T3	278215	58973	0	0
T7	203433	985	0	0
T8	13331	116	0	0
T9	529644	1	0	0
T10	164472	31616	0	0
T11	1693	14	0	0
T12	2025	10	0	0
T13	8565	135	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	601094	0	0
T2	49921	148	0	0
T3	278215	2809	0	0
T7	203433	317	0	0
T8	13331	119	0	0
T9	529644	0	0	0
T10	164472	3189	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	152	0	0
T14	31263	64	0	0
T15	0	145	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	237327	0	0
T2	49921	101	0	0
T3	278215	165	0	0
T7	203433	234	0	0
T8	13331	117	0	0
T9	529644	0	0	0
T10	164472	98	0	0
T11	1693	13	0	0
T12	2025	9	0	0
T13	8565	143	0	0
T14	31263	63	0	0
T15	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	234510	0	0
GntImpliesValid_A	443603072	234510	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	234510	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3078675	0	0
ReadyAndValidImplyGrant_A	443603072	234510	0	0
ReqAndReadyImplyGrant_A	443603072	234510	0	0
ReqImpliesValid_A	443603072	603612	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	234510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3078675	0	0
T1	16026	1	0	0
T2	49921	675	0	0
T3	278215	52138	0	0
T7	203433	938	0	0
T8	13331	130	0	0
T9	529644	1	0	0
T10	164472	38293	0	0
T11	1693	15	0	0
T12	2025	12	0	0
T13	8565	128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	603612	0	0
T2	49921	108	0	0
T3	278215	1594	0	0
T7	203433	286	0	0
T8	13331	133	0	0
T9	529644	0	0	0
T10	164472	2943	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	139	0	0
T14	31263	96	0	0
T15	0	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	234510	0	0
T2	49921	87	0	0
T3	278215	153	0	0
T7	203433	236	0	0
T8	13331	131	0	0
T9	529644	0	0	0
T10	164472	121	0	0
T11	1693	14	0	0
T12	2025	11	0	0
T13	8565	133	0	0
T14	31263	78	0	0
T15	0	125	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	221093	0	0
GntImpliesValid_A	443603072	221093	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	221093	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	3056424	0	0
ReadyAndValidImplyGrant_A	443603072	221093	0	0
ReqAndReadyImplyGrant_A	443603072	221093	0	0
ReqImpliesValid_A	443603072	565169	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	0	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	221093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	3056424	0	0
T1	16026	1	0	0
T2	49921	628	0	0
T3	278215	58292	0	0
T7	203433	1020	0	0
T8	13331	106	0	0
T9	529644	1	0	0
T10	164472	37757	0	0
T11	1693	16	0	0
T12	2025	11	0	0
T13	8565	137	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	565169	0	0
T2	49921	109	0	0
T3	278215	5398	0	0
T7	203433	289	0	0
T8	13331	115	0	0
T9	529644	0	0	0
T10	164472	407	0	0
T11	1693	17	0	0
T12	2025	10	0	0
T13	8565	146	0	0
T14	31263	72	0	0
T15	0	179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	221093	0	0
T2	49921	90	0	0
T3	278215	185	0	0
T7	203433	244	0	0
T8	13331	110	0	0
T9	529644	0	0	0
T10	164472	117	0	0
T11	1693	16	0	0
T12	2025	10	0	0
T13	8565	141	0	0
T14	31263	71	0	0
T15	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	932259	0	0
GntImpliesValid_A	443603072	932259	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	932259	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	11449336	0	0
ReadyAndValidImplyGrant_A	443603072	932259	0	0
ReqAndReadyImplyGrant_A	443603072	932259	0	0
ReqImpliesValid_A	443603072	2377636	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	19467	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	932259	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	11449336	0	0
T1	16026	1534	0	0
T2	49921	2416	0	0
T3	278215	231018	0	0
T7	203433	3091	0	0
T8	13331	1	0	0
T9	529644	438	0	0
T10	164472	130740	0	0
T11	1693	1	0	0
T12	2025	1	0	0
T13	8565	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	2377636	0	0
T1	16026	2356	0	0
T2	49921	555	0	0
T3	278215	26224	0	0
T7	203433	1284	0	0
T8	13331	537	0	0
T9	529644	158	0	0
T10	164472	13835	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	19467	0	899
T1	16026	45	0	1
T2	49921	0	0	1
T3	278215	0	0	1
T7	203433	0	0	1
T8	13331	8	0	1
T9	529644	0	0	1
T10	164472	0	0	1
T11	1693	0	0	1
T12	2025	0	0	1
T13	8565	8	0	1
T14	0	1	0	0
T17	0	1	0	0
T18	0	28	0	0
T19	0	1	0	0
T20	0	152	0	0
T21	0	2	0	0
T22	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	932259	0	0
T1	16026	719	0	0
T2	49921	371	0	0
T3	278215	706	0	0
T7	203433	959	0	0
T8	13331	537	0	0
T9	529644	130	0	0
T10	164472	429	0	0
T11	1693	36	0	0
T12	2025	42	0	0
T13	8565	521	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	443603072	443482693	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	443603072	918404	0	0
GntImpliesValid_A	443603072	918404	0	0
GrantKnown_A	443603072	443482693	0	0
IdxKnown_A	443603072	443482693	0	0
IndexIsCorrect_A	443603072	918404	0	0
LockArbDecision_A	443603072	0	0	0
NoReadyValidNoGrant_A	443603072	371752420	0	0
ReadyAndValidImplyGrant_A	443603072	918404	0	0
ReqAndReadyImplyGrant_A	443603072	918404	0	0
ReqImpliesValid_A	443603072	13139982	0	0
ReqStaysHighUntilGranted0_M	443603072	0	0	0
RoundRobin_A	443603072	28871	0	899
ValidKnown_A	443603072	443482693	0	0
gen_data_port_assertion.DataFlow_A	443603072	918404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	371752420	0	0
T1	16026	13971	0	0
T2	49921	42779	0	0
T3	278215	245614	0	0
T7	203433	169140	0	0
T8	13331	1	0	0
T9	529644	440707	0	0
T10	164472	148469	0	0
T11	1693	1	0	0
T12	2025	1	0	0
T13	8565	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	13139982	0	0
T1	16026	475	0	0
T2	49921	2858	0	0
T3	278215	208419	0	0
T7	203433	3823	0	0
T8	13331	516	0	0
T9	529644	704	0	0
T10	164472	157158	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	28871	0	899
T8	13331	9	0	1
T9	529644	0	0	1
T10	164472	0	0	1
T11	1693	0	0	1
T12	2025	0	0	1
T13	8565	5	0	1
T14	31263	1	0	1
T15	37921	0	0	1
T16	438247	23	0	1
T17	241908	2	0	1
T18	0	3	0	0
T19	0	4	0	0
T20	0	190	0	0
T22	0	12	0	0
T23	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	443482693	0	0
T1	16026	16000	0	0
T2	49921	49851	0	0
T3	278215	278211	0	0
T7	203433	203429	0	0
T8	13331	13263	0	0
T9	529644	529579	0	0
T10	164472	164470	0	0
T11	1693	1683	0	0
T12	2025	1980	0	0
T13	8565	8543	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443603072	918404	0	0
T1	16026	56	0	0
T2	49921	361	0	0
T3	278215	689	0	0
T7	203433	907	0	0
T8	13331	516	0	0
T9	529644	151	0	0
T10	164472	454	0	0
T11	1693	34	0	0
T12	2025	34	0	0
T13	8565	552	0	0