Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1441824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

228755

1

T1

28

T2

77

T3

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	567387	1			T1	61		T2	226		T3	969
values[0x0]	535946	1			T1	63		T2	196		T3	966
values[0x1]	567246	1			T1	51		T2	209		T3	1049

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1115922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

554657

1

T1

57

T2

193

T3

951

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26177	1			T1	11		T2	7		T3	50
valid_sources[0x01]	25274	1			T2	23		T3	33		T10	6
valid_sources[0x02]	26082	1			T2	26		T3	40		T7	13
valid_sources[0x03]	26639	1			T2	1		T3	49		T10	10
valid_sources[0x04]	26661	1			T1	7		T3	42		T10	7
valid_sources[0x05]	26319	1			T1	12		T2	6		T3	54
valid_sources[0x06]	25713	1			T2	8		T3	54		T10	6
valid_sources[0x07]	26010	1			T2	33		T3	58		T9	3
valid_sources[0x08]	25730	1			T2	35		T3	48		T10	6
valid_sources[0x09]	26451	1			T1	5		T2	23		T3	45
valid_sources[0x0a]	27512	1			T2	6		T3	47		T10	7
valid_sources[0x0b]	25716	1			T3	30		T7	10		T10	4
valid_sources[0x0c]	25195	1			T2	8		T3	54		T11	27
valid_sources[0x0d]	26226	1			T1	3		T2	13		T3	50
valid_sources[0x0e]	25800	1			T2	2		T3	47		T7	26
valid_sources[0x0f]	25871	1			T2	5		T3	42		T9	15
valid_sources[0x10]	25674	1			T1	1		T3	37		T10	19
valid_sources[0x11]	25782	1			T2	7		T3	46		T10	3
valid_sources[0x12]	26052	1			T1	4		T2	1		T3	46
valid_sources[0x13]	26556	1			T2	17		T3	40		T10	9
valid_sources[0x14]	26293	1			T1	3		T2	7		T3	49
valid_sources[0x15]	26265	1			T2	10		T3	43		T10	10
valid_sources[0x16]	26616	1			T1	2		T2	4		T3	51
valid_sources[0x17]	25117	1			T2	13		T3	47		T10	11
valid_sources[0x18]	26181	1			T1	2		T2	5		T3	53
valid_sources[0x19]	25503	1			T1	10		T2	22		T3	54
valid_sources[0x1a]	25899	1			T1	21		T2	2		T3	41
valid_sources[0x1b]	25762	1			T2	10		T3	46		T10	7
valid_sources[0x1c]	26604	1			T2	3		T3	59		T7	7
valid_sources[0x1d]	25445	1			T1	1		T2	12		T3	45
valid_sources[0x1e]	26024	1			T1	16		T2	19		T3	33
valid_sources[0x1f]	26288	1			T3	47		T10	3		T11	106
valid_sources[0x20]	25272	1			T1	4		T2	10		T3	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24242

1

T1

5

T2

9

T3

51

values[0x0]

all_enables

biggest_size

180681

1

T1

20

T2

64

T3

307

values[0x1]

all_enables

biggest_size

23832

1

T1

3

T2

4

T3

30

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1458046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236548

1

T1

21

T2

115

T3

371

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	580954	1			T1	30		T2	277		T3	987
values[0x0]	533048	1			T1	33		T2	243		T3	907
values[0x1]	580592	1			T1	37		T2	303		T3	967

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1118524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

576070

1

T1

42

T2

281

T3

981

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26595	1			T1	2		T2	27		T3	26
valid_sources[0x01]	26481	1			T2	10		T3	39		T7	3
valid_sources[0x02]	26764	1			T1	4		T2	22		T3	67
valid_sources[0x03]	26279	1			T1	3		T3	43		T9	5
valid_sources[0x04]	26684	1			T1	1		T2	14		T3	26
valid_sources[0x05]	26623	1			T1	1		T2	14		T3	46
valid_sources[0x06]	26603	1			T1	1		T2	12		T3	41
valid_sources[0x07]	26792	1			T1	1		T2	17		T3	40
valid_sources[0x08]	26813	1			T1	2		T2	35		T3	40
valid_sources[0x09]	25678	1			T1	1		T2	22		T3	37
valid_sources[0x0a]	26777	1			T2	7		T3	55		T9	1
valid_sources[0x0b]	26774	1			T1	1		T2	3		T3	46
valid_sources[0x0c]	25571	1			T2	4		T3	55		T9	3
valid_sources[0x0d]	26189	1			T1	1		T2	7		T3	37
valid_sources[0x0e]	27040	1			T1	3		T2	13		T3	55
valid_sources[0x0f]	26516	1			T1	2		T2	14		T3	61
valid_sources[0x10]	26403	1			T1	3		T2	2		T3	53
valid_sources[0x11]	26269	1			T1	1		T2	7		T3	47
valid_sources[0x12]	26478	1			T1	2		T2	10		T3	42
valid_sources[0x13]	26018	1			T1	3		T2	14		T3	45
valid_sources[0x14]	26511	1			T2	7		T3	54		T7	3
valid_sources[0x15]	26988	1			T1	2		T2	2		T3	57
valid_sources[0x16]	26210	1			T1	2		T2	36		T3	52
valid_sources[0x17]	26336	1			T1	1		T2	21		T3	35
valid_sources[0x18]	26669	1			T1	2		T2	18		T3	31
valid_sources[0x19]	25872	1			T1	2		T2	29		T3	54
valid_sources[0x1a]	26737	1			T1	3		T2	5		T3	42
valid_sources[0x1b]	26585	1			T1	1		T2	3		T3	49
valid_sources[0x1c]	26346	1			T2	12		T3	34		T7	2
valid_sources[0x1d]	26569	1			T2	12		T3	55		T9	1
valid_sources[0x1e]	26746	1			T2	17		T3	38		T10	10
valid_sources[0x1f]	26447	1			T1	1		T2	8		T3	59
valid_sources[0x20]	26203	1			T2	8		T3	44		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24915

1

T1

2

T2

11

T3

33

values[0x0]

all_enables

biggest_size

186652

1

T1

16

T2

90

T3

311

values[0x1]

all_enables

biggest_size

24981

1

T1

3

T2

14

T3

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1455678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

230589

1

T1

23

T2

113

T3

419

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572627	1			T1	53		T2	281		T3	1009
values[0x0]	541474	1			T1	55		T2	304		T3	978
values[0x1]	572166	1			T1	54		T2	282		T3	903

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1124965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

561302

1

T1

52

T2

274

T3

949

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25970	1			T1	4		T2	4		T3	50
valid_sources[0x01]	26591	1			T1	1		T2	32		T3	40
valid_sources[0x02]	26138	1			T1	1		T2	59		T3	46
valid_sources[0x03]	26942	1			T1	1		T2	3		T3	40
valid_sources[0x04]	26217	1			T1	3		T2	7		T3	41
valid_sources[0x05]	26752	1			T1	1		T2	3		T3	49
valid_sources[0x06]	26164	1			T1	2		T2	19		T3	44
valid_sources[0x07]	26342	1			T1	3		T2	39		T3	41
valid_sources[0x08]	27289	1			T1	2		T2	48		T3	52
valid_sources[0x09]	26862	1			T1	2		T2	30		T3	57
valid_sources[0x0a]	25558	1			T1	4		T2	4		T3	46
valid_sources[0x0b]	26200	1			T1	5		T2	4		T3	43
valid_sources[0x0c]	25769	1			T1	2		T2	17		T3	50
valid_sources[0x0d]	26208	1			T2	3		T3	52		T10	7
valid_sources[0x0e]	26104	1			T2	11		T3	50		T10	9
valid_sources[0x0f]	26891	1			T2	3		T3	57		T10	12
valid_sources[0x10]	26445	1			T1	2		T2	1		T3	44
valid_sources[0x11]	26372	1			T1	3		T2	18		T3	45
valid_sources[0x12]	26122	1			T1	7		T2	1		T3	47
valid_sources[0x13]	26802	1			T1	5		T2	18		T3	44
valid_sources[0x14]	25915	1			T1	2		T2	6		T3	49
valid_sources[0x15]	26944	1			T1	1		T2	8		T3	34
valid_sources[0x16]	25940	1			T1	7		T2	11		T3	50
valid_sources[0x17]	26437	1			T1	3		T2	11		T3	41
valid_sources[0x18]	26575	1			T1	2		T2	3		T3	44
valid_sources[0x19]	26095	1			T1	3		T2	28		T3	41
valid_sources[0x1a]	26408	1			T1	2		T2	6		T3	52
valid_sources[0x1b]	25601	1			T1	6		T2	9		T3	45
valid_sources[0x1c]	26257	1			T1	1		T2	12		T3	45
valid_sources[0x1d]	26544	1			T1	1		T2	11		T3	44
valid_sources[0x1e]	26370	1			T1	6		T2	17		T3	40
valid_sources[0x1f]	26785	1			T1	2		T3	38		T10	8
valid_sources[0x20]	25933	1			T1	1		T2	7		T3	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24143

1

T1

2

T2

9

T3

43

values[0x0]

all_enables

biggest_size

182254

1

T1

18

T2

93

T3

330

values[0x1]

all_enables

biggest_size

24192

1

T1

3

T2

11

T3

46