Unified Coverage Report :: Module

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7543742	0	0
GntImpliesValid_A	2147483647	7543742	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7543742	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	491999823	0	0
ReadyAndValidImplyGrant_A	2147483647	7543742	0	0
ReqAndReadyImplyGrant_A	2147483647	7543742	0	0
ReqImpliesValid_A	2147483647	35234097	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40773	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7543742	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	234360	234168
T2	441744	428688
T3	8300136	8299992
T7	39408	39120
T8	65448	60360
T9	34056	32592
T10	8556168	8553744
T11	312216	310776
T12	46944	45864
T13	9068160	9068064

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	21600	21600
T1	24	24
T2	24	24
T3	24	24
T7	24	24
T8	24	24
T9	24	24
T10	24	24
T11	24	24
T12	24	24
T13	24	24

GntImpliesReady_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

GntImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

GrantKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	234360	234168
T2	441744	428688
T3	8300136	8299992
T7	39408	39120
T8	65448	60360
T9	34056	32592
T10	8556168	8553744
T11	312216	310776
T12	46944	45864
T13	9068160	9068064

IdxKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	234360	234168
T2	441744	428688
T3	8300136	8299992
T7	39408	39120
T8	65448	60360
T9	34056	32592
T10	8556168	8553744
T11	312216	310776
T12	46944	45864
T13	9068160	9068064

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	2147483647	491999823
T1	234360	11505
T2	441744	26371
T3	8300136	313062
T7	39408	487
T8	65448	4126
T9	34056	579
T10	8556168	473449
T11	312216	7643
T12	46944	551
T13	9068160	344257
T14	0	12224
T16	0	1850
T17	0	2815

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	2147483647	35234097
T1	234360	820
T2	441744	4011
T3	8300136	21799
T7	39408	438
T8	65448	457
T9	34056	471
T10	8556168	123500
T11	312216	5356
T12	46944	455
T13	9068160	20784
T14	0	5041
T15	0	1612
T16	0	276
T17	0	1672

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	2147483647	40773	21600
T3	345839	12	1
T7	1642	0	1
T8	2727	0	1
T9	1419	0	1
T10	356507	0	1
T11	26018	8	2
T12	3912	0	2
T13	755680	0	2
T14	441690	0	2
T15	672090	4	2
T16	9702	0	1
T17	241663	7	1
T18	24281	12	1
T19	0	1	0
T20	0	2	0
T21	0	303	0
T22	0	1	0
T23	0	319	0
T24	0	176	0
T25	0	7	0
T26	0	356	0
T27	0	24	0
T28	0	1	0
T29	0	23	0
T30	2391	0	1
T31	42239	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	234360	234168
T2	441744	428688
T3	8300136	8299992
T7	39408	39120
T8	65448	60360
T9	34056	32592
T10	8556168	8553744
T11	312216	310776
T12	46944	45864
T13	9068160	9068064

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	2147483647	7543742
T1	234360	437
T2	441744	1825
T3	8300136	8730
T7	39408	401
T8	65448	240
T9	34056	381
T10	8556168	31062
T11	312216	4493
T12	46944	400
T13	9068160	9223
T14	0	3435
T15	0	971
T16	0	133
T17	0	458

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	842120	0	0
GntImpliesValid_A	456712087	842120	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	842120	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	12428697	0	0
ReadyAndValidImplyGrant_A	456712087	842120	0	0
ReqAndReadyImplyGrant_A	456712087	842120	0	0
ReqImpliesValid_A	456712087	2428046	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	842120	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	12428697
T1	9765	326
T2	18406	1406
T3	345839	2693
T7	1642	28
T8	2727	176
T9	1419	29
T10	356507	21016
T11	13009	425
T12	1956	44
T13	377840	5084

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	2428046
T1	9765	51
T2	18406	246
T3	345839	947
T7	1642	37
T8	2727	33
T9	1419	54
T10	356507	4531
T11	13009	592
T12	1956	73
T13	377840	2768

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	842120
T1	9765	38
T2	18406	198
T3	345839	647
T7	1642	32
T8	2727	25
T9	1419	41
T10	356507	2979
T11	13009	508
T12	1956	58
T13	377840	1421

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	855805	0	0
GntImpliesValid_A	456712087	855805	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	855805	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	12820424	0	0
ReadyAndValidImplyGrant_A	456712087	855805	0	0
ReqAndReadyImplyGrant_A	456712087	855805	0	0
ReqImpliesValid_A	456712087	2597080	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	855805	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	12820424
T1	9765	301
T2	18406	1543
T3	345839	2806
T7	1642	30
T8	2727	213
T9	1419	41
T10	356507	23754
T11	13009	415
T12	1956	41
T13	377840	5288

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	2597080
T1	9765	43
T2	18406	274
T3	345839	955
T7	1642	35
T8	2727	38
T9	1419	70
T10	356507	6586
T11	13009	590
T12	1956	54
T13	377840	2761

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	855805
T1	9765	43
T2	18406	204
T3	345839	700
T7	1642	32
T8	2727	23
T9	1419	55
T10	356507	3644
T11	13009	502
T12	1956	47
T13	377840	1419

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	213054	0	0
GntImpliesValid_A	456712087	213054	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	213054	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3133485	0	0
ReadyAndValidImplyGrant_A	456712087	213054	0	0
ReqAndReadyImplyGrant_A	456712087	213054	0	0
ReqImpliesValid_A	456712087	606626	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	213054	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3133485
T1	9765	83
T2	18406	320
T3	345839	1676
T7	1642	11
T8	2727	64
T9	1419	14
T10	356507	4699
T11	13009	108
T12	1956	9
T13	377840	1858

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	606626
T1	9765	20
T2	18406	36
T3	345839	1116
T7	1642	10
T8	2727	5
T9	1419	17
T10	356507	2624
T11	13009	117
T12	1956	10
T13	377840	1128

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	213054
T1	9765	9
T2	18406	36
T3	345839	496
T7	1642	10
T8	2727	5
T9	1419	15
T10	356507	984
T11	13009	112
T12	1956	9
T13	377840	538

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	209067	0	0
GntImpliesValid_A	456712087	209067	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	209067	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3155601	0	0
ReadyAndValidImplyGrant_A	456712087	209067	0	0
ReqAndReadyImplyGrant_A	456712087	209067	0	0
ReqImpliesValid_A	456712087	578041	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	209067	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3155601
T1	9765	78
T2	18406	339
T3	345839	1621
T7	1642	14
T8	2727	27
T9	1419	6
T10	356507	3936
T11	13009	116
T12	1956	11
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	578041
T1	9765	28
T2	18406	48
T3	345839	1267
T7	1642	15
T8	2727	4
T9	1419	5
T10	356507	678
T11	13009	121
T12	1956	14
T13	377840	0
T14	0	275

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	209067
T1	9765	17
T2	18406	48
T3	345839	494
T7	1642	14
T8	2727	4
T9	1419	5
T10	356507	519
T11	13009	118
T12	1956	12
T13	377840	0
T14	0	230

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T9

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	207158	0	0
GntImpliesValid_A	456712087	207158	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	207158	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	4823526	0	0
ReadyAndValidImplyGrant_A	456712087	207158	0	0
ReqAndReadyImplyGrant_A	456712087	207158	0	0
ReqImpliesValid_A	456712087	1081875	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	207158	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	4823526
T1	9765	58
T2	18406	389
T3	345839	0
T7	1642	45
T8	2727	265
T9	1419	67
T10	356507	3431
T11	13009	748
T12	1956	136
T13	377840	0
T14	0	3246
T16	0	471

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	1081875
T1	9765	13
T2	18406	66
T3	345839	0
T7	1642	14
T8	2727	5
T9	1419	15
T10	356507	602
T11	13009	181
T12	1956	20
T13	377840	0
T14	0	404
T16	0	55

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	207158
T1	9765	13
T2	18406	58
T3	345839	0
T7	1642	11
T8	2727	5
T9	1419	11
T10	356507	499
T11	13009	123
T12	1956	11
T13	377840	0
T14	0	203
T16	0	26

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T9

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	207338	0	0
GntImpliesValid_A	456712087	207338	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	207338	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	5172236	0	0
ReadyAndValidImplyGrant_A	456712087	207338	0	0
ReqAndReadyImplyGrant_A	456712087	207338	0	0
ReqImpliesValid_A	456712087	1252525	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	207338	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	5172236
T1	9765	71
T2	18406	318
T3	345839	0
T7	1642	32
T8	2727	21
T9	1419	64
T10	356507	5727
T11	13009	2170
T12	1956	24
T13	377840	0
T14	0	3601
T16	0	310

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	1252525
T1	9765	17
T2	18406	56
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	25
T10	356507	7607
T11	13009	409
T12	1956	5
T13	377840	0
T14	0	556
T16	0	38

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	207338
T1	9765	14
T2	18406	44
T3	345839	0
T7	1642	9
T8	2727	4
T9	1419	10
T10	356507	925
T11	13009	107
T12	1956	5
T13	377840	0
T14	0	221
T16	0	23

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T9

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	203698	0	0
GntImpliesValid_A	456712087	203698	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	203698	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	5120666	0	0
ReadyAndValidImplyGrant_A	456712087	203698	0	0
ReqAndReadyImplyGrant_A	456712087	203698	0	0
ReqImpliesValid_A	456712087	1119952	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	203698	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	5120666
T1	9765	37
T2	18406	465
T3	345839	0
T7	1642	37
T8	2727	0
T9	1419	88
T10	356507	3056
T11	13009	514
T12	1956	97
T13	377840	0
T14	0	1686
T16	0	750
T17	0	2815

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	1119952
T1	9765	9
T2	18406	91
T3	345839	0
T7	1642	17
T8	2727	0
T9	1419	32
T10	356507	503
T11	13009	163
T12	1956	23
T13	377840	0
T14	0	305
T16	0	104
T17	0	1672

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	203698
T1	9765	9
T2	18406	48
T3	345839	0
T7	1642	12
T8	2727	0
T9	1419	12
T10	356507	442
T11	13009	106
T12	1956	9
T13	377840	0
T14	0	214
T16	0	26
T17	0	458

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T2,T7,T9

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	205514	0	0
GntImpliesValid_A	456712087	205514	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	205514	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	4936054	0	0
ReadyAndValidImplyGrant_A	456712087	205514	0	0
ReqAndReadyImplyGrant_A	456712087	205514	0	0
ReqImpliesValid_A	456712087	1061290	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	205514	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	4936054
T1	9765	48
T2	18406	605
T3	345839	0
T7	1642	106
T8	2727	35
T9	1419	110
T10	356507	9045
T11	13009	1391
T12	1956	48
T13	377840	0
T14	0	3691
T16	0	319

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	1061290
T1	9765	10
T2	18406	356
T3	345839	0
T7	1642	26
T8	2727	4
T9	1419	26
T10	356507	12764
T11	13009	303
T12	1956	8
T13	377840	0
T14	0	582
T16	0	43

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	205514
T1	9765	10
T2	18406	117
T3	345839	0
T7	1642	15
T8	2727	4
T9	1419	11
T10	356507	1105
T11	13009	116
T12	1956	8
T13	377840	0
T14	0	218
T16	0	32

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	205013	0	0
GntImpliesValid_A	456712087	205013	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	205013	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3110734	0	0
ReadyAndValidImplyGrant_A	456712087	205013	0	0
ReqAndReadyImplyGrant_A	456712087	205013	0	0
ReqImpliesValid_A	456712087	554665	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	205013	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3110734
T1	9765	95
T2	18406	347
T3	345839	1705
T7	1642	22
T8	2727	29
T9	1419	13
T10	356507	3477
T11	13009	113
T12	1956	11
T13	377840	1834

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	554665
T1	9765	34
T2	18406	51
T3	345839	1225
T7	1642	23
T8	2727	3
T9	1419	14
T10	356507	591
T11	13009	130
T12	1956	10
T13	377840	1214

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	205013
T1	9765	15
T2	18406	45
T3	345839	527
T7	1642	22
T8	2727	3
T9	1419	13
T10	356507	466
T11	13009	121
T12	1956	10
T13	377840	534

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T10

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T10
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	204605	0	0
GntImpliesValid_A	456712087	204605	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	204605	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3091445	0	0
ReadyAndValidImplyGrant_A	456712087	204605	0	0
ReqAndReadyImplyGrant_A	456712087	204605	0	0
ReqImpliesValid_A	456712087	593021	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	204605	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3091445
T1	9765	100
T2	18406	386
T3	345839	1
T7	1642	11
T8	2727	67
T9	1419	6
T10	356507	3964
T11	13009	118
T12	1956	6
T13	377840	5023

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	593021
T1	9765	18
T2	18406	52
T3	345839	0
T7	1642	12
T8	2727	7
T9	1419	5
T10	356507	656
T11	13009	133
T12	1956	5
T13	377840	3624
T14	0	302

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	204605
T1	9765	18
T2	18406	45
T3	345839	0
T7	1642	11
T8	2727	7
T9	1419	5
T10	356507	527
T11	13009	125
T12	1956	5
T13	377840	1526
T14	0	222

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T10

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T7,T10
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	213231	0	0
GntImpliesValid_A	456712087	213231	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	213231	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3108242	0	0
ReadyAndValidImplyGrant_A	456712087	213231	0	0
ReqAndReadyImplyGrant_A	456712087	213231	0	0
ReqImpliesValid_A	456712087	593551	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	213231	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3108242
T1	9765	106
T2	18406	378
T3	345839	1
T7	1642	11
T8	2727	22
T9	1419	7
T10	356507	7382
T11	13009	108
T12	1956	13
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	593551
T1	9765	17
T2	18406	53
T3	345839	0
T7	1642	12
T8	2727	4
T9	1419	6
T10	356507	6951
T11	13009	121
T12	1956	14
T13	377840	0
T14	0	242
T16	0	36

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	213231
T1	9765	17
T2	18406	46
T3	345839	0
T7	1642	11
T8	2727	4
T9	1419	6
T10	356507	1433
T11	13009	114
T12	1956	13
T13	377840	0
T14	0	209
T16	0	26

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T10,T11
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	217161	0	0
GntImpliesValid_A	456712087	217161	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	217161	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3182722	0	0
ReadyAndValidImplyGrant_A	456712087	217161	0	0
ReqAndReadyImplyGrant_A	456712087	217161	0	0
ReqImpliesValid_A	456712087	649237	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	217161	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3182722
T1	9765	76
T2	18406	331
T3	345839	1522
T7	1642	18
T8	2727	10
T9	1419	14
T10	356507	8223
T11	13009	108
T12	1956	5
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	649237
T1	9765	12
T2	18406	41
T3	345839	1057
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	13868
T11	13009	117
T12	1956	4
T13	377840	0
T14	0	288

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	217161
T1	9765	12
T2	18406	41
T3	345839	474
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	2078
T11	13009	112
T12	1956	4
T13	377840	0
T14	0	231

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T11

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T10,T11
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	202271	0	0
GntImpliesValid_A	456712087	202271	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	202271	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3125176	0	0
ReadyAndValidImplyGrant_A	456712087	202271	0	0
ReqAndReadyImplyGrant_A	456712087	202271	0	0
ReqImpliesValid_A	456712087	565414	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	202271	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3125176
T1	9765	141
T2	18406	460
T3	345839	1
T7	1642	10
T8	2727	17
T9	1419	12
T10	356507	6066
T11	13009	126
T12	1956	7
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	565414
T1	9765	14
T2	18406	65
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	3477
T11	13009	131
T12	1956	6
T13	377840	0
T14	0	260
T15	0	785

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	202271
T1	9765	14
T2	18406	58
T3	345839	0
T7	1642	9
T8	2727	2
T9	1419	11
T10	356507	995
T11	13009	128
T12	1956	6
T13	377840	0
T14	0	199
T15	0	481

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T10

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T10
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	210705	0	0
GntImpliesValid_A	456712087	210705	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	210705	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3060277	0	0
ReadyAndValidImplyGrant_A	456712087	210705	0	0
ReqAndReadyImplyGrant_A	456712087	210705	0	0
ReqImpliesValid_A	456712087	613267	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	210705	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3060277
T1	9765	70
T2	18406	309
T3	345839	3350
T7	1642	9
T8	2727	46
T9	1419	13
T10	356507	4685
T11	13009	110
T12	1956	8
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	613267
T1	9765	10
T2	18406	55
T3	345839	2385
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	5307
T11	13009	119
T12	1956	7
T13	377840	0
T14	0	272

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	210705
T1	9765	10
T2	18406	39
T3	345839	989
T7	1642	8
T8	2727	4
T9	1419	12
T10	356507	985
T11	13009	114
T12	1956	7
T13	377840	0
T14	0	217

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	206833	0	0
GntImpliesValid_A	456712087	206833	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	206833	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3124589	0	0
ReadyAndValidImplyGrant_A	456712087	206833	0	0
ReqAndReadyImplyGrant_A	456712087	206833	0	0
ReqImpliesValid_A	456712087	578090	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	206833	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3124589
T1	9765	52
T2	18406	284
T3	345839	1649
T7	1642	17
T8	2727	62
T9	1419	13
T10	356507	6278
T11	13009	127
T12	1956	9
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	578090
T1	9765	15
T2	18406	63
T3	345839	1198
T7	1642	18
T8	2727	5
T9	1419	16
T10	356507	3297
T11	13009	132
T12	1956	12
T13	377840	0
T14	0	276

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	206833
T1	9765	10
T2	18406	38
T3	345839	490
T7	1642	17
T8	2727	5
T9	1419	14
T10	356507	994
T11	13009	129
T12	1956	10
T13	377840	0
T14	0	219

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	205826	0	0
GntImpliesValid_A	456712087	205826	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	205826	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3078275	0	0
ReadyAndValidImplyGrant_A	456712087	205826	0	0
ReqAndReadyImplyGrant_A	456712087	205826	0	0
ReqImpliesValid_A	456712087	588719	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	205826	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3078275
T1	9765	130
T2	18406	382
T3	345839	1532
T7	1642	10
T8	2727	50
T9	1419	11
T10	356507	3620
T11	13009	115
T12	1956	11
T13	377840	1599

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	588719
T1	9765	17
T2	18406	49
T3	345839	1175
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	558
T11	13009	120
T12	1956	10
T13	377840	1169

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	205826
T1	9765	15
T2	18406	49
T3	345839	474
T7	1642	9
T8	2727	7
T9	1419	10
T10	356507	479
T11	13009	117
T12	1956	10
T13	377840	478

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	234146	0	0
GntImpliesValid_A	456712087	234146	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	234146	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3221624	0	0
ReadyAndValidImplyGrant_A	456712087	234146	0	0
ReqAndReadyImplyGrant_A	456712087	234146	0	0
ReqImpliesValid_A	456712087	639996	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	234146	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3221624
T1	9765	205
T2	18406	322
T3	345839	1
T7	1642	17
T8	2727	25
T9	1419	13
T10	356507	7691
T11	13009	223
T12	1956	7
T13	377840	1917

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	639996
T1	9765	24
T2	18406	72
T3	345839	0
T7	1642	18
T8	2727	2
T9	1419	14
T10	356507	8153
T11	13009	248
T12	1956	6
T13	377840	1180
T14	0	248

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	234146
T1	9765	22
T2	18406	52
T3	345839	0
T7	1642	17
T8	2727	2
T9	1419	13
T10	356507	1558
T11	13009	235
T12	1956	6
T13	377840	561
T14	0	205

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	204022	0	0
GntImpliesValid_A	456712087	204022	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	204022	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3133508	0	0
ReadyAndValidImplyGrant_A	456712087	204022	0	0
ReqAndReadyImplyGrant_A	456712087	204022	0	0
ReqImpliesValid_A	456712087	542064	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	204022	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3133508
T1	9765	116
T2	18406	327
T3	345839	1577
T7	1642	9
T8	2727	100
T9	1419	12
T10	356507	3711
T11	13009	113
T12	1956	10
T13	377840	1769

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	542064
T1	9765	48
T2	18406	41
T3	345839	1063
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	580
T11	13009	124
T12	1956	9
T13	377840	1135

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	204022
T1	9765	16
T2	18406	41
T3	345839	481
T7	1642	8
T8	2727	8
T9	1419	11
T10	356507	499
T11	13009	118
T12	1956	9
T13	377840	510

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	219789	0	0
GntImpliesValid_A	456712087	219789	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	219789	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3151704	0	0
ReadyAndValidImplyGrant_A	456712087	219789	0	0
ReqAndReadyImplyGrant_A	456712087	219789	0	0
ReqImpliesValid_A	456712087	622891	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	219789	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3151704
T1	9765	66
T2	18406	287
T3	345839	1
T7	1642	9
T8	2727	27
T9	1419	12
T10	356507	4431
T11	13009	126
T12	1956	14
T13	377840	3336

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	622891
T1	9765	13
T2	18406	54
T3	345839	0
T7	1642	8
T8	2727	6
T9	1419	13
T10	356507	4984
T11	13009	135
T12	1956	13
T13	377840	2411
T14	0	242

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	219789
T1	9765	13
T2	18406	42
T3	345839	0
T7	1642	8
T8	2727	5
T9	1419	12
T10	356507	946
T11	13009	130
T12	1956	13
T13	377840	1036
T14	0	209

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	192549	0	0
GntImpliesValid_A	456712087	192549	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	192549	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	2991503	0	0
ReadyAndValidImplyGrant_A	456712087	192549	0	0
ReqAndReadyImplyGrant_A	456712087	192549	0	0
ReqImpliesValid_A	456712087	513207	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	192549	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	2991503
T1	9765	163
T2	18406	312
T3	345839	1529
T7	1642	11
T8	2727	420
T9	1419	15
T10	356507	5601
T11	13009	115
T12	1956	10
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	513207
T1	9765	30
T2	18406	43
T3	345839	1141
T7	1642	12
T8	2727	133
T9	1419	16
T10	356507	2099
T11	13009	116
T12	1956	11
T13	377840	0
T14	0	245

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	192549
T1	9765	17
T2	18406	43
T3	345839	486
T7	1642	11
T8	2727	65
T9	1419	15
T10	356507	927
T11	13009	115
T12	1956	10
T13	377840	0
T14	0	195

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	210151	0	0
GntImpliesValid_A	456712087	210151	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	210151	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3138227	0	0
ReadyAndValidImplyGrant_A	456712087	210151	0	0
ReqAndReadyImplyGrant_A	456712087	210151	0	0
ReqImpliesValid_A	456712087	572742	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	210151	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3138227
T1	9765	109
T2	18406	324
T3	345839	1648
T7	1642	11
T8	2727	61
T9	1419	9
T10	356507	3686
T11	13009	140
T12	1956	12
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	572742
T1	9765	14
T2	18406	48
T3	345839	1291
T7	1642	12
T8	2727	7
T9	1419	8
T10	356507	678
T11	13009	151
T12	1956	17
T13	377840	0
T14	0	252

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	210151
T1	9765	14
T2	18406	38
T3	345839	510
T7	1642	11
T8	2727	7
T9	1419	8
T10	356507	501
T11	13009	145
T12	1956	14
T13	377840	0
T14	0	207

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	215167	0	0
GntImpliesValid_A	456712087	215167	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	215167	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	3115766	0	0
ReadyAndValidImplyGrant_A	456712087	215167	0	0
ReqAndReadyImplyGrant_A	456712087	215167	0	0
ReqImpliesValid_A	456712087	633577	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	0	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	215167	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	3115766
T1	9765	175
T2	18406	672
T3	345839	1
T7	1642	17
T8	2727	78
T9	1419	8
T10	356507	4086
T11	13009	112
T12	1956	16
T13	377840	1

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	633577
T1	9765	45
T2	18406	160
T3	345839	0
T7	1642	20
T8	2727	9
T9	1419	7
T10	356507	6272
T11	13009	121
T12	1956	15
T13	377840	0
T14	0	292
T15	0	827

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	900

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	215167
T1	9765	20
T2	18406	90
T3	345839	0
T7	1642	18
T8	2727	9
T9	1419	7
T10	356507	1022
T11	13009	116
T12	1956	15
T13	377840	0
T14	0	236
T15	0	490

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	832490	0	0
GntImpliesValid_A	456712087	832490	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	832490	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	12030240	0	0
ReadyAndValidImplyGrant_A	456712087	832490	0	0
ReqAndReadyImplyGrant_A	456712087	832490	0	0
ReqImpliesValid_A	456712087	2258506	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	17021	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	832490	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	12030240
T1	9765	254
T2	18406	1155
T3	345839	1994
T7	1642	1
T8	2727	138
T9	1419	1
T10	356507	21808
T11	13009	1
T12	1956	1
T13	377840	1917

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	2258506
T1	9765	38
T2	18406	239
T3	345839	794
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	7269
T11	13009	512
T12	1956	45
T13	377840	777

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	456712087	17021	900
T11	13009	4	1
T12	1956	0	1
T13	377840	0	1
T14	220845	0	1
T15	336045	0	1
T16	9702	0	1
T17	241663	7	1
T18	24281	0	1
T21	0	296	0
T23	0	15	0
T24	0	24	0
T25	0	7	0
T26	0	356	0
T27	0	24	0
T28	0	1	0
T29	0	23	0
T30	2391	0	1
T31	42239	0	1

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	832490
T1	9765	35
T2	18406	189
T3	345839	623
T7	1642	58
T8	2727	15
T9	1419	38
T10	356507	3599
T11	13009	512
T12	1956	45
T13	377840	599

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00



	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	90	(ready_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456712087	456588629	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	456712087	826029	0	0
GntImpliesValid_A	456712087	826029	0	0
GrantKnown_A	456712087	456588629	0	0
IdxKnown_A	456712087	456588629	0	0
IndexIsCorrect_A	456712087	826029	0	0
LockArbDecision_A	456712087	0	0	0
NoReadyValidNoGrant_A	456712087	384745102	0	0
ReadyAndValidImplyGrant_A	456712087	826029	0	0
ReqAndReadyImplyGrant_A	456712087	826029	0	0
ReqImpliesValid_A	456712087	13989715	0	0
ReqStaysHighUntilGranted0_M	456712087	0	0	0
RoundRobin_A	456712087	23752	0	900
ValidKnown_A	456712087	456588629	0	0
gen_data_port_assertion.DataFlow_A	456712087	826029	0	0

CheckHotOne_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

CheckNGreaterZero_A

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1
T13	1	1

GntImpliesReady_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

GntImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

GrantKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IdxKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

IndexIsCorrect_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes
Total	456712087	384745102
T1	9765	8645
T2	18406	14710
T3	345839	287754
T7	1642	1
T8	2727	2173
T9	1419	1
T10	356507	304076
T11	13009	1
T12	1956	1
T13	377840	314623

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

ReqImpliesValid_A

Name	Attempts	Real Successes
Total	456712087	13989715
T1	9765	280
T2	18406	1752
T3	345839	6185
T7	1642	31
T8	2727	150
T9	1419	33
T10	356507	22865
T11	13009	470
T12	1956	64
T13	377840	2617

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456712087	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Incomplete
Total	456712087	23752	900
T3	345839	12	1
T7	1642	0	1
T8	2727	0	1
T9	1419	0	1
T10	356507	0	1
T11	13009	4	1
T12	1956	0	1
T13	377840	0	1
T14	220845	0	1
T15	336045	4	1
T18	0	12	0
T19	0	1	0
T20	0	2	0
T21	0	7	0
T22	0	1	0
T23	0	304	0
T24	0	152	0

ValidKnown_A

Name	Attempts	Real Successes
Total	456712087	456588629
T1	9765	9757
T2	18406	17862
T3	345839	345833
T7	1642	1630
T8	2727	2515
T9	1419	1358
T10	356507	356406
T11	13009	12949
T12	1956	1911
T13	377840	377836

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes
Total	456712087	826029
T1	9765	36
T2	18406	216
T3	345839	1339
T7	1642	31
T8	2727	25
T9	1419	33
T10	356507	2956
T11	13009	470
T12	1956	64
T13	377840	601

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33