Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1514065 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 240921 1 T1 17 T2 23 T3 290


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 596643 1 T1 48 T2 64 T3 734
values[0x0] 562105 1 T1 43 T2 69 T3 675
values[0x1] 596238 1 T1 50 T2 48 T3 728


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1169350 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 585636 1 T1 44 T2 46 T3 721


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27087 1 T2 2 T3 44 T8 2
valid_sources[0x01] 27887 1 T2 5 T3 31 T9 11
valid_sources[0x02] 27676 1 T2 5 T3 33 T8 1
valid_sources[0x03] 26910 1 T2 2 T3 21 T9 9
valid_sources[0x04] 26540 1 T2 5 T3 35 T7 12
valid_sources[0x05] 26927 1 T1 3 T2 2 T3 23
valid_sources[0x06] 28021 1 T1 5 T2 3 T3 35
valid_sources[0x07] 27150 1 T3 42 T8 2 T9 6
valid_sources[0x08] 28444 1 T2 2 T3 43 T8 5
valid_sources[0x09] 28028 1 T2 4 T3 41 T7 2
valid_sources[0x0a] 28467 1 T1 3 T2 1 T3 35
valid_sources[0x0b] 26676 1 T1 5 T2 5 T3 25
valid_sources[0x0c] 27972 1 T2 3 T3 34 T7 19
valid_sources[0x0d] 26001 1 T2 5 T3 32 T8 3
valid_sources[0x0e] 28426 1 T2 2 T3 41 T8 4
valid_sources[0x0f] 27932 1 T1 6 T2 4 T3 29
valid_sources[0x10] 28393 1 T2 1 T3 32 T7 14
valid_sources[0x11] 27590 1 T2 5 T3 35 T8 1
valid_sources[0x12] 26253 1 T3 40 T8 1 T9 11
valid_sources[0x13] 26816 1 T2 3 T3 43 T7 23
valid_sources[0x14] 27225 1 T2 2 T3 35 T8 2
valid_sources[0x15] 27431 1 T2 2 T3 32 T8 1
valid_sources[0x16] 27213 1 T2 5 T3 35 T7 10
valid_sources[0x17] 27979 1 T1 3 T2 1 T3 33
valid_sources[0x18] 27300 1 T1 10 T2 3 T3 35
valid_sources[0x19] 27526 1 T1 4 T2 3 T3 34
valid_sources[0x1a] 26883 1 T1 1 T2 4 T3 33
valid_sources[0x1b] 27547 1 T1 8 T2 2 T3 35
valid_sources[0x1c] 27879 1 T1 3 T2 3 T3 29
valid_sources[0x1d] 27844 1 T2 3 T3 38 T8 1
valid_sources[0x1e] 27778 1 T1 5 T2 2 T3 27
valid_sources[0x1f] 27496 1 T1 1 T2 5 T3 20
valid_sources[0x20] 27930 1 T1 1 T3 28 T9 5


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25366 1 T2 1 T3 26 T8 4
values[0x0] all_enables biggest_size 189983 1 T1 16 T2 21 T3 244
values[0x1] all_enables biggest_size 25572 1 T1 1 T2 1 T3 20


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1530146 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 249426 1 T1 18 T2 35 T3 289


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 610781 1 T1 34 T2 111 T3 716
values[0x0] 559589 1 T1 42 T2 72 T3 681
values[0x1] 609202 1 T1 45 T2 110 T3 759


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1173684 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605888 1 T1 37 T2 101 T3 706


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28107 1 T3 30 T7 5 T9 3
valid_sources[0x01] 27420 1 T2 3 T3 34 T7 2
valid_sources[0x02] 28068 1 T2 4 T3 69 T8 2
valid_sources[0x03] 28121 1 T3 48 T7 2 T8 2
valid_sources[0x04] 28128 1 T2 1 T3 31 T8 1
valid_sources[0x05] 27502 1 T1 2 T2 1 T3 44
valid_sources[0x06] 26910 1 T3 26 T8 4 T9 21
valid_sources[0x07] 28052 1 T1 5 T2 17 T3 17
valid_sources[0x08] 27360 1 T2 1 T3 14 T7 1
valid_sources[0x09] 27334 1 T2 2 T3 35 T7 5
valid_sources[0x0a] 27554 1 T2 3 T3 26 T7 6
valid_sources[0x0b] 27837 1 T2 2 T3 68 T7 7
valid_sources[0x0c] 28011 1 T1 8 T2 18 T3 52
valid_sources[0x0d] 27686 1 T2 6 T3 45 T8 1
valid_sources[0x0e] 28443 1 T2 4 T3 53 T8 4
valid_sources[0x0f] 27606 1 T2 6 T3 23 T7 10
valid_sources[0x10] 28255 1 T2 6 T3 41 T7 2
valid_sources[0x11] 28227 1 T1 3 T3 32 T7 2
valid_sources[0x12] 27392 1 T1 7 T2 4 T3 29
valid_sources[0x13] 27768 1 T2 4 T3 31 T7 1
valid_sources[0x14] 27619 1 T1 2 T2 17 T3 21
valid_sources[0x15] 28428 1 T1 1 T3 14 T7 3
valid_sources[0x16] 27310 1 T2 5 T3 31 T7 2
valid_sources[0x17] 28033 1 T1 2 T3 28 T7 9
valid_sources[0x18] 27660 1 T3 36 T8 2 T9 7
valid_sources[0x19] 27296 1 T1 5 T2 10 T3 37
valid_sources[0x1a] 28539 1 T2 11 T3 34 T8 2
valid_sources[0x1b] 28318 1 T1 5 T2 2 T3 27
valid_sources[0x1c] 27568 1 T2 10 T3 51 T7 4
valid_sources[0x1d] 27203 1 T1 1 T2 2 T3 22
valid_sources[0x1e] 28336 1 T1 1 T2 5 T3 15
valid_sources[0x1f] 27033 1 T1 15 T2 3 T3 36
valid_sources[0x20] 27449 1 T1 1 T3 30 T7 6


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26416 1 T1 2 T2 5 T3 33
values[0x0] all_enables biggest_size 196802 1 T1 15 T2 25 T3 233
values[0x1] all_enables biggest_size 26208 1 T1 1 T2 5 T3 23


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1520196 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 241783 1 T1 15 T2 27 T3 312


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 599226 1 T1 38 T2 75 T3 753
values[0x0] 564788 1 T1 31 T2 71 T3 740
values[0x1] 597965 1 T1 41 T2 64 T3 738


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1173618 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 588361 1 T1 38 T2 64 T3 748


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27119 1 T2 3 T3 35 T8 1
valid_sources[0x01] 27849 1 T2 8 T3 40 T7 2
valid_sources[0x02] 28550 1 T3 34 T9 27 T10 29
valid_sources[0x03] 27449 1 T3 33 T7 3 T8 3
valid_sources[0x04] 27348 1 T2 5 T3 37 T8 2
valid_sources[0x05] 27427 1 T2 1 T3 31 T7 3
valid_sources[0x06] 27587 1 T2 1 T3 41 T8 2
valid_sources[0x07] 28039 1 T1 12 T2 2 T3 26
valid_sources[0x08] 27176 1 T2 4 T3 39 T8 1
valid_sources[0x09] 27357 1 T1 6 T2 2 T3 33
valid_sources[0x0a] 27743 1 T2 4 T3 33 T9 16
valid_sources[0x0b] 27367 1 T2 4 T3 37 T9 4
valid_sources[0x0c] 26958 1 T2 4 T3 48 T7 7
valid_sources[0x0d] 27028 1 T2 3 T3 40 T8 2
valid_sources[0x0e] 27682 1 T2 4 T3 26 T7 3
valid_sources[0x0f] 27075 1 T2 4 T3 24 T8 1
valid_sources[0x10] 27128 1 T2 2 T3 32 T8 2
valid_sources[0x11] 27323 1 T1 3 T2 4 T3 22
valid_sources[0x12] 27323 1 T2 3 T3 54 T7 3
valid_sources[0x13] 26794 1 T2 4 T3 36 T8 5
valid_sources[0x14] 26780 1 T2 1 T3 53 T7 2
valid_sources[0x15] 28331 1 T2 3 T3 31 T9 2
valid_sources[0x16] 26878 1 T2 2 T3 29 T7 2
valid_sources[0x17] 27767 1 T2 3 T3 30 T7 1
valid_sources[0x18] 27928 1 T2 4 T3 45 T8 2
valid_sources[0x19] 27184 1 T1 7 T2 3 T3 35
valid_sources[0x1a] 28832 1 T2 3 T3 25 T7 9
valid_sources[0x1b] 27888 1 T2 2 T3 29 T8 2
valid_sources[0x1c] 27232 1 T2 3 T3 32 T8 3
valid_sources[0x1d] 27612 1 T2 4 T3 40 T7 5
valid_sources[0x1e] 27652 1 T2 7 T3 36 T8 2
valid_sources[0x1f] 27317 1 T2 5 T3 36 T8 2
valid_sources[0x20] 27536 1 T1 6 T2 3 T3 19


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25282 1 T1 3 T2 2 T3 25
values[0x0] all_enables biggest_size 191133 1 T1 12 T2 20 T3 260
values[0x1] all_enables biggest_size 25368 1 T2 5 T3 27 T7 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%