Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7956368	0	0
GntImpliesValid_A	2147483647	7956368	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7956368	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	448223571	0	0
ReadyAndValidImplyGrant_A	2147483647	7956368	0	0
ReqAndReadyImplyGrant_A	2147483647	7956368	0	0
ReqImpliesValid_A	2147483647	33687639	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49671	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7956368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5722896	5722080	0	0
T2	159192	158808	0	0
T3	180144	179952	0	0
T7	7051872	7051632	0	0
T8	1257192	1256256	0	0
T9	72600	72384	0	0
T10	1918584	1917480	0	0
T11	638832	638568	0	0
T12	3771960	3739248	0	0
T13	5261496	5244936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5722896	5722080	0	0
T2	159192	158808	0	0
T3	180144	179952	0	0
T7	7051872	7051632	0	0
T8	1257192	1256256	0	0
T9	72600	72384	0	0
T10	1918584	1917480	0	0
T11	638832	638568	0	0
T12	3771960	3739248	0	0
T13	5261496	5244936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5722896	5722080	0	0
T2	159192	158808	0	0
T3	180144	179952	0	0
T7	7051872	7051632	0	0
T8	1257192	1256256	0	0
T9	72600	72384	0	0
T10	1918584	1917480	0	0
T11	638832	638568	0	0
T12	3771960	3739248	0	0
T13	5261496	5244936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	448223571	0	0
T1	5722896	200006	0	0
T2	159192	7725	0	0
T3	180144	3230	0	0
T7	7051872	246637	0	0
T8	1257192	76045	0	0
T9	72600	2178	0	0
T10	1918584	128218	0	0
T11	638832	30723	0	0
T12	3771960	86289	0	0
T13	5261496	305260	0	0
T14	0	3287	0	0
T15	0	34472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33687639	0	0
T1	5722896	585	0	0
T2	159192	4679	0	0
T3	180144	3723	0	0
T7	7051872	821	0	0
T8	1257192	8376	0	0
T9	72600	2044	0	0
T10	1918584	17349	0	0
T11	638832	17076	0	0
T12	3771960	116937	0	0
T13	5261496	93558	0	0
T14	0	2672	0	0
T15	0	4487	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49671	0	21600
T3	15012	17	0	2
T7	587656	0	0	2
T8	104766	0	0	2
T9	6050	10	0	2
T10	159882	0	0	2
T11	53236	0	0	2
T12	314330	825	0	2
T13	438458	22	0	2
T14	15878	18	0	2
T15	954928	0	0	2
T16	0	33	0	0
T17	0	61	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	41	0	0
T21	0	2	0	0
T22	0	580	0	0
T23	0	5	0	0
T24	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5722896	5722080	0	0
T2	159192	158808	0	0
T3	180144	179952	0	0
T7	7051872	7051632	0	0
T8	1257192	1256256	0	0
T9	72600	72384	0	0
T10	1918584	1917480	0	0
T11	638832	638568	0	0
T12	3771960	3739248	0	0
T13	5261496	5244936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7956368	0	0
T1	5722896	372	0	0
T2	159192	684	0	0
T3	180144	3397	0	0
T7	7051872	494	0	0
T8	1257192	3600	0	0
T9	72600	1798	0	0
T10	1918584	6648	0	0
T11	638832	2876	0	0
T12	3771960	94426	0	0
T13	5261496	20219	0	0
T14	0	2171	0	0
T15	0	242	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	886967	0	0
GntImpliesValid_A	408662289	886967	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	886967	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	11985123	0	0
ReadyAndValidImplyGrant_A	408662289	886967	0	0
ReqAndReadyImplyGrant_A	408662289	886967	0	0
ReqImpliesValid_A	408662289	2471125	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	886967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	11985123	0	0
T1	238454	185	0	0
T2	6633	456	0	0
T3	7506	306	0	0
T7	293828	251	0	0
T8	52383	2864	0	0
T9	3025	139	0	0
T10	79941	5417	0	0
T11	26618	1461	0	0
T12	157165	8442	0	0
T13	219229	12933	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2471125	0	0
T1	238454	64	0	0
T2	6633	80	0	0
T3	7506	417	0	0
T7	293828	86	0	0
T8	52383	508	0	0
T9	3025	208	0	0
T10	79941	1355	0	0
T11	26618	412	0	0
T12	157165	17800	0	0
T13	219229	2952	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886967	0	0
T1	238454	49	0	0
T2	6633	63	0	0
T3	7506	361	0	0
T7	293828	58	0	0
T8	52383	390	0	0
T9	3025	173	0	0
T10	79941	753	0	0
T11	26618	205	0	0
T12	157165	13112	0	0
T13	219229	1864	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	886755	0	0
GntImpliesValid_A	408662289	886755	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	886755	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	12036345	0	0
ReadyAndValidImplyGrant_A	408662289	886755	0	0
ReqAndReadyImplyGrant_A	408662289	886755	0	0
ReqImpliesValid_A	408662289	2391118	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	886755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	12036345	0	0
T1	238454	191	0	0
T2	6633	651	0	0
T3	7506	310	0	0
T7	293828	254	0	0
T8	52383	3406	0	0
T9	3025	144	0	0
T10	79941	5269	0	0
T11	26618	2916	0	0
T12	157165	7883	0	0
T13	219229	13609	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2391118	0	0
T1	238454	57	0	0
T2	6633	140	0	0
T3	7506	459	0	0
T7	293828	76	0	0
T8	52383	703	0	0
T9	3025	227	0	0
T10	79941	1449	0	0
T11	26618	3569	0	0
T12	157165	13452	0	0
T13	219229	3208	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	886755	0	0
T1	238454	41	0	0
T2	6633	78	0	0
T3	7506	384	0	0
T7	293828	52	0	0
T8	52383	443	0	0
T9	3025	185	0	0
T10	79941	712	0	0
T11	26618	934	0	0
T12	157165	10658	0	0
T13	219229	2018	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	222839	0	0
GntImpliesValid_A	408662289	222839	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	222839	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3042662	0	0
ReadyAndValidImplyGrant_A	408662289	222839	0	0
ReqAndReadyImplyGrant_A	408662289	222839	0	0
ReqImpliesValid_A	408662289	588520	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	222839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3042662	0	0
T1	238454	57	0	0
T2	6633	1	0	0
T3	7506	91	0	0
T7	293828	56	0	0
T8	52383	699	0	0
T9	3025	45	0	0
T10	79941	1319	0	0
T11	26618	1	0	0
T12	157165	2324	0	0
T13	219229	2230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	588520	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	14	0	0
T8	52383	93	0	0
T9	3025	50	0	0
T10	79941	232	0	0
T11	26618	0	0	0
T12	157165	2846	0	0
T13	219229	309	0	0
T14	0	110	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222839	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	95	0	0
T7	293828	14	0	0
T8	52383	86	0	0
T9	3025	47	0	0
T10	79941	168	0	0
T11	26618	0	0	0
T12	157165	2576	0	0
T13	219229	281	0	0
T14	0	102	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	213916	0	0
GntImpliesValid_A	408662289	213916	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	213916	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	2966119	0	0
ReadyAndValidImplyGrant_A	408662289	213916	0	0
ReqAndReadyImplyGrant_A	408662289	213916	0	0
ReqImpliesValid_A	408662289	496207	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	213916	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2966119	0	0
T1	238454	42	0	0
T2	6633	1	0	0
T3	7506	92	0	0
T7	293828	64	0	0
T8	52383	652	0	0
T9	3025	50	0	0
T10	79941	1478	0	0
T11	26618	1	0	0
T12	157165	2060	0	0
T13	219229	1807	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	496207	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	19	0	0
T8	52383	129	0	0
T9	3025	53	0	0
T10	79941	308	0	0
T11	26618	0	0	0
T12	157165	2325	0	0
T13	219229	264	0	0
T14	0	142	0	0
T15	0	459	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213916	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	18	0	0
T8	52383	93	0	0
T9	3025	51	0	0
T10	79941	207	0	0
T11	26618	0	0	0
T12	157165	2183	0	0
T13	219229	239	0	0
T14	0	133	0	0
T15	0	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	215900	0	0
GntImpliesValid_A	408662289	215900	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	215900	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	5938869	0	0
ReadyAndValidImplyGrant_A	408662289	215900	0	0
ReqAndReadyImplyGrant_A	408662289	215900	0	0
ReqImpliesValid_A	408662289	1155133	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	215900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	5938869	0	0
T1	238454	59	0	0
T2	6633	0	0	0
T3	7506	322	0	0
T7	293828	60	0	0
T8	52383	1485	0	0
T9	3025	436	0	0
T10	79941	8142	0	0
T11	26618	0	0	0
T12	157165	8116	0	0
T13	219229	17016	0	0
T14	0	784	0	0
T15	0	20196	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	1155133	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	130	0	0
T7	293828	13	0	0
T8	52383	176	0	0
T9	3025	105	0	0
T10	79941	1024	0	0
T11	26618	0	0	0
T12	157165	2090	0	0
T13	219229	30901	0	0
T14	0	193	0	0
T15	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	215900	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	103	0	0
T7	293828	13	0	0
T8	52383	109	0	0
T9	3025	69	0	0
T10	79941	184	0	0
T11	26618	0	0	0
T12	157165	1613	0	0
T13	219229	1489	0	0
T14	0	101	0	0
T15	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	212473	0	0
GntImpliesValid_A	408662289	212473	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	212473	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	5438511	0	0
ReadyAndValidImplyGrant_A	408662289	212473	0	0
ReqAndReadyImplyGrant_A	408662289	212473	0	0
ReqImpliesValid_A	408662289	1127047	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	212473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	5438511	0	0
T1	238454	73	0	0
T2	6633	0	0	0
T3	7506	286	0	0
T7	293828	62	0	0
T8	52383	1215	0	0
T9	3025	190	0	0
T10	79941	7007	0	0
T11	26618	0	0	0
T12	157165	8762	0	0
T13	219229	6910	0	0
T14	0	697	0	0
T15	0	3566	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	1127047	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	138	0	0
T7	293828	18	0	0
T8	52383	101	0	0
T9	3025	77	0	0
T10	79941	834	0	0
T11	26618	0	0	0
T12	157165	5505	0	0
T13	219229	3606	0	0
T14	0	200	0	0
T15	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212473	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	14	0	0
T8	52383	80	0	0
T9	3025	45	0	0
T10	79941	192	0	0
T11	26618	0	0	0
T12	157165	2230	0	0
T13	219229	717	0	0
T14	0	100	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	209885	0	0
GntImpliesValid_A	408662289	209885	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	209885	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	4928295	0	0
ReadyAndValidImplyGrant_A	408662289	209885	0	0
ReqAndReadyImplyGrant_A	408662289	209885	0	0
ReqImpliesValid_A	408662289	1042564	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	209885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	4928295	0	0
T1	238454	105	0	0
T2	6633	0	0	0
T3	7506	297	0	0
T7	293828	107	0	0
T8	52383	6092	0	0
T9	3025	172	0	0
T10	79941	2819	0	0
T11	26618	0	0	0
T12	157165	9676	0	0
T13	219229	2092	0	0
T14	0	1098	0	0
T15	0	5844	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	1042564	0	0
T1	238454	17	0	0
T2	6633	0	0	0
T3	7506	127	0	0
T7	293828	24	0	0
T8	52383	660	0	0
T9	3025	94	0	0
T10	79941	365	0	0
T11	26618	0	0	0
T12	157165	4330	0	0
T13	219229	287	0	0
T14	0	268	0	0
T15	0	735	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	209885	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	16	0	0
T8	52383	97	0	0
T9	3025	60	0	0
T10	79941	163	0	0
T11	26618	0	0	0
T12	157165	2169	0	0
T13	219229	252	0	0
T14	0	119	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	207100	0	0
GntImpliesValid_A	408662289	207100	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	207100	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	5142166	0	0
ReadyAndValidImplyGrant_A	408662289	207100	0	0
ReqAndReadyImplyGrant_A	408662289	207100	0	0
ReqImpliesValid_A	408662289	1062981	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	207100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	5142166	0	0
T1	238454	99	0	0
T2	6633	0	0	0
T3	7506	276	0	0
T7	293828	116	0	0
T8	52383	2162	0	0
T9	3025	290	0	0
T10	79941	5296	0	0
T11	26618	0	0	0
T12	157165	8835	0	0
T13	219229	2374	0	0
T14	0	708	0	0
T15	0	4866	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	1062981	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	102	0	0
T7	293828	35	0	0
T8	52383	237	0	0
T9	3025	81	0	0
T10	79941	674	0	0
T11	26618	0	0	0
T12	157165	2189	0	0
T13	219229	343	0	0
T14	0	190	0	0
T15	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	207100	0	0
T1	238454	7	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	18	0	0
T8	52383	84	0	0
T9	3025	63	0	0
T10	79941	166	0	0
T11	26618	0	0	0
T12	157165	1689	0	0
T13	219229	264	0	0
T14	0	113	0	0
T15	0	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	229311	0	0
GntImpliesValid_A	408662289	229311	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	229311	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3012241	0	0
ReadyAndValidImplyGrant_A	408662289	229311	0	0
ReqAndReadyImplyGrant_A	408662289	229311	0	0
ReqImpliesValid_A	408662289	607969	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	229311	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3012241	0	0
T1	238454	40	0	0
T2	6633	1	0	0
T3	7506	75	0	0
T7	293828	59	0	0
T8	52383	644	0	0
T9	3025	48	0	0
T10	79941	1583	0	0
T11	26618	1	0	0
T12	157165	1583	0	0
T13	219229	2546	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	607969	0	0
T1	238454	21	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	13	0	0
T8	52383	106	0	0
T9	3025	51	0	0
T10	79941	310	0	0
T11	26618	0	0	0
T12	157165	2694	0	0
T13	219229	692	0	0
T14	0	112	0	0
T15	0	176	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	229311	0	0
T1	238454	14	0	0
T2	6633	0	0	0
T3	7506	78	0	0
T7	293828	12	0	0
T8	52383	88	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	0	0	0
T12	157165	2129	0	0
T13	219229	370	0	0
T14	0	106	0	0
T15	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	225134	0	0
GntImpliesValid_A	408662289	225134	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	225134	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3022599	0	0
ReadyAndValidImplyGrant_A	408662289	225134	0	0
ReqAndReadyImplyGrant_A	408662289	225134	0	0
ReqImpliesValid_A	408662289	576814	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	225134	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3022599	0	0
T1	238454	68	0	0
T2	6633	1	0	0
T3	7506	79	0	0
T7	293828	44	0	0
T8	52383	762	0	0
T9	3025	55	0	0
T10	79941	1585	0	0
T11	26618	1	0	0
T12	157165	1632	0	0
T13	219229	5595	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	576814	0	0
T1	238454	19	0	0
T2	6633	0	0	0
T3	7506	84	0	0
T7	293828	10	0	0
T8	52383	172	0	0
T9	3025	70	0	0
T10	79941	302	0	0
T11	26618	0	0	0
T12	157165	3727	0	0
T13	219229	5764	0	0
T14	0	115	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	225134	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	10	0	0
T8	52383	100	0	0
T9	3025	62	0	0
T10	79941	194	0	0
T11	26618	0	0	0
T12	157165	2670	0	0
T13	219229	1141	0	0
T14	0	110	0	0
T15	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	220004	0	0
GntImpliesValid_A	408662289	220004	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	220004	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3044392	0	0
ReadyAndValidImplyGrant_A	408662289	220004	0	0
ReqAndReadyImplyGrant_A	408662289	220004	0	0
ReqImpliesValid_A	408662289	590561	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	220004	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3044392	0	0
T1	238454	34	0	0
T2	6633	1	0	0
T3	7506	76	0	0
T7	293828	58	0	0
T8	52383	738	0	0
T9	3025	45	0	0
T10	79941	1304	0	0
T11	26618	1	0	0
T12	157165	1921	0	0
T13	219229	3183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	590561	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	87	0	0
T7	293828	18	0	0
T8	52383	108	0	0
T9	3025	52	0	0
T10	79941	229	0	0
T11	26618	0	0	0
T12	157165	2195	0	0
T13	219229	3656	0	0
T14	0	117	0	0
T15	0	337	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220004	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	12	0	0
T8	52383	101	0	0
T9	3025	48	0	0
T10	79941	170	0	0
T11	26618	0	0	0
T12	157165	2049	0	0
T13	219229	698	0	0
T14	0	112	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	226237	0	0
GntImpliesValid_A	408662289	226237	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	226237	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3008351	0	0
ReadyAndValidImplyGrant_A	408662289	226237	0	0
ReqAndReadyImplyGrant_A	408662289	226237	0	0
ReqImpliesValid_A	408662289	544614	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	226237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3008351	0	0
T1	238454	17	0	0
T2	6633	1	0	0
T3	7506	96	0	0
T7	293828	44	0	0
T8	52383	592	0	0
T9	3025	51	0	0
T10	79941	1159	0	0
T11	26618	1	0	0
T12	157165	1907	0	0
T13	219229	2005	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	544614	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	105	0	0
T7	293828	16	0	0
T8	52383	113	0	0
T9	3025	58	0	0
T10	79941	254	0	0
T11	26618	0	0	0
T12	157165	2394	0	0
T13	219229	368	0	0
T14	0	99	0	0
T15	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	226237	0	0
T1	238454	6	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	11	0	0
T8	52383	92	0	0
T9	3025	54	0	0
T10	79941	165	0	0
T11	26618	0	0	0
T12	157165	2141	0	0
T13	219229	275	0	0
T14	0	94	0	0
T15	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	219668	0	0
GntImpliesValid_A	408662289	219668	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	219668	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3017507	0	0
ReadyAndValidImplyGrant_A	408662289	219668	0	0
ReqAndReadyImplyGrant_A	408662289	219668	0	0
ReqImpliesValid_A	408662289	553918	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	219668	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3017507	0	0
T1	238454	26	0	0
T2	6633	1	0	0
T3	7506	78	0	0
T7	293828	49	0	0
T8	52383	721	0	0
T9	3025	47	0	0
T10	79941	1429	0	0
T11	26618	685	0	0
T12	157165	2502	0	0
T13	219229	2006	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	553918	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	93	0	0
T7	293828	13	0	0
T8	52383	132	0	0
T9	3025	52	0	0
T10	79941	273	0	0
T11	26618	4882	0	0
T12	157165	3641	0	0
T13	219229	308	0	0
T14	0	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	219668	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	13	0	0
T8	52383	100	0	0
T9	3025	49	0	0
T10	79941	202	0	0
T11	26618	484	0	0
T12	157165	3062	0	0
T13	219229	258	0	0
T14	0	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	213050	0	0
GntImpliesValid_A	408662289	213050	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	213050	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	2955109	0	0
ReadyAndValidImplyGrant_A	408662289	213050	0	0
ReqAndReadyImplyGrant_A	408662289	213050	0	0
ReqImpliesValid_A	408662289	510292	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	213050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2955109	0	0
T1	238454	40	0	0
T2	6633	1	0	0
T3	7506	80	0	0
T7	293828	19	0	0
T8	52383	582	0	0
T9	3025	47	0	0
T10	79941	1286	0	0
T11	26618	411	0	0
T12	157165	2147	0	0
T13	219229	5514	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	510292	0	0
T1	238454	16	0	0
T2	6633	0	0	0
T3	7506	85	0	0
T7	293828	7	0	0
T8	52383	97	0	0
T9	3025	54	0	0
T10	79941	245	0	0
T11	26618	4608	0	0
T12	157165	4146	0	0
T13	219229	1908	0	0
T14	0	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	213050	0	0
T1	238454	10	0	0
T2	6633	0	0	0
T3	7506	82	0	0
T7	293828	7	0	0
T8	52383	78	0	0
T9	3025	50	0	0
T10	79941	189	0	0
T11	26618	450	0	0
T12	157165	3137	0	0
T13	219229	803	0	0
T14	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	222817	0	0
GntImpliesValid_A	408662289	222817	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	222817	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	2999831	0	0
ReadyAndValidImplyGrant_A	408662289	222817	0	0
ReqAndReadyImplyGrant_A	408662289	222817	0	0
ReqImpliesValid_A	408662289	561817	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	222817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2999831	0	0
T1	238454	65	0	0
T2	6633	1	0	0
T3	7506	83	0	0
T7	293828	44	0	0
T8	52383	776	0	0
T9	3025	61	0	0
T10	79941	1490	0	0
T11	26618	1	0	0
T12	157165	3035	0	0
T13	219229	1847	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	561817	0	0
T1	238454	13	0	0
T2	6633	0	0	0
T3	7506	90	0	0
T7	293828	23	0	0
T8	52383	165	0	0
T9	3025	64	0	0
T10	79941	313	0	0
T11	26618	0	0	0
T12	157165	6054	0	0
T13	219229	274	0	0
T14	0	128	0	0
T15	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222817	0	0
T1	238454	11	0	0
T2	6633	0	0	0
T3	7506	86	0	0
T7	293828	12	0	0
T8	52383	106	0	0
T9	3025	62	0	0
T10	79941	204	0	0
T11	26618	0	0	0
T12	157165	4535	0	0
T13	219229	235	0	0
T14	0	122	0	0
T15	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	217755	0	0
GntImpliesValid_A	408662289	217755	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	217755	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3080402	0	0
ReadyAndValidImplyGrant_A	408662289	217755	0	0
ReqAndReadyImplyGrant_A	408662289	217755	0	0
ReqImpliesValid_A	408662289	566677	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	217755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3080402	0	0
T1	238454	44	0	0
T2	6633	1	0	0
T3	7506	78	0	0
T7	293828	69	0	0
T8	52383	654	0	0
T9	3025	47	0	0
T10	79941	1181	0	0
T11	26618	1	0	0
T12	157165	2086	0	0
T13	219229	7006	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	566677	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	81	0	0
T7	293828	16	0	0
T8	52383	95	0	0
T9	3025	60	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	2557	0	0
T13	219229	2576	0	0
T14	0	106	0	0
T15	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	217755	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	79	0	0
T7	293828	15	0	0
T8	52383	88	0	0
T9	3025	53	0	0
T10	79941	180	0	0
T11	26618	0	0	0
T12	157165	2312	0	0
T13	219229	1214	0	0
T14	0	104	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	257043	0	0
GntImpliesValid_A	408662289	257043	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	257043	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3118427	0	0
ReadyAndValidImplyGrant_A	408662289	257043	0	0
ReqAndReadyImplyGrant_A	408662289	257043	0	0
ReqImpliesValid_A	408662289	655195	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	257043	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3118427	0	0
T1	238454	40	0	0
T2	6633	1	0	0
T3	7506	151	0	0
T7	293828	59	0	0
T8	52383	1227	0	0
T9	3025	50	0	0
T10	79941	1337	0	0
T11	26618	1	0	0
T12	157165	1864	0	0
T13	219229	1899	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	655195	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	166	0	0
T7	293828	15	0	0
T8	52383	213	0	0
T9	3025	51	0	0
T10	79941	347	0	0
T11	26618	0	0	0
T12	157165	1961	0	0
T13	219229	298	0	0
T14	0	122	0	0
T15	0	237	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	257043	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	158	0	0
T7	293828	15	0	0
T8	52383	168	0	0
T9	3025	50	0	0
T10	79941	186	0	0
T11	26618	0	0	0
T12	157165	1903	0	0
T13	219229	247	0	0
T14	0	115	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	214852	0	0
GntImpliesValid_A	408662289	214852	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	214852	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	2960764	0	0
ReadyAndValidImplyGrant_A	408662289	214852	0	0
ReqAndReadyImplyGrant_A	408662289	214852	0	0
ReqImpliesValid_A	408662289	558260	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	214852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2960764	0	0
T1	238454	34	0	0
T2	6633	1	0	0
T3	7506	100	0	0
T7	293828	54	0	0
T8	52383	789	0	0
T9	3025	69	0	0
T10	79941	1202	0	0
T11	26618	1037	0	0
T12	157165	2340	0	0
T13	219229	3818	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	558260	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	117	0	0
T7	293828	19	0	0
T8	52383	111	0	0
T9	3025	70	0	0
T10	79941	197	0	0
T11	26618	1901	0	0
T12	157165	2947	0	0
T13	219229	2847	0	0
T14	0	107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	214852	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	108	0	0
T7	293828	17	0	0
T8	52383	100	0	0
T9	3025	69	0	0
T10	79941	169	0	0
T11	26618	454	0	0
T12	157165	2634	0	0
T13	219229	671	0	0
T14	0	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	222571	0	0
GntImpliesValid_A	408662289	222571	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	222571	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3022590	0	0
ReadyAndValidImplyGrant_A	408662289	222571	0	0
ReqAndReadyImplyGrant_A	408662289	222571	0	0
ReqImpliesValid_A	408662289	564340	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	222571	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3022590	0	0
T1	238454	44	0	0
T2	6633	1	0	0
T3	7506	99	0	0
T7	293828	106	0	0
T8	52383	504	0	0
T9	3025	49	0	0
T10	79941	1445	0	0
T11	26618	1	0	0
T12	157165	3119	0	0
T13	219229	4692	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	564340	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	102	0	0
T7	293828	31	0	0
T8	52383	83	0	0
T9	3025	50	0	0
T10	79941	270	0	0
T11	26618	0	0	0
T12	157165	4326	0	0
T13	219229	3315	0	0
T14	0	110	0	0
T15	0	555	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	222571	0	0
T1	238454	8	0	0
T2	6633	0	0	0
T3	7506	100	0	0
T7	293828	24	0	0
T8	52383	75	0	0
T9	3025	49	0	0
T10	79941	185	0	0
T11	26618	0	0	0
T12	157165	3713	0	0
T13	219229	789	0	0
T14	0	106	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	220958	0	0
GntImpliesValid_A	408662289	220958	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	220958	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3012391	0	0
ReadyAndValidImplyGrant_A	408662289	220958	0	0
ReqAndReadyImplyGrant_A	408662289	220958	0	0
ReqImpliesValid_A	408662289	554212	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	220958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3012391	0	0
T1	238454	42	0	0
T2	6633	1	0	0
T3	7506	89	0	0
T7	293828	58	0	0
T8	52383	635	0	0
T9	3025	61	0	0
T10	79941	1339	0	0
T11	26618	1	0	0
T12	157165	2157	0	0
T13	219229	4097	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	554212	0	0
T1	238454	19	0	0
T2	6633	0	0	0
T3	7506	106	0	0
T7	293828	15	0	0
T8	52383	122	0	0
T9	3025	64	0	0
T10	79941	275	0	0
T11	26618	0	0	0
T12	157165	2868	0	0
T13	219229	1433	0	0
T14	0	107	0	0
T15	0	443	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	220958	0	0
T1	238454	12	0	0
T2	6633	0	0	0
T3	7506	97	0	0
T7	293828	12	0	0
T8	52383	99	0	0
T9	3025	62	0	0
T10	79941	193	0	0
T11	26618	0	0	0
T12	157165	2503	0	0
T13	219229	697	0	0
T14	0	104	0	0
T15	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	212898	0	0
GntImpliesValid_A	408662289	212898	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	212898	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	2975159	0	0
ReadyAndValidImplyGrant_A	408662289	212898	0	0
ReqAndReadyImplyGrant_A	408662289	212898	0	0
ReqImpliesValid_A	408662289	531994	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	212898	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2975159	0	0
T1	238454	49	0	0
T2	6633	842	0	0
T3	7506	85	0	0
T7	293828	39	0	0
T8	52383	641	0	0
T9	3025	40	0	0
T10	79941	1401	0	0
T11	26618	1	0	0
T12	157165	1922	0	0
T13	219229	5180	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	531994	0	0
T1	238454	13	0	0
T2	6633	3649	0	0
T3	7506	88	0	0
T7	293828	10	0	0
T8	52383	101	0	0
T9	3025	41	0	0
T10	79941	244	0	0
T11	26618	0	0	0
T12	157165	3337	0	0
T13	219229	2134	0	0
T14	0	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	212898	0	0
T1	238454	12	0	0
T2	6633	391	0	0
T3	7506	86	0	0
T7	293828	10	0	0
T8	52383	87	0	0
T9	3025	40	0	0
T10	79941	181	0	0
T11	26618	0	0	0
T12	157165	2620	0	0
T13	219229	756	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	232224	0	0
GntImpliesValid_A	408662289	232224	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	232224	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	3069545	0	0
ReadyAndValidImplyGrant_A	408662289	232224	0	0
ReqAndReadyImplyGrant_A	408662289	232224	0	0
ReqImpliesValid_A	408662289	577007	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	0	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	232224	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	3069545	0	0
T1	238454	55	0	0
T2	6633	1	0	0
T3	7506	79	0	0
T7	293828	70	0	0
T8	52383	764	0	0
T9	3025	40	0	0
T10	79941	1372	0	0
T11	26618	1	0	0
T12	157165	1956	0	0
T13	219229	2354	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	577007	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	88	0	0
T7	293828	18	0	0
T8	52383	104	0	0
T9	3025	47	0	0
T10	79941	308	0	0
T11	26618	0	0	0
T12	157165	3467	0	0
T13	219229	406	0	0
T14	0	123	0	0
T15	0	1330	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	232224	0	0
T1	238454	9	0	0
T2	6633	0	0	0
T3	7506	83	0	0
T7	293828	18	0	0
T8	52383	99	0	0
T9	3025	43	0	0
T10	79941	189	0	0
T11	26618	0	0	0
T12	157165	2702	0	0
T13	219229	292	0	0
T14	0	117	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	890699	0	0
GntImpliesValid_A	408662289	890699	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	890699	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	11125536	0	0
ReadyAndValidImplyGrant_A	408662289	890699	0	0
ReqAndReadyImplyGrant_A	408662289	890699	0	0
ReqImpliesValid_A	408662289	2271990	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	20329	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	890699	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	11125536	0	0
T1	238454	135	0	0
T2	6633	375	0	0
T3	7506	1	0	0
T7	293828	161	0	0
T8	52383	2982	0	0
T9	3025	1	0	0
T10	79941	5045	0	0
T11	26618	1223	0	0
T12	157165	19	0	0
T13	219229	13666	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	2271990	0	0
T1	238454	62	0	0
T2	6633	110	0	0
T3	7506	377	0	0
T7	293828	53	0	0
T8	52383	504	0	0
T9	3025	180	0	0
T10	79941	1301	0	0
T11	26618	329	0	0
T12	157165	10072	0	0
T13	219229	11658	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	20329	0	900
T3	7506	9	0	1
T7	293828	0	0	1
T8	52383	0	0	1
T9	3025	5	0	1
T10	79941	0	0	1
T11	26618	0	0	1
T12	157165	231	0	1
T13	219229	22	0	1
T14	7939	13	0	1
T15	477464	0	0	1
T16	0	17	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	21	0	0
T24	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	890699	0	0
T1	238454	42	0	0
T2	6633	76	0	0
T3	7506	377	0	0
T7	293828	46	0	0
T8	52383	415	0	0
T9	3025	180	0	0
T10	79941	753	0	0
T11	26618	185	0	0
T12	157165	10072	0	0
T13	219229	2830	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408662289	408535344	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408662289	875312	0	0
GntImpliesValid_A	408662289	875312	0	0
GrantKnown_A	408662289	408535344	0	0
IdxKnown_A	408662289	408535344	0	0
IndexIsCorrect_A	408662289	875312	0	0
LockArbDecision_A	408662289	0	0	0
NoReadyValidNoGrant_A	408662289	343320637	0	0
ReadyAndValidImplyGrant_A	408662289	875312	0	0
ReqAndReadyImplyGrant_A	408662289	875312	0	0
ReqImpliesValid_A	408662289	13127284	0	0
ReqStaysHighUntilGranted0_M	408662289	0	0	0
RoundRobin_A	408662289	29342	0	900
ValidKnown_A	408662289	408535344	0	0
gen_data_port_assertion.DataFlow_A	408662289	875312	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	343320637	0	0
T1	238454	198462	0	0
T2	6633	5386	0	0
T3	7506	1	0	0
T7	293828	244734	0	0
T8	52383	44459	0	0
T9	3025	1	0	0
T10	79941	67313	0	0
T11	26618	22977	0	0
T12	157165	1	0	0
T13	219229	180881	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	13127284	0	0
T1	238454	162	0	0
T2	6633	700	0	0
T3	7506	396	0	0
T7	293828	259	0	0
T8	52383	3543	0	0
T9	3025	185	0	0
T10	79941	6054	0	0
T11	26618	1375	0	0
T12	157165	10014	0	0
T13	219229	14051	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	29342	0	900
T3	7506	8	0	1
T7	293828	0	0	1
T8	52383	0	0	1
T9	3025	5	0	1
T10	79941	0	0	1
T11	26618	0	0	1
T12	157165	594	0	1
T13	219229	0	0	1
T14	7939	5	0	1
T15	477464	0	0	1
T16	0	16	0	0
T17	0	61	0	0
T20	0	20	0	0
T21	0	2	0	0
T22	0	580	0	0
T23	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	408535344	0	0
T1	238454	238420	0	0
T2	6633	6617	0	0
T3	7506	7498	0	0
T7	293828	293818	0	0
T8	52383	52344	0	0
T9	3025	3016	0	0
T10	79941	79895	0	0
T11	26618	26607	0	0
T12	157165	155802	0	0
T13	219229	218539	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408662289	875312	0	0
T1	238454	38	0	0
T2	6633	76	0	0
T3	7506	396	0	0
T7	293828	57	0	0
T8	52383	422	0	0
T9	3025	185	0	0
T10	79941	741	0	0
T11	26618	164	0	0
T12	157165	10014	0	0
T13	219229	1819	0	0