Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1492637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236228

1

T1

16

T2

329

T3

174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	587599	1			T1	40		T2	758		T3	385
values[0x0]	553776	1			T1	37		T2	816		T3	412
values[0x1]	587490	1			T1	40		T2	771		T3	418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1153428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

575437

1

T1

38

T2

759

T3

375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25684	1			T1	1		T2	43		T7	70
valid_sources[0x01]	27150	1			T1	1		T2	27		T3	20
valid_sources[0x02]	27866	1			T2	33		T3	16		T7	56
valid_sources[0x03]	27074	1			T1	1		T2	30		T3	19
valid_sources[0x04]	26547	1			T1	11		T2	31		T3	16
valid_sources[0x05]	26156	1			T2	45		T3	19		T7	32
valid_sources[0x06]	26318	1			T2	34		T3	5		T7	20
valid_sources[0x07]	27497	1			T1	2		T2	38		T3	18
valid_sources[0x08]	26646	1			T2	48		T7	12		T8	1
valid_sources[0x09]	26958	1			T2	30		T3	56		T8	2
valid_sources[0x0a]	26781	1			T1	5		T2	48		T3	53
valid_sources[0x0b]	27656	1			T1	2		T2	40		T3	9
valid_sources[0x0c]	27656	1			T1	4		T2	34		T3	28
valid_sources[0x0d]	28086	1			T2	29		T3	17		T7	33
valid_sources[0x0e]	28229	1			T1	1		T2	30		T3	40
valid_sources[0x0f]	27348	1			T2	46		T3	42		T7	7
valid_sources[0x10]	27899	1			T2	39		T3	35		T7	50
valid_sources[0x11]	28316	1			T2	34		T3	17		T7	31
valid_sources[0x12]	27062	1			T2	35		T3	24		T7	66
valid_sources[0x13]	26989	1			T1	1		T2	33		T3	9
valid_sources[0x14]	28400	1			T2	32		T8	1		T9	42
valid_sources[0x15]	26473	1			T2	45		T3	9		T7	17
valid_sources[0x16]	26983	1			T1	2		T2	36		T3	9
valid_sources[0x17]	27317	1			T1	8		T2	35		T7	69
valid_sources[0x18]	26577	1			T1	3		T2	51		T3	18
valid_sources[0x19]	27306	1			T2	36		T7	35		T8	3
valid_sources[0x1a]	26363	1			T2	34		T3	81		T7	23
valid_sources[0x1b]	26796	1			T2	34		T3	31		T7	46
valid_sources[0x1c]	26682	1			T2	27		T7	23		T8	2
valid_sources[0x1d]	26768	1			T1	2		T2	34		T3	15
valid_sources[0x1e]	26097	1			T2	31		T3	15		T7	45
valid_sources[0x1f]	26876	1			T2	41		T3	37		T7	35
valid_sources[0x20]	26558	1			T2	32		T3	47		T7	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24834

1

T1

1

T2

33

T3

16

values[0x0]

all_enables

biggest_size

186371

1

T1

14

T2

259

T3

139

values[0x1]

all_enables

biggest_size

25023

1

T1

1

T2

37

T3

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1499886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243824

1

T1

12

T2

334

T3

163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	598655	1			T1	45		T2	806		T3	401
values[0x0]	548397	1			T1	38		T2	782		T3	426
values[0x1]	596658	1			T1	33		T2	746		T3	416

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

593553

1

T1

39

T2

783

T3

411

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26597	1			T2	21		T7	69		T9	60
valid_sources[0x01]	26910	1			T1	5		T2	28		T3	15
valid_sources[0x02]	27244	1			T1	1		T2	31		T3	20
valid_sources[0x03]	27481	1			T2	49		T3	26		T7	42
valid_sources[0x04]	26737	1			T1	2		T2	31		T3	16
valid_sources[0x05]	27622	1			T2	30		T3	19		T7	22
valid_sources[0x06]	26807	1			T1	3		T2	36		T3	20
valid_sources[0x07]	27647	1			T2	37		T3	8		T7	61
valid_sources[0x08]	27153	1			T1	3		T2	28		T7	9
valid_sources[0x09]	27193	1			T1	1		T2	38		T3	64
valid_sources[0x0a]	27679	1			T2	21		T3	35		T7	53
valid_sources[0x0b]	27458	1			T2	22		T3	6		T7	55
valid_sources[0x0c]	27355	1			T2	56		T3	38		T7	65
valid_sources[0x0d]	27170	1			T1	4		T2	21		T3	8
valid_sources[0x0e]	27016	1			T1	1		T2	25		T3	28
valid_sources[0x0f]	27246	1			T2	39		T3	37		T7	18
valid_sources[0x10]	27912	1			T1	4		T2	16		T3	58
valid_sources[0x11]	27347	1			T1	1		T2	49		T3	23
valid_sources[0x12]	27753	1			T1	3		T2	29		T3	36
valid_sources[0x13]	27371	1			T2	20		T3	6		T7	18
valid_sources[0x14]	27779	1			T1	2		T2	37		T9	69
valid_sources[0x15]	27146	1			T1	1		T2	44		T3	20
valid_sources[0x16]	27169	1			T1	8		T2	39		T3	17
valid_sources[0x17]	27276	1			T1	1		T2	25		T7	67
valid_sources[0x18]	27378	1			T2	29		T3	15		T7	6
valid_sources[0x19]	27353	1			T1	2		T2	25		T7	34
valid_sources[0x1a]	26931	1			T1	4		T2	24		T3	106
valid_sources[0x1b]	27405	1			T1	2		T2	15		T3	27
valid_sources[0x1c]	27180	1			T1	3		T2	72		T7	36
valid_sources[0x1d]	27371	1			T2	35		T3	18		T7	7
valid_sources[0x1e]	27134	1			T1	3		T2	49		T3	26
valid_sources[0x1f]	27435	1			T1	3		T2	34		T3	42
valid_sources[0x20]	26775	1			T2	43		T3	21		T7	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25636

1

T1

2

T2

35

T3

16

values[0x0]

all_enables

biggest_size

192279

1

T1

9

T2

263

T3

133

values[0x1]

all_enables

biggest_size

25909

1

T1

1

T2

36

T3

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1499974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238070

1

T1

14

T2

312

T3

151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	591052	1			T1	39		T2	715		T3	408
values[0x0]	556944	1			T1	42		T2	752		T3	394
values[0x1]	590048	1			T1	38		T2	775		T3	377

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1158615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

579429

1

T1

39

T2

749

T3

391

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25962	1			T1	1		T2	46		T7	40
valid_sources[0x01]	27275	1			T1	4		T2	30		T3	11
valid_sources[0x02]	26783	1			T2	34		T3	28		T7	44
valid_sources[0x03]	27254	1			T1	4		T2	22		T3	22
valid_sources[0x04]	26915	1			T2	19		T3	14		T7	32
valid_sources[0x05]	26455	1			T1	1		T2	37		T3	11
valid_sources[0x06]	27079	1			T1	1		T2	49		T3	11
valid_sources[0x07]	26470	1			T1	2		T2	37		T3	10
valid_sources[0x08]	27613	1			T1	3		T2	18		T7	11
valid_sources[0x09]	27280	1			T1	2		T2	29		T3	40
valid_sources[0x0a]	27355	1			T2	33		T3	44		T7	31
valid_sources[0x0b]	27768	1			T1	1		T2	51		T3	14
valid_sources[0x0c]	27372	1			T2	40		T3	54		T7	66
valid_sources[0x0d]	27703	1			T1	1		T2	32		T3	14
valid_sources[0x0e]	27488	1			T1	1		T2	41		T3	14
valid_sources[0x0f]	26891	1			T1	1		T2	22		T3	32
valid_sources[0x10]	28282	1			T1	2		T2	25		T3	53
valid_sources[0x11]	27003	1			T2	37		T3	25		T7	27
valid_sources[0x12]	27298	1			T1	3		T2	33		T3	30
valid_sources[0x13]	27068	1			T2	31		T3	15		T7	14
valid_sources[0x14]	27165	1			T2	33		T9	46		T11	82
valid_sources[0x15]	26907	1			T1	2		T2	45		T3	12
valid_sources[0x16]	27686	1			T2	30		T3	9		T7	31
valid_sources[0x17]	26660	1			T1	3		T2	50		T7	55
valid_sources[0x18]	27205	1			T2	35		T3	15		T7	16
valid_sources[0x19]	27700	1			T1	1		T2	44		T7	24
valid_sources[0x1a]	26877	1			T1	1		T2	50		T3	85
valid_sources[0x1b]	26511	1			T2	38		T3	30		T7	55
valid_sources[0x1c]	26950	1			T2	42		T7	13		T9	46
valid_sources[0x1d]	27598	1			T1	5		T2	41		T3	5
valid_sources[0x1e]	26989	1			T1	1		T2	17		T3	28
valid_sources[0x1f]	26719	1			T1	5		T2	36		T3	52
valid_sources[0x20]	26646	1			T2	23		T3	48		T7	59

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25035

1

T1

1

T2

31

T3

11

values[0x0]

all_enables

biggest_size

188097

1

T1

13

T2

255

T3

123

values[0x1]

all_enables

biggest_size

24938

1

T2

26

T3

17

T7

24