Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1593755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253823

1

T1

2341

T2

14

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	626736	1			T1	5727		T2	46		T3	61
values[0x0]	592966	1			T1	5569		T2	43		T3	55
values[0x1]	627876	1			T1	5731		T2	27		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1231468	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616110

1

T1

5675

T2

38

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29045	1			T1	247		T2	2		T3	5
valid_sources[0x01]	29991	1			T1	434		T3	1		T7	1
valid_sources[0x02]	30628	1			T1	239		T2	5		T3	4
valid_sources[0x03]	29120	1			T1	302		T2	3		T8	5
valid_sources[0x04]	29386	1			T1	326		T3	4		T8	1
valid_sources[0x05]	28892	1			T1	123		T2	1		T3	1
valid_sources[0x06]	28575	1			T1	152		T2	3		T3	1
valid_sources[0x07]	28348	1			T1	158		T2	1		T3	5
valid_sources[0x08]	28155	1			T1	181		T7	2		T8	2
valid_sources[0x09]	28778	1			T1	186		T2	1		T7	2
valid_sources[0x0a]	29470	1			T1	236		T2	1		T3	3
valid_sources[0x0b]	28586	1			T1	303		T2	3		T3	1
valid_sources[0x0c]	27710	1			T1	152		T2	4		T3	1
valid_sources[0x0d]	28858	1			T1	409		T2	4		T3	2
valid_sources[0x0e]	29691	1			T1	321		T2	1		T3	3
valid_sources[0x0f]	28384	1			T1	245		T2	4		T3	4
valid_sources[0x10]	28495	1			T1	302		T2	4		T3	4
valid_sources[0x11]	28516	1			T1	166		T2	2		T7	1
valid_sources[0x12]	28276	1			T1	197		T3	1		T9	4
valid_sources[0x13]	28333	1			T1	112		T2	1		T3	3
valid_sources[0x14]	29568	1			T1	377		T3	2		T7	2
valid_sources[0x15]	28731	1			T1	246		T2	4		T3	1
valid_sources[0x16]	28743	1			T1	173		T2	1		T3	3
valid_sources[0x17]	29416	1			T1	196		T3	3		T7	1
valid_sources[0x18]	27680	1			T1	219		T2	1		T3	3
valid_sources[0x19]	29395	1			T1	277		T2	3		T3	1
valid_sources[0x1a]	29569	1			T1	142		T2	3		T3	1
valid_sources[0x1b]	27916	1			T1	258		T2	2		T3	3
valid_sources[0x1c]	28318	1			T1	294		T2	1		T3	3
valid_sources[0x1d]	28195	1			T1	207		T2	3		T3	2
valid_sources[0x1e]	28076	1			T1	328		T2	1		T3	2
valid_sources[0x1f]	29389	1			T1	196		T2	1		T3	5
valid_sources[0x20]	28440	1			T1	193		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26651

1

T1

235

T3

3

T7

4

values[0x0]

all_enables

biggest_size

200583

1

T1

1887

T2

13

T3

22

values[0x1]

all_enables

biggest_size

26589

1

T1

219

T2

1

T7

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1610723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262206

1

T1

2433

T2

26

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640407	1			T1	5876		T2	41		T3	45
values[0x0]	591278	1			T1	5596		T2	56		T3	44
values[0x1]	641244	1			T1	5859		T2	45		T3	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1237324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

635605

1

T1

5799

T2

51

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29108	1			T1	232		T2	3		T3	5
valid_sources[0x01]	29852	1			T1	275		T2	3		T3	1
valid_sources[0x02]	29339	1			T1	228		T2	1		T3	2
valid_sources[0x03]	29434	1			T1	267		T2	1		T9	5
valid_sources[0x04]	29081	1			T1	250		T2	6		T10	4
valid_sources[0x05]	30052	1			T1	223		T2	6		T3	3
valid_sources[0x06]	29538	1			T1	282		T2	2		T8	6
valid_sources[0x07]	28742	1			T1	235		T2	3		T3	1
valid_sources[0x08]	28963	1			T1	282		T2	1		T7	7
valid_sources[0x09]	28157	1			T1	226		T2	2		T7	8
valid_sources[0x0a]	29585	1			T1	264		T2	2		T7	1
valid_sources[0x0b]	29290	1			T1	260		T2	1		T8	2
valid_sources[0x0c]	28943	1			T1	305		T2	3		T3	3
valid_sources[0x0d]	29029	1			T1	250		T2	3		T3	2
valid_sources[0x0e]	29097	1			T1	241		T2	2		T7	2
valid_sources[0x0f]	29424	1			T1	281		T3	7		T8	1
valid_sources[0x10]	29462	1			T1	309		T2	2		T7	3
valid_sources[0x11]	28394	1			T1	281		T2	5		T3	10
valid_sources[0x12]	29045	1			T1	269		T2	2		T3	5
valid_sources[0x13]	29130	1			T1	259		T2	4		T10	5
valid_sources[0x14]	29579	1			T1	258		T2	3		T9	11
valid_sources[0x15]	29418	1			T1	244		T2	3		T8	3
valid_sources[0x16]	29306	1			T1	261		T2	1		T8	2
valid_sources[0x17]	28982	1			T1	313		T2	3		T3	1
valid_sources[0x18]	28847	1			T1	269		T2	2		T3	1
valid_sources[0x19]	29730	1			T1	274		T3	1		T9	1
valid_sources[0x1a]	30156	1			T1	301		T2	4		T3	1
valid_sources[0x1b]	29057	1			T1	267		T2	4		T3	6
valid_sources[0x1c]	29205	1			T1	235		T8	4		T9	13
valid_sources[0x1d]	28572	1			T1	280		T7	5		T10	9
valid_sources[0x1e]	29528	1			T1	274		T2	1		T3	1
valid_sources[0x1f]	29371	1			T1	291		T2	3		T3	1
valid_sources[0x20]	29637	1			T1	286		T3	4		T7	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27344

1

T1

212

T2

1

T3

2

values[0x0]

all_enables

biggest_size

207111

1

T1

1957

T2

24

T3

14

values[0x1]

all_enables

biggest_size

27751

1

T1

264

T2

1

T7

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1598308	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254097

1

T1

2429

T2

16

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628011	1			T1	5756		T2	41		T3	38
values[0x0]	594277	1			T1	5631		T2	26		T3	45
values[0x1]	630117	1			T1	5844		T2	35		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1235926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616479

1

T1

5764

T2

36

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28781	1			T1	263		T2	1		T7	3
valid_sources[0x01]	29079	1			T1	304		T3	4		T8	2
valid_sources[0x02]	29208	1			T1	274		T3	4		T7	2
valid_sources[0x03]	29288	1			T1	260		T7	1		T8	3
valid_sources[0x04]	29608	1			T1	246		T3	1		T7	2
valid_sources[0x05]	28976	1			T1	192		T2	3		T3	4
valid_sources[0x06]	29737	1			T1	313		T3	3		T7	3
valid_sources[0x07]	28671	1			T1	282		T3	3		T7	3
valid_sources[0x08]	28222	1			T1	278		T3	1		T7	1
valid_sources[0x09]	29567	1			T1	322		T3	2		T7	4
valid_sources[0x0a]	29214	1			T1	227		T3	3		T7	5
valid_sources[0x0b]	28957	1			T1	208		T2	6		T3	3
valid_sources[0x0c]	28014	1			T1	306		T3	1		T9	1
valid_sources[0x0d]	28269	1			T1	268		T2	5		T3	2
valid_sources[0x0e]	29012	1			T1	221		T3	5		T7	1
valid_sources[0x0f]	28500	1			T1	300		T3	2		T7	1
valid_sources[0x10]	29094	1			T1	278		T3	5		T8	7
valid_sources[0x11]	30131	1			T1	321		T7	3		T8	3
valid_sources[0x12]	29390	1			T1	309		T3	2		T7	5
valid_sources[0x13]	29527	1			T1	200		T7	5		T8	1
valid_sources[0x14]	29041	1			T1	300		T7	9		T8	4
valid_sources[0x15]	28403	1			T1	223		T3	2		T8	2
valid_sources[0x16]	28338	1			T1	251		T2	4		T3	4
valid_sources[0x17]	28866	1			T1	298		T2	4		T3	3
valid_sources[0x18]	28797	1			T1	293		T2	7		T3	1
valid_sources[0x19]	28877	1			T1	305		T3	2		T7	1
valid_sources[0x1a]	29408	1			T1	350		T2	5		T3	3
valid_sources[0x1b]	28852	1			T1	193		T2	3		T3	3
valid_sources[0x1c]	28921	1			T1	203		T2	3		T3	1
valid_sources[0x1d]	28566	1			T1	279		T7	2		T9	3
valid_sources[0x1e]	28825	1			T1	233		T3	1		T7	2
valid_sources[0x1f]	28357	1			T1	259		T7	11		T9	7
valid_sources[0x20]	28753	1			T1	314		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26834

1

T1

228

T2

3

T3

2

values[0x0]

all_enables

biggest_size

200505

1

T1

1951

T2

11

T3

13

values[0x1]

all_enables

biggest_size

26758

1

T1

250

T2

2

T7

3