Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8071540	0	0
GntImpliesValid_A	2147483647	8071540	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8071540	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	482310171	0	0
ReadyAndValidImplyGrant_A	2147483647	8071540	0	0
ReqAndReadyImplyGrant_A	2147483647	8071540	0	0
ReqImpliesValid_A	2147483647	34665788	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	55887	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8071540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13981536	13976472	0	0
T2	42600	41808	0	0
T3	216936	216024	0	0
T7	11540088	11538360	0	0
T8	309360	308160	0	0
T9	235320	234816	0	0
T10	11969712	11969040	0	0
T11	5867784	5865456	0	0
T12	2450280	2449992	0	0
T13	6821304	6787296	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13981536	13976472	0	0
T2	42600	41808	0	0
T3	216936	216024	0	0
T7	11540088	11538360	0	0
T8	309360	308160	0	0
T9	235320	234816	0	0
T10	11969712	11969040	0	0
T11	5867784	5865456	0	0
T12	2450280	2449992	0	0
T13	6821304	6787296	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13981536	13976472	0	0
T2	42600	41808	0	0
T3	216936	216024	0	0
T7	11540088	11538360	0	0
T8	309360	308160	0	0
T9	235320	234816	0	0
T10	11969712	11969040	0	0
T11	5867784	5865456	0	0
T12	2450280	2449992	0	0
T13	6821304	6787296	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482310171	0	0
T1	13981536	816867	0	0
T2	42600	482	0	0
T3	216936	10506	0	0
T7	11540088	625469	0	0
T8	309360	15154	0	0
T9	235320	11380	0	0
T10	11969712	421786	0	0
T11	5867784	338979	0	0
T12	2450280	97532	0	0
T13	6821304	391862	0	0
T14	0	10308	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34665788	0	0
T1	13981536	141460	0	0
T2	42600	401	0	0
T3	216936	894	0	0
T7	11540088	25288	0	0
T8	309360	937	0	0
T9	235320	1030	0	0
T10	11969712	2891	0	0
T11	5867784	47950	0	0
T12	2450280	70253	0	0
T13	6821304	114582	0	0
T14	0	17712	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55887	0	21600
T1	582564	164	0	1
T2	1775	0	0	1
T3	9039	0	0	1
T7	480837	0	0	1
T8	12890	0	0	1
T9	9805	0	0	1
T10	498738	0	0	1
T11	488982	2	0	2
T12	204190	65	0	2
T13	568442	99	0	2
T14	71982	879	0	1
T15	99590	166	0	1
T16	27753	1	0	1
T17	0	2	0	0
T18	0	143	0	0
T19	0	30	0	0
T20	0	54	0	0
T21	0	11	0	0
T22	0	1	0	0
T23	16886	0	0	1
T24	114967	0	0	1
T25	33116	0	0	1
T26	5438	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13981536	13976472	0	0
T2	42600	41808	0	0
T3	216936	216024	0	0
T7	11540088	11538360	0	0
T8	309360	308160	0	0
T9	235320	234816	0	0
T10	11969712	11969040	0	0
T11	5867784	5865456	0	0
T12	2450280	2449992	0	0
T13	6821304	6787296	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8071540	0	0
T1	13981536	46812	0	0
T2	42600	360	0	0
T3	216936	418	0	0
T7	11540088	434	0	0
T8	309360	494	0	0
T9	235320	451	0	0
T10	11969712	1686	0	0
T11	5867784	20248	0	0
T12	2450280	9628	0	0
T13	6821304	20175	0	0
T14	0	10700	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	894651	0	0
GntImpliesValid_A	446823022	894651	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	894651	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	12369114	0	0
ReadyAndValidImplyGrant_A	446823022	894651	0	0
ReqAndReadyImplyGrant_A	446823022	894651	0	0
ReqImpliesValid_A	446823022	2539731	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	894651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	12369114	0	0
T1	582564	32588	0	0
T2	1775	45	0	0
T3	9039	299	0	0
T7	480837	20305	0	0
T8	12890	513	0	0
T9	9805	412	0	0
T10	498738	826	0	0
T11	244491	16040	0	0
T12	102095	3923	0	0
T13	284221	15485	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	2539731	0	0
T1	582564	6877	0	0
T2	1775	64	0	0
T3	9039	58	0	0
T7	480837	2578	0	0
T8	12890	104	0	0
T9	9805	99	0	0
T10	498738	278	0	0
T11	244491	3461	0	0
T12	102095	8169	0	0
T13	284221	5011	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	894651	0	0
T1	582564	4346	0	0
T2	1775	54	0	0
T3	9039	43	0	0
T7	480837	56	0	0
T8	12890	61	0	0
T9	9805	65	0	0
T10	498738	196	0	0
T11	244491	2253	0	0
T12	102095	1153	0	0
T13	284221	2573	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	904508	0	0
GntImpliesValid_A	446823022	904508	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	904508	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	12126318	0	0
ReadyAndValidImplyGrant_A	446823022	904508	0	0
ReqAndReadyImplyGrant_A	446823022	904508	0	0
ReqImpliesValid_A	446823022	2475099	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	904508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	12126318	0	0
T1	582564	38547	0	0
T2	1775	22	0	0
T3	9039	366	0	0
T7	480837	15103	0	0
T8	12890	423	0	0
T9	9805	362	0	0
T10	498738	714	0	0
T11	244491	16481	0	0
T12	102095	4357	0	0
T13	284221	13520	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	2475099	0	0
T1	582564	17720	0	0
T2	1775	35	0	0
T3	9039	61	0	0
T7	480837	1647	0	0
T8	12890	79	0	0
T9	9805	54	0	0
T10	498738	245	0	0
T11	244491	3356	0	0
T12	102095	8300	0	0
T13	284221	3179	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	904508	0	0
T1	582564	5898	0	0
T2	1775	28	0	0
T3	9039	45	0	0
T7	480837	49	0	0
T8	12890	48	0	0
T9	9805	50	0	0
T10	498738	182	0	0
T11	244491	2324	0	0
T12	102095	1203	0	0
T13	284221	1945	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	222162	0	0
GntImpliesValid_A	446823022	222162	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	222162	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3072620	0	0
ReadyAndValidImplyGrant_A	446823022	222162	0	0
ReqAndReadyImplyGrant_A	446823022	222162	0	0
ReqImpliesValid_A	446823022	562999	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	222162	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3072620	0	0
T1	582564	6541	0	0
T2	1775	8	0	0
T3	9039	97	0	0
T7	480837	3380	0	0
T8	12890	52	0	0
T9	9805	87	0	0
T10	498738	178	0	0
T11	244491	3269	0	0
T12	102095	1	0	0
T13	284221	5831	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	562999	0	0
T1	582564	957	0	0
T2	1775	7	0	0
T3	9039	14	0	0
T7	480837	795	0	0
T8	12890	8	0	0
T9	9805	28	0	0
T10	498738	47	0	0
T11	244491	541	0	0
T12	102095	0	0	0
T13	284221	1633	0	0
T14	0	1350	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222162	0	0
T1	582564	833	0	0
T2	1775	7	0	0
T3	9039	13	0	0
T7	480837	9	0	0
T8	12890	8	0	0
T9	9805	13	0	0
T10	498738	41	0	0
T11	244491	451	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	893	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	219625	0	0
GntImpliesValid_A	446823022	219625	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	219625	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3096531	0	0
ReadyAndValidImplyGrant_A	446823022	219625	0	0
ReqAndReadyImplyGrant_A	446823022	219625	0	0
ReqImpliesValid_A	446823022	537373	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	219625	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3096531	0	0
T1	582564	6006	0	0
T2	1775	11	0	0
T3	9039	130	0	0
T7	480837	4900	0	0
T8	12890	127	0	0
T9	9805	97	0	0
T10	498738	208	0	0
T11	244491	3083	0	0
T12	102095	1033	0	0
T13	284221	1967	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	537373	0	0
T1	582564	945	0	0
T2	1775	10	0	0
T3	9039	17	0	0
T7	480837	171	0	0
T8	12890	26	0	0
T9	9805	11	0	0
T10	498738	71	0	0
T11	244491	547	0	0
T12	102095	4468	0	0
T13	284221	310	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	219625	0	0
T1	582564	797	0	0
T2	1775	10	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	20	0	0
T9	9805	11	0	0
T10	498738	52	0	0
T11	244491	430	0	0
T12	102095	512	0	0
T13	284221	267	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	229536	0	0
GntImpliesValid_A	446823022	229536	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	229536	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	4903643	0	0
ReadyAndValidImplyGrant_A	446823022	229536	0	0
ReqAndReadyImplyGrant_A	446823022	229536	0	0
ReqImpliesValid_A	446823022	1263280	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	229536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	4903643	0	0
T1	582564	26984	0	0
T2	1775	101	0	0
T3	9039	75	0	0
T7	480837	11157	0	0
T8	12890	251	0	0
T9	9805	84	0	0
T10	498738	253	0	0
T11	244491	3989	0	0
T12	102095	0	0	0
T13	284221	33113	0	0
T14	0	3142	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	1263280	0	0
T1	582564	7387	0	0
T2	1775	18	0	0
T3	9039	14	0	0
T7	480837	7	0	0
T8	12890	36	0	0
T9	9805	28	0	0
T10	498738	46	0	0
T11	244491	483	0	0
T12	102095	0	0	0
T13	284221	41042	0	0
T14	0	549	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229536	0	0
T1	582564	1344	0	0
T2	1775	12	0	0
T3	9039	12	0	0
T7	480837	7	0	0
T8	12890	18	0	0
T9	9805	18	0	0
T10	498738	39	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	1253	0	0
T14	0	408	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	210557	0	0
GntImpliesValid_A	446823022	210557	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	210557	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	5357284	0	0
ReadyAndValidImplyGrant_A	446823022	210557	0	0
ReqAndReadyImplyGrant_A	446823022	210557	0	0
ReqImpliesValid_A	446823022	1139388	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	210557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	5357284	0	0
T1	582564	19777	0	0
T2	1775	43	0	0
T3	9039	89	0	0
T7	480837	6242	0	0
T8	12890	224	0	0
T9	9805	121	0	0
T10	498738	376	0	0
T11	244491	5068	0	0
T12	102095	0	0	0
T13	284221	7424	0	0
T14	0	3311	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	1139388	0	0
T1	582564	9076	0	0
T2	1775	4	0	0
T3	9039	23	0	0
T7	480837	12	0	0
T8	12890	23	0	0
T9	9805	8	0	0
T10	498738	87	0	0
T11	244491	622	0	0
T12	102095	0	0	0
T13	284221	777	0	0
T14	0	5717	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	210557	0	0
T1	582564	2256	0	0
T2	1775	4	0	0
T3	9039	13	0	0
T7	480837	12	0	0
T8	12890	13	0	0
T9	9805	8	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	1426	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	212280	0	0
GntImpliesValid_A	446823022	212280	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	212280	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	5960179	0	0
ReadyAndValidImplyGrant_A	446823022	212280	0	0
ReqAndReadyImplyGrant_A	446823022	212280	0	0
ReqImpliesValid_A	446823022	1223054	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	212280	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	5960179	0	0
T1	582564	13760	0	0
T2	1775	71	0	0
T3	9039	104	0	0
T7	480837	21550	0	0
T8	12890	264	0	0
T9	9805	64	0	0
T10	498738	312	0	0
T11	244491	4328	0	0
T12	102095	0	0	0
T13	284221	8779	0	0
T14	0	3855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	1223054	0	0
T1	582564	1277	0	0
T2	1775	24	0	0
T3	9039	16	0	0
T7	480837	645	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	551	0	0
T12	102095	0	0	0
T13	284221	8283	0	0
T14	0	683	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	212280	0	0
T1	582564	830	0	0
T2	1775	14	0	0
T3	9039	10	0	0
T7	480837	14	0	0
T8	12890	19	0	0
T9	9805	12	0	0
T10	498738	44	0	0
T11	244491	462	0	0
T12	102095	0	0	0
T13	284221	1195	0	0
T14	0	421	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	223633	0	0
GntImpliesValid_A	446823022	223633	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	223633	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	5743009	0	0
ReadyAndValidImplyGrant_A	446823022	223633	0	0
ReqAndReadyImplyGrant_A	446823022	223633	0	0
ReqImpliesValid_A	446823022	1317295	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	223633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	5743009	0	0
T1	582564	27612	0	0
T2	1775	40	0	0
T3	9039	135	0	0
T7	480837	6707	0	0
T8	12890	192	0	0
T9	9805	128	0	0
T10	498738	417	0	0
T11	244491	5338	0	0
T12	102095	2594	0	0
T13	284221	20465	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	1317295	0	0
T1	582564	6483	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	724	0	0
T8	12890	14	0	0
T9	9805	26	0	0
T10	498738	94	0	0
T11	244491	546	0	0
T12	102095	3768	0	0
T13	284221	18665	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223633	0	0
T1	582564	1253	0	0
T2	1775	7	0	0
T3	9039	16	0	0
T7	480837	12	0	0
T8	12890	14	0	0
T9	9805	18	0	0
T10	498738	54	0	0
T11	244491	488	0	0
T12	102095	1001	0	0
T13	284221	1046	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	223510	0	0
GntImpliesValid_A	446823022	223510	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	223510	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3114899	0	0
ReadyAndValidImplyGrant_A	446823022	223510	0	0
ReqAndReadyImplyGrant_A	446823022	223510	0	0
ReqImpliesValid_A	446823022	540577	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	223510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3114899	0	0
T1	582564	7875	0	0
T2	1775	7	0	0
T3	9039	63	0	0
T7	480837	3692	0	0
T8	12890	222	0	0
T9	9805	130	0	0
T10	498738	181	0	0
T11	244491	3528	0	0
T12	102095	1	0	0
T13	284221	2234	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	540577	0	0
T1	582564	1830	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	913	0	0
T8	12890	47	0	0
T9	9805	12	0	0
T10	498738	53	0	0
T11	244491	501	0	0
T12	102095	0	0	0
T13	284221	323	0	0
T14	0	1384	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	223510	0	0
T1	582564	1208	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	12	0	0
T8	12890	22	0	0
T9	9805	12	0	0
T10	498738	43	0	0
T11	244491	448	0	0
T12	102095	0	0	0
T13	284221	290	0	0
T14	0	913	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	216491	0	0
GntImpliesValid_A	446823022	216491	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	216491	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3028065	0	0
ReadyAndValidImplyGrant_A	446823022	216491	0	0
ReqAndReadyImplyGrant_A	446823022	216491	0	0
ReqImpliesValid_A	446823022	542650	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	216491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3028065	0	0
T1	582564	6069	0	0
T2	1775	11	0	0
T3	9039	65	0	0
T7	480837	3153	0	0
T8	12890	174	0	0
T9	9805	95	0	0
T10	498738	159	0	0
T11	244491	3666	0	0
T12	102095	1	0	0
T13	284221	2181	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	542650	0	0
T1	582564	914	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	46	0	0
T11	244491	576	0	0
T12	102095	0	0	0
T13	284221	391	0	0
T14	0	1823	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216491	0	0
T1	582564	821	0	0
T2	1775	10	0	0
T3	9039	7	0	0
T7	480837	9	0	0
T8	12890	19	0	0
T9	9805	10	0	0
T10	498738	40	0	0
T11	244491	486	0	0
T12	102095	0	0	0
T13	284221	292	0	0
T14	0	1404	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	226174	0	0
GntImpliesValid_A	446823022	226174	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	226174	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3097177	0	0
ReadyAndValidImplyGrant_A	446823022	226174	0	0
ReqAndReadyImplyGrant_A	446823022	226174	0	0
ReqImpliesValid_A	446823022	553064	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	226174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3097177	0	0
T1	582564	7369	0	0
T2	1775	9	0	0
T3	9039	88	0	0
T7	480837	4387	0	0
T8	12890	94	0	0
T9	9805	33	0	0
T10	498738	175	0	0
T11	244491	3543	0	0
T12	102095	1	0	0
T13	284221	2176	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	553064	0	0
T1	582564	5247	0	0
T2	1775	10	0	0
T3	9039	22	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	62	0	0
T11	244491	520	0	0
T12	102095	0	0	0
T13	284221	315	0	0
T14	0	488	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	226174	0	0
T1	582564	1313	0	0
T2	1775	9	0	0
T3	9039	11	0	0
T7	480837	14	0	0
T8	12890	12	0	0
T9	9805	6	0	0
T10	498738	44	0	0
T11	244491	447	0	0
T12	102095	0	0	0
T13	284221	270	0	0
T14	0	474	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	225130	0	0
GntImpliesValid_A	446823022	225130	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	225130	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3044489	0	0
ReadyAndValidImplyGrant_A	446823022	225130	0	0
ReqAndReadyImplyGrant_A	446823022	225130	0	0
ReqImpliesValid_A	446823022	551325	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	225130	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3044489	0	0
T1	582564	9502	0	0
T2	1775	7	0	0
T3	9039	152	0	0
T7	480837	4659	0	0
T8	12890	69	0	0
T9	9805	47	0	0
T10	498738	208	0	0
T11	244491	3286	0	0
T12	102095	1	0	0
T13	284221	2003	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	551325	0	0
T1	582564	3759	0	0
T2	1775	8	0	0
T3	9039	20	0	0
T7	480837	964	0	0
T8	12890	14	0	0
T9	9805	7	0	0
T10	498738	73	0	0
T11	244491	506	0	0
T12	102095	0	0	0
T13	284221	352	0	0
T14	0	442	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225130	0	0
T1	582564	1715	0	0
T2	1775	7	0	0
T3	9039	19	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	7	0	0
T10	498738	53	0	0
T11	244491	455	0	0
T12	102095	0	0	0
T13	284221	274	0	0
T14	0	433	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	217660	0	0
GntImpliesValid_A	446823022	217660	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	217660	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3102720	0	0
ReadyAndValidImplyGrant_A	446823022	217660	0	0
ReqAndReadyImplyGrant_A	446823022	217660	0	0
ReqImpliesValid_A	446823022	539051	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	217660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3102720	0	0
T1	582564	8951	0	0
T2	1775	15	0	0
T3	9039	64	0	0
T7	480837	2614	0	0
T8	12890	107	0	0
T9	9805	47	0	0
T10	498738	245	0	0
T11	244491	3300	0	0
T12	102095	1	0	0
T13	284221	2138	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	539051	0	0
T1	582564	2072	0	0
T2	1775	20	0	0
T3	9039	12	0	0
T7	480837	280	0	0
T8	12890	13	0	0
T9	9805	19	0	0
T10	498738	72	0	0
T11	244491	509	0	0
T12	102095	0	0	0
T13	284221	352	0	0
T14	0	1158	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	217660	0	0
T1	582564	1306	0	0
T2	1775	17	0	0
T3	9039	12	0	0
T7	480837	13	0	0
T8	12890	13	0	0
T9	9805	6	0	0
T10	498738	59	0	0
T11	244491	446	0	0
T12	102095	0	0	0
T13	284221	299	0	0
T14	0	928	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	233205	0	0
GntImpliesValid_A	446823022	233205	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	233205	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3080006	0	0
ReadyAndValidImplyGrant_A	446823022	233205	0	0
ReqAndReadyImplyGrant_A	446823022	233205	0	0
ReqImpliesValid_A	446823022	576722	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	233205	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3080006	0	0
T1	582564	6236	0	0
T2	1775	5	0	0
T3	9039	107	0	0
T7	480837	3884	0	0
T8	12890	126	0	0
T9	9805	170	0	0
T10	498738	258	0	0
T11	244491	3656	0	0
T12	102095	1432	0	0
T13	284221	2059	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	576722	0	0
T1	582564	993	0	0
T2	1775	8	0	0
T3	9039	17	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	41	0	0
T10	498738	67	0	0
T11	244491	637	0	0
T12	102095	1989	0	0
T13	284221	290	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	233205	0	0
T1	582564	824	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	9	0	0
T8	12890	18	0	0
T9	9805	19	0	0
T10	498738	60	0	0
T11	244491	477	0	0
T12	102095	555	0	0
T13	284221	272	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	225791	0	0
GntImpliesValid_A	446823022	225791	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	225791	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3104195	0	0
ReadyAndValidImplyGrant_A	446823022	225791	0	0
ReqAndReadyImplyGrant_A	446823022	225791	0	0
ReqImpliesValid_A	446823022	588708	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	225791	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3104195	0	0
T1	582564	7050	0	0
T2	1775	11	0	0
T3	9039	61	0	0
T7	480837	4549	0	0
T8	12890	127	0	0
T9	9805	48	0	0
T10	498738	178	0	0
T11	244491	3579	0	0
T12	102095	1	0	0
T13	284221	2348	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	588708	0	0
T1	582564	2485	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	16	0	0
T10	498738	67	0	0
T11	244491	513	0	0
T12	102095	0	0	0
T13	284221	375	0	0
T14	0	463	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	225791	0	0
T1	582564	1261	0	0
T2	1775	10	0	0
T3	9039	13	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	9	0	0
T10	498738	47	0	0
T11	244491	465	0	0
T12	102095	0	0	0
T13	284221	296	0	0
T14	0	455	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	220867	0	0
GntImpliesValid_A	446823022	220867	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	220867	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3101566	0	0
ReadyAndValidImplyGrant_A	446823022	220867	0	0
ReqAndReadyImplyGrant_A	446823022	220867	0	0
ReqImpliesValid_A	446823022	559075	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	220867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3101566	0	0
T1	582564	9974	0	0
T2	1775	13	0	0
T3	9039	85	0	0
T7	480837	2257	0	0
T8	12890	86	0	0
T9	9805	84	0	0
T10	498738	181	0	0
T11	244491	4533	0	0
T12	102095	1143	0	0
T13	284221	4668	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	559075	0	0
T1	582564	8053	0	0
T2	1775	12	0	0
T3	9039	30	0	0
T7	480837	10	0	0
T8	12890	20	0	0
T9	9805	9	0	0
T10	498738	48	0	0
T11	244491	4324	0	0
T12	102095	1767	0	0
T13	284221	1583	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	220867	0	0
T1	582564	1818	0	0
T2	1775	12	0	0
T3	9039	14	0	0
T7	480837	10	0	0
T8	12890	14	0	0
T9	9805	9	0	0
T10	498738	42	0	0
T11	244491	902	0	0
T12	102095	481	0	0
T13	284221	771	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	246924	0	0
GntImpliesValid_A	446823022	246924	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	246924	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3176382	0	0
ReadyAndValidImplyGrant_A	446823022	246924	0	0
ReqAndReadyImplyGrant_A	446823022	246924	0	0
ReqImpliesValid_A	446823022	601801	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	246924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3176382	0	0
T1	582564	10711	0	0
T2	1775	11	0	0
T3	9039	82	0	0
T7	480837	5663	0	0
T8	12890	70	0	0
T9	9805	90	0	0
T10	498738	246	0	0
T11	244491	3795	0	0
T12	102095	1	0	0
T13	284221	3505	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	601801	0	0
T1	582564	7439	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	717	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	80	0	0
T11	244491	603	0	0
T12	102095	0	0	0
T13	284221	2259	0	0
T14	0	520	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	246924	0	0
T1	582564	1838	0	0
T2	1775	10	0	0
T3	9039	8	0	0
T7	480837	19	0	0
T8	12890	11	0	0
T9	9805	13	0	0
T10	498738	63	0	0
T11	244491	525	0	0
T12	102095	0	0	0
T13	284221	816	0	0
T14	0	500	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	230257	0	0
GntImpliesValid_A	446823022	230257	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	230257	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3151719	0	0
ReadyAndValidImplyGrant_A	446823022	230257	0	0
ReqAndReadyImplyGrant_A	446823022	230257	0	0
ReqImpliesValid_A	446823022	581463	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	230257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3151719	0	0
T1	582564	6330	0	0
T2	1775	12	0	0
T3	9039	92	0	0
T7	480837	4861	0	0
T8	12890	77	0	0
T9	9805	71	0	0
T10	498738	228	0	0
T11	244491	6163	0	0
T12	102095	1032	0	0
T13	284221	2247	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	581463	0	0
T1	582564	1023	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	18	0	0
T10	498738	56	0	0
T11	244491	2380	0	0
T12	102095	4372	0	0
T13	284221	368	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	230257	0	0
T1	582564	866	0	0
T2	1775	11	0	0
T3	9039	11	0	0
T7	480837	12	0	0
T8	12890	12	0	0
T9	9805	9	0	0
T10	498738	44	0	0
T11	244491	923	0	0
T12	102095	482	0	0
T13	284221	298	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	216650	0	0
GntImpliesValid_A	446823022	216650	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	216650	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3046645	0	0
ReadyAndValidImplyGrant_A	446823022	216650	0	0
ReqAndReadyImplyGrant_A	446823022	216650	0	0
ReqImpliesValid_A	446823022	543268	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	216650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3046645	0	0
T1	582564	5795	0	0
T2	1775	10	0	0
T3	9039	144	0	0
T7	480837	3531	0	0
T8	12890	51	0	0
T9	9805	79	0	0
T10	498738	209	0	0
T11	244491	3580	0	0
T12	102095	1	0	0
T13	284221	2640	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	543268	0	0
T1	582564	995	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	359	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	59	0	0
T11	244491	622	0	0
T12	102095	0	0	0
T13	284221	5280	0	0
T14	0	1554	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	216650	0	0
T1	582564	803	0	0
T2	1775	9	0	0
T3	9039	18	0	0
T7	480837	13	0	0
T8	12890	6	0	0
T9	9805	10	0	0
T10	498738	49	0	0
T11	244491	499	0	0
T12	102095	0	0	0
T13	284221	793	0	0
T14	0	1096	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	229823	0	0
GntImpliesValid_A	446823022	229823	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	229823	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3055032	0	0
ReadyAndValidImplyGrant_A	446823022	229823	0	0
ReqAndReadyImplyGrant_A	446823022	229823	0	0
ReqImpliesValid_A	446823022	603784	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	229823	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3055032	0	0
T1	582564	6600	0	0
T2	1775	12	0	0
T3	9039	82	0	0
T7	480837	3626	0	0
T8	12890	153	0	0
T9	9805	94	0	0
T10	498738	178	0	0
T11	244491	6746	0	0
T12	102095	724	0	0
T13	284221	2178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	603784	0	0
T1	582564	2594	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	20	0	0
T9	9805	20	0	0
T10	498738	56	0	0
T11	244491	3300	0	0
T12	102095	4791	0	0
T13	284221	341	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	229823	0	0
T1	582564	1198	0	0
T2	1775	11	0	0
T3	9039	8	0	0
T7	480837	10	0	0
T8	12890	15	0	0
T9	9805	14	0	0
T10	498738	47	0	0
T11	244491	1024	0	0
T12	102095	480	0	0
T13	284221	284	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	228218	0	0
GntImpliesValid_A	446823022	228218	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	228218	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3084164	0	0
ReadyAndValidImplyGrant_A	446823022	228218	0	0
ReqAndReadyImplyGrant_A	446823022	228218	0	0
ReqImpliesValid_A	446823022	568887	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	228218	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3084164	0	0
T1	582564	8773	0	0
T2	1775	7	0	0
T3	9039	87	0	0
T7	480837	1913	0	0
T8	12890	101	0	0
T9	9805	109	0	0
T10	498738	169	0	0
T11	244491	3700	0	0
T12	102095	1	0	0
T13	284221	4904	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	568887	0	0
T1	582564	2188	0	0
T2	1775	6	0	0
T3	9039	12	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	38	0	0
T11	244491	611	0	0
T12	102095	0	0	0
T13	284221	1433	0	0
T14	0	404	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	228218	0	0
T1	582564	1328	0	0
T2	1775	6	0	0
T3	9039	11	0	0
T7	480837	10	0	0
T8	12890	12	0	0
T9	9805	11	0	0
T10	498738	37	0	0
T11	244491	479	0	0
T12	102095	0	0	0
T13	284221	779	0	0
T14	0	399	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	222064	0	0
GntImpliesValid_A	446823022	222064	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	222064	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	3083293	0	0
ReadyAndValidImplyGrant_A	446823022	222064	0	0
ReqAndReadyImplyGrant_A	446823022	222064	0	0
ReqImpliesValid_A	446823022	523093	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	0	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	222064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	3083293	0	0
T1	582564	8987	0	0
T2	1775	9	0	0
T3	9039	96	0	0
T7	480837	4527	0	0
T8	12890	105	0	0
T9	9805	49	0	0
T10	498738	228	0	0
T11	244491	6884	0	0
T12	102095	1	0	0
T13	284221	3028	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	523093	0	0
T1	582564	1948	0	0
T2	1775	10	0	0
T3	9039	12	0	0
T7	480837	85	0	0
T8	12890	15	0	0
T9	9805	8	0	0
T10	498738	65	0	0
T11	244491	1448	0	0
T12	102095	0	0	0
T13	284221	545	0	0
T14	0	1177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	222064	0	0
T1	582564	1224	0	0
T2	1775	9	0	0
T3	9039	12	0	0
T7	480837	11	0	0
T8	12890	15	0	0
T9	9805	7	0	0
T10	498738	51	0	0
T11	244491	912	0	0
T12	102095	0	0	0
T13	284221	400	0	0
T14	0	950	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	900762	0	0
GntImpliesValid_A	446823022	900762	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	900762	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	11477074	0	0
ReadyAndValidImplyGrant_A	446823022	900762	0	0
ReqAndReadyImplyGrant_A	446823022	900762	0	0
ReqImpliesValid_A	446823022	2295837	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	21520	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	900762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	11477074	0	0
T1	582564	34962	0	0
T2	1775	1	0	0
T3	9039	271	0	0
T7	480837	17242	0	0
T8	12890	260	0	0
T9	9805	394	0	0
T10	498738	546	0	0
T11	244491	14879	0	0
T12	102095	5081	0	0
T13	284221	12001	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	2295837	0	0
T1	582564	15450	0	0
T2	1775	51	0	0
T3	9039	42	0	0
T7	480837	1024	0	0
T8	12890	59	0	0
T9	9805	114	0	0
T10	498738	205	0	0
T11	244491	3005	0	0
T12	102095	14199	0	0
T13	284221	3387	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	21520	0	900
T1	582564	164	0	1
T2	1775	0	0	1
T3	9039	0	0	1
T7	480837	0	0	1
T8	12890	0	0	1
T9	9805	0	0	1
T10	498738	0	0	1
T11	244491	1	0	1
T12	102095	27	0	1
T13	284221	2	0	1
T14	0	492	0	0
T15	0	95	0	0
T18	0	141	0	0
T19	0	30	0	0
T21	0	4	0	0
T22	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	900762	0	0
T1	582564	7462	0	0
T2	1775	51	0	0
T3	9039	39	0	0
T7	480837	49	0	0
T8	12890	46	0	0
T9	9805	59	0	0
T10	498738	153	0	0
T11	244491	2235	0	0
T12	102095	1917	0	0
T13	284221	2074	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	446823022	446694267	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	446823022	891062	0	0
GntImpliesValid_A	446823022	891062	0	0
GrantKnown_A	446823022	446694267	0	0
IdxKnown_A	446823022	446694267	0	0
IndexIsCorrect_A	446823022	891062	0	0
LockArbDecision_A	446823022	0	0	0
NoReadyValidNoGrant_A	446823022	374934047	0	0
ReadyAndValidImplyGrant_A	446823022	891062	0	0
ReqAndReadyImplyGrant_A	446823022	891062	0	0
ReqImpliesValid_A	446823022	13438264	0	0
ReqStaysHighUntilGranted0_M	446823022	0	0	0
RoundRobin_A	446823022	34367	0	900
ValidKnown_A	446823022	446694267	0	0
gen_data_port_assertion.DataFlow_A	446823022	891062	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	374934047	0	0
T1	582564	499868	0	0
T2	1775	1	0	0
T3	9039	7672	0	0
T7	480837	465567	0	0
T8	12890	11286	0	0
T9	9805	8485	0	0
T10	498738	415113	0	0
T11	244491	206545	0	0
T12	102095	76202	0	0
T13	284221	234968	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	13438264	0	0
T1	582564	33748	0	0
T2	1775	40	0	0
T3	9039	431	0	0
T7	480837	14282	0	0
T8	12890	332	0	0
T9	9805	450	0	0
T10	498738	932	0	0
T11	244491	17788	0	0
T12	102095	18430	0	0
T13	284221	18088	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	34367	0	900
T11	244491	1	0	1
T12	102095	38	0	1
T13	284221	97	0	1
T14	71982	387	0	1
T15	99590	71	0	1
T16	27753	1	0	1
T17	0	2	0	0
T18	0	2	0	0
T20	0	54	0	0
T21	0	7	0	0
T23	16886	0	0	1
T24	114967	0	0	1
T25	33116	0	0	1
T26	5438	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	446694267	0	0
T1	582564	582353	0	0
T2	1775	1742	0	0
T3	9039	9001	0	0
T7	480837	480765	0	0
T8	12890	12840	0	0
T9	9805	9784	0	0
T10	498738	498710	0	0
T11	244491	244394	0	0
T12	102095	102083	0	0
T13	284221	282804	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446823022	891062	0	0
T1	582564	4270	0	0
T2	1775	40	0	0
T3	9039	48	0	0
T7	480837	48	0	0
T8	12890	50	0	0
T9	9805	55	0	0
T10	498738	199	0	0
T11	244491	2206	0	0
T12	102095	1844	0	0
T13	284221	2610	0	0