Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1457845 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 230756 1 T1 54 T2 78 T3 18


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 573281 1 T1 131 T2 171 T3 52
values[0x0] 541917 1 T1 119 T2 171 T3 12
values[0x1] 573403 1 T1 135 T2 186 T3 72


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1127467 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 561134 1 T1 145 T2 174 T3 51


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26198 1 T2 6 T3 3 T7 2
valid_sources[0x01] 26259 1 T1 6 T2 6 T3 1
valid_sources[0x02] 26419 1 T2 11 T3 1 T8 133
valid_sources[0x03] 26256 1 T1 8 T2 6 T3 2
valid_sources[0x04] 27543 1 T2 19 T3 3 T7 7
valid_sources[0x05] 25672 1 T2 6 T3 3 T8 288
valid_sources[0x06] 27399 1 T1 10 T2 13 T8 118
valid_sources[0x07] 26338 1 T2 5 T3 2 T7 1
valid_sources[0x08] 25844 1 T1 15 T2 12 T7 5
valid_sources[0x09] 25572 1 T1 6 T2 5 T3 5
valid_sources[0x0a] 25169 1 T2 8 T8 127 T9 24
valid_sources[0x0b] 25547 1 T2 5 T3 4 T7 9
valid_sources[0x0c] 25865 1 T2 9 T3 6 T7 3
valid_sources[0x0d] 26372 1 T2 7 T3 4 T8 168
valid_sources[0x0e] 25519 1 T1 20 T2 4 T3 3
valid_sources[0x0f] 25675 1 T2 12 T7 4 T8 115
valid_sources[0x10] 26602 1 T1 6 T2 5 T3 2
valid_sources[0x11] 26543 1 T1 17 T2 5 T3 2
valid_sources[0x12] 27078 1 T2 9 T3 2 T8 176
valid_sources[0x13] 26162 1 T2 7 T7 3 T8 139
valid_sources[0x14] 26494 1 T2 12 T3 2 T7 7
valid_sources[0x15] 26910 1 T1 32 T2 11 T3 1
valid_sources[0x16] 26442 1 T2 8 T7 10 T8 176
valid_sources[0x17] 26228 1 T1 18 T2 8 T3 1
valid_sources[0x18] 26262 1 T2 6 T3 6 T7 4
valid_sources[0x19] 27859 1 T1 17 T2 8 T3 3
valid_sources[0x1a] 26399 1 T1 5 T2 10 T3 4
valid_sources[0x1b] 26811 1 T2 16 T3 2 T8 104
valid_sources[0x1c] 26186 1 T2 3 T3 2 T8 175
valid_sources[0x1d] 26201 1 T2 9 T3 1 T7 2
valid_sources[0x1e] 25462 1 T2 6 T3 2 T8 174
valid_sources[0x1f] 25438 1 T1 12 T2 7 T3 3
valid_sources[0x20] 27237 1 T2 18 T7 1 T8 119


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24560 1 T1 4 T2 10 T3 3
values[0x0] all_enables biggest_size 182177 1 T1 46 T2 58 T3 5
values[0x1] all_enables biggest_size 24019 1 T1 4 T2 10 T3 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1467112 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 239758 1 T1 59 T2 70 T3 10


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 584471 1 T1 119 T2 168 T3 51
values[0x0] 538984 1 T1 132 T2 156 T3 10
values[0x1] 583415 1 T1 163 T2 159 T3 46


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1126018 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 580852 1 T1 147 T2 159 T3 36


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27053 1 T2 3 T3 1 T7 4
valid_sources[0x01] 26407 1 T1 20 T2 11 T3 1
valid_sources[0x02] 27022 1 T2 4 T3 3 T8 198
valid_sources[0x03] 26654 1 T1 5 T2 9 T3 2
valid_sources[0x04] 26411 1 T2 8 T3 1 T8 130
valid_sources[0x05] 27177 1 T2 4 T7 1 T8 178
valid_sources[0x06] 27452 1 T1 7 T2 8 T3 1
valid_sources[0x07] 26466 1 T2 2 T8 152 T9 42
valid_sources[0x08] 26944 1 T1 5 T2 7 T7 11
valid_sources[0x09] 26361 1 T1 5 T2 6 T3 3
valid_sources[0x0a] 26578 1 T2 4 T3 2 T8 169
valid_sources[0x0b] 26868 1 T2 4 T3 3 T7 1
valid_sources[0x0c] 26235 1 T2 12 T3 2 T7 2
valid_sources[0x0d] 27026 1 T2 7 T3 5 T7 6
valid_sources[0x0e] 27320 1 T1 20 T2 11 T3 5
valid_sources[0x0f] 26738 1 T2 6 T3 1 T7 1
valid_sources[0x10] 26505 1 T1 15 T2 9 T3 3
valid_sources[0x11] 26796 1 T1 8 T2 4 T3 1
valid_sources[0x12] 25919 1 T2 9 T3 1 T8 184
valid_sources[0x13] 25459 1 T2 7 T3 4 T7 5
valid_sources[0x14] 27464 1 T2 6 T3 2 T7 3
valid_sources[0x15] 26492 1 T1 36 T2 7 T3 2
valid_sources[0x16] 26403 1 T2 8 T8 143 T9 36
valid_sources[0x17] 27071 1 T1 6 T2 11 T3 4
valid_sources[0x18] 26715 1 T2 11 T3 1 T8 167
valid_sources[0x19] 26783 1 T1 18 T2 12 T3 1
valid_sources[0x1a] 26386 1 T1 8 T2 11 T3 1
valid_sources[0x1b] 26752 1 T2 8 T3 1 T7 3
valid_sources[0x1c] 25835 1 T2 5 T3 2 T8 157
valid_sources[0x1d] 26245 1 T2 4 T8 137 T9 20
valid_sources[0x1e] 26140 1 T2 7 T7 3 T8 151
valid_sources[0x1f] 26544 1 T1 7 T2 4 T8 188
valid_sources[0x20] 27629 1 T2 8 T3 1 T8 173


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25296 1 T1 4 T2 9 T3 4
values[0x0] all_enables biggest_size 189424 1 T1 51 T2 54 T3 3
values[0x1] all_enables biggest_size 25038 1 T1 4 T2 7 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1468121 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 233264 1 T1 71 T2 75 T3 14


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 577182 1 T1 134 T2 140 T3 64
values[0x0] 546162 1 T1 142 T2 164 T3 16
values[0x1] 578041 1 T1 132 T2 162 T3 69


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1134489 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 566896 1 T1 163 T2 160 T3 53


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26512 1 T2 7 T3 5 T8 209
valid_sources[0x01] 26459 1 T1 13 T2 2 T7 1
valid_sources[0x02] 26779 1 T2 6 T3 4 T7 1
valid_sources[0x03] 26000 1 T1 14 T2 4 T3 4
valid_sources[0x04] 26604 1 T2 12 T3 4 T8 125
valid_sources[0x05] 25936 1 T2 8 T3 3 T8 187
valid_sources[0x06] 27131 1 T1 20 T2 6 T3 3
valid_sources[0x07] 26048 1 T2 4 T3 2 T7 17
valid_sources[0x08] 27048 1 T1 15 T2 8 T3 2
valid_sources[0x09] 26149 1 T1 5 T2 10 T3 1
valid_sources[0x0a] 27166 1 T2 15 T7 3 T8 160
valid_sources[0x0b] 25997 1 T2 5 T3 5 T7 1
valid_sources[0x0c] 26265 1 T2 4 T3 1 T8 210
valid_sources[0x0d] 26469 1 T2 2 T3 1 T7 1
valid_sources[0x0e] 26644 1 T1 16 T2 7 T3 1
valid_sources[0x0f] 26988 1 T2 8 T7 1 T8 170
valid_sources[0x10] 26666 1 T1 6 T2 11 T3 1
valid_sources[0x11] 26616 1 T1 16 T2 15 T3 6
valid_sources[0x12] 25671 1 T2 13 T3 2 T7 2
valid_sources[0x13] 25719 1 T2 5 T3 1 T7 12
valid_sources[0x14] 26624 1 T2 13 T3 2 T7 5
valid_sources[0x15] 26928 1 T1 21 T2 7 T3 1
valid_sources[0x16] 27421 1 T2 15 T3 1 T7 7
valid_sources[0x17] 25977 1 T1 16 T2 12 T3 2
valid_sources[0x18] 26328 1 T2 7 T3 5 T7 4
valid_sources[0x19] 27190 1 T1 6 T2 7 T3 2
valid_sources[0x1a] 26562 1 T1 19 T2 4 T3 4
valid_sources[0x1b] 25496 1 T2 7 T3 2 T7 7
valid_sources[0x1c] 26193 1 T2 8 T3 6 T8 138
valid_sources[0x1d] 26442 1 T2 4 T3 1 T7 8
valid_sources[0x1e] 27530 1 T2 4 T3 2 T8 155
valid_sources[0x1f] 26120 1 T1 5 T2 7 T3 4
valid_sources[0x20] 27315 1 T2 3 T7 1 T8 150


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24313 1 T1 6 T2 6 T3 6
values[0x0] all_enables biggest_size 184469 1 T1 59 T2 60 T3 5
values[0x1] all_enables biggest_size 24482 1 T1 6 T2 9 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%