Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7377273	0	0
GntImpliesValid_A	2147483647	7377273	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7377273	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	450540738	0	0
ReadyAndValidImplyGrant_A	2147483647	7377273	0	0
ReqAndReadyImplyGrant_A	2147483647	7377273	0	0
ReqImpliesValid_A	2147483647	34094268	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	34430	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7377273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	565032	563616	0	0
T2	327168	326640	0	0
T3	243384	242664	0	0
T7	7375368	7374384	0	0
T8	9499128	9493968	0	0
T9	241224	240624	0	0
T10	96696	96384	0	0
T11	110064	108576	0	0
T12	187944	187656	0	0
T13	309216	308328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	565032	563616	0	0
T2	327168	326640	0	0
T3	243384	242664	0	0
T7	7375368	7374384	0	0
T8	9499128	9493968	0	0
T9	241224	240624	0	0
T10	96696	96384	0	0
T11	110064	108576	0	0
T12	187944	187656	0	0
T13	309216	308328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	565032	563616	0	0
T2	327168	326640	0	0
T3	243384	242664	0	0
T7	7375368	7374384	0	0
T8	9499128	9493968	0	0
T9	241224	240624	0	0
T10	96696	96384	0	0
T11	110064	108576	0	0
T12	187944	187656	0	0
T13	309216	308328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	450540738	0	0
T1	565032	30569	0	0
T2	327168	16365	0	0
T3	243384	5331	0	0
T4	0	25944	0	0
T7	7375368	257942	0	0
T8	9499128	518674	0	0
T9	241224	6758	0	0
T10	96696	133	0	0
T11	110064	260	0	0
T12	187944	3705	0	0
T13	309216	14310	0	0
T14	0	1889	0	0
T15	0	12622	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34094268	0	0
T1	565032	2104	0	0
T2	327168	7452	0	0
T3	243384	4682	0	0
T4	0	3123	0	0
T7	7375368	729	0	0
T8	9499128	86239	0	0
T9	241224	7286	0	0
T10	96696	3490	0	0
T11	110064	4643	0	0
T12	187944	3974	0	0
T13	309216	1162	0	0
T14	0	1242	0	0
T15	0	5864	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34430	0	21600
T3	20282	7	0	2
T4	954660	0	0	2
T7	614614	0	0	2
T8	791594	73	0	2
T9	20102	31	0	2
T10	8058	295	0	2
T11	9172	508	0	2
T12	15662	10	0	2
T13	25768	0	0	2
T14	36760	0	0	2
T15	0	4	0	0
T16	0	345	0	0
T17	0	8	0	0
T18	0	1	0	0
T19	0	102	0	0
T20	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	565032	563616	0	0
T2	327168	326640	0	0
T3	243384	242664	0	0
T7	7375368	7374384	0	0
T8	9499128	9493968	0	0
T9	241224	240624	0	0
T10	96696	96384	0	0
T11	110064	108576	0	0
T12	187944	187656	0	0
T13	309216	308328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7377273	0	0
T1	565032	1205	0	0
T2	327168	1477	0	0
T3	243384	4169	0	0
T4	0	255	0	0
T7	7375368	465	0	0
T8	9499128	26768	0	0
T9	241224	6427	0	0
T10	96696	2229	0	0
T11	110064	2969	0	0
T12	187944	3627	0	0
T13	309216	489	0	0
T14	0	820	0	0
T15	0	3686	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	817797	0	0
GntImpliesValid_A	407543394	817797	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	817797	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	12551789	0	0
ReadyAndValidImplyGrant_A	407543394	817797	0	0
ReqAndReadyImplyGrant_A	407543394	817797	0	0
ReqImpliesValid_A	407543394	2372697	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	817797	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	12551789	0	0
T1	23543	1076	0	0
T2	13632	805	0	0
T3	10141	396	0	0
T7	307307	173	0	0
T8	395797	18105	0	0
T9	10051	518	0	0
T10	4029	68	0	0
T11	4586	83	0	0
T12	7831	333	0	0
T13	12884	377	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	2372697	0	0
T1	23543	148	0	0
T2	13632	178	0	0
T3	10141	571	0	0
T7	307307	54	0	0
T8	395797	3536	0	0
T9	10051	973	0	0
T10	4029	1619	0	0
T11	4586	132	0	0
T12	7831	480	0	0
T13	12884	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	817797	0	0
T1	23543	133	0	0
T2	13632	122	0	0
T3	10141	483	0	0
T7	307307	42	0	0
T8	395797	2411	0	0
T9	10051	745	0	0
T10	4029	843	0	0
T11	4586	107	0	0
T12	7831	406	0	0
T13	12884	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	813126	0	0
GntImpliesValid_A	407543394	813126	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	813126	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	12571646	0	0
ReadyAndValidImplyGrant_A	407543394	813126	0	0
ReqAndReadyImplyGrant_A	407543394	813126	0	0
ReqImpliesValid_A	407543394	2414092	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	813126	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	12571646	0	0
T1	23543	931	0	0
T2	13632	939	0	0
T3	10141	377	0	0
T7	307307	166	0	0
T8	395797	21091	0	0
T9	10051	507	0	0
T10	4029	41	0	0
T11	4586	89	0	0
T12	7831	334	0	0
T13	12884	365	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	2414092	0	0
T1	23543	133	0	0
T2	13632	194	0	0
T3	10141	540	0	0
T7	307307	46	0	0
T8	395797	9325	0	0
T9	10051	828	0	0
T10	4029	80	0	0
T11	4586	1636	0	0
T12	7831	467	0	0
T13	12884	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	813126	0	0
T1	23543	122	0	0
T2	13632	123	0	0
T3	10141	458	0	0
T7	307307	39	0	0
T8	395797	3235	0	0
T9	10051	667	0	0
T10	4029	60	0	0
T11	4586	862	0	0
T12	7831	400	0	0
T13	12884	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	199033	0	0
GntImpliesValid_A	407543394	199033	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	199033	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3165129	0	0
ReadyAndValidImplyGrant_A	407543394	199033	0	0
ReqAndReadyImplyGrant_A	407543394	199033	0	0
ReqImpliesValid_A	407543394	534819	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	199033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3165129	0	0
T1	23543	225	0	0
T2	13632	1	0	0
T3	10141	101	0	0
T7	307307	56	0	0
T8	395797	6018	0	0
T9	10051	161	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	99	0	0
T13	12884	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	534819	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	116	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	1883	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	108	0	0
T13	12884	11	0	0
T14	0	57	0	0
T15	0	315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199033	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	108	0	0
T4	0	12	0	0
T7	307307	13	0	0
T8	395797	872	0	0
T9	10051	170	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	103	0	0
T13	12884	11	0	0
T14	0	36	0	0
T15	0	221	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	217486	0	0
GntImpliesValid_A	407543394	217486	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	217486	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3148987	0	0
ReadyAndValidImplyGrant_A	407543394	217486	0	0
ReqAndReadyImplyGrant_A	407543394	217486	0	0
ReqImpliesValid_A	407543394	600438	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	217486	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3148987	0	0
T1	23543	265	0	0
T2	13632	1	0	0
T3	10141	116	0	0
T7	307307	68	0	0
T8	395797	5610	0	0
T9	10051	162	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	95	0	0
T13	12884	101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	600438	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	119	0	0
T4	0	18	0	0
T7	307307	29	0	0
T8	395797	2754	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	106	0	0
T13	12884	14	0	0
T14	0	63	0	0
T15	0	408	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	217486	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	18	0	0
T7	307307	21	0	0
T8	395797	891	0	0
T9	10051	168	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	14	0	0
T14	0	48	0	0
T15	0	257	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	209386	0	0
GntImpliesValid_A	407543394	209386	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	209386	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	4427623	0	0
ReadyAndValidImplyGrant_A	407543394	209386	0	0
ReqAndReadyImplyGrant_A	407543394	209386	0	0
ReqImpliesValid_A	407543394	1032681	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	209386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	4427623	0	0
T1	23543	335	0	0
T2	13632	0	0	0
T3	10141	581	0	0
T4	0	2165	0	0
T7	307307	101	0	0
T8	395797	9014	0	0
T9	10051	737	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	356	0	0
T13	12884	271	0	0
T14	0	390	0	0
T15	0	2498	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	1032681	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	182	0	0
T4	0	603	0	0
T7	307307	15	0	0
T8	395797	3555	0	0
T9	10051	241	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	118	0	0
T13	12884	11	0	0
T14	0	52	0	0
T15	0	364	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	209386	0	0
T1	23543	27	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	8	0	0
T7	307307	15	0	0
T8	395797	780	0	0
T9	10051	167	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	100	0	0
T13	12884	11	0	0
T14	0	45	0	0
T15	0	214	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	201378	0	0
GntImpliesValid_A	407543394	201378	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	201378	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	4587330	0	0
ReadyAndValidImplyGrant_A	407543394	201378	0	0
ReqAndReadyImplyGrant_A	407543394	201378	0	0
ReqImpliesValid_A	407543394	995732	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	201378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	4587330	0	0
T1	23543	399	0	0
T2	13632	0	0	0
T3	10141	1226	0	0
T4	0	6560	0	0
T7	307307	150	0	0
T8	395797	39576	0	0
T9	10051	991	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	459	0	0
T13	12884	131	0	0
T14	0	413	0	0
T15	0	5210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	995732	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	230	0	0
T4	0	108	0	0
T7	307307	13	0	0
T8	395797	3779	0	0
T9	10051	289	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	196	0	0
T13	12884	24	0	0
T14	0	71	0	0
T15	0	679	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201378	0	0
T1	23543	23	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	16	0	0
T7	307307	13	0	0
T8	395797	458	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	130	0	0
T13	12884	15	0	0
T14	0	39	0	0
T15	0	236	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	205431	0	0
GntImpliesValid_A	407543394	205431	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	205431	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	6051668	0	0
ReadyAndValidImplyGrant_A	407543394	205431	0	0
ReqAndReadyImplyGrant_A	407543394	205431	0	0
ReqImpliesValid_A	407543394	1360001	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	205431	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	6051668	0	0
T1	23543	612	0	0
T2	13632	0	0	0
T3	10141	473	0	0
T4	0	3200	0	0
T7	307307	90	0	0
T8	395797	8758	0	0
T9	10051	630	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	309	0	0
T13	12884	91	0	0
T14	0	797	0	0
T15	0	2555	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	1360001	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	148	0	0
T4	0	19	0	0
T7	307307	30	0	0
T8	395797	606	0	0
T9	10051	234	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	108	0	0
T13	12884	22	0	0
T14	0	158	0	0
T15	0	388	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205431	0	0
T1	23543	40	0	0
T2	13632	0	0	0
T3	10141	114	0	0
T4	0	13	0	0
T7	307307	19	0	0
T8	395797	468	0	0
T9	10051	174	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	13	0	0
T14	0	41	0	0
T15	0	226	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	199588	0	0
GntImpliesValid_A	407543394	199588	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	199588	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	4486254	0	0
ReadyAndValidImplyGrant_A	407543394	199588	0	0
ReqAndReadyImplyGrant_A	407543394	199588	0	0
ReqImpliesValid_A	407543394	966387	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	199588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	4486254	0	0
T1	23543	1652	0	0
T2	13632	0	0	0
T3	10141	469	0	0
T4	0	14019	0	0
T7	307307	158	0	0
T8	395797	8906	0	0
T9	10051	597	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	379	0	0
T13	12884	119	0	0
T14	0	289	0	0
T15	0	2359	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	966387	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	147	0	0
T4	0	561	0	0
T7	307307	49	0	0
T8	395797	758	0	0
T9	10051	250	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	136	0	0
T13	12884	14	0	0
T14	0	53	0	0
T15	0	381	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	199588	0	0
T1	23543	29	0	0
T2	13632	0	0	0
T3	10141	113	0	0
T4	0	15	0	0
T7	307307	18	0	0
T8	395797	466	0	0
T9	10051	172	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	249	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	201264	0	0
GntImpliesValid_A	407543394	201264	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	201264	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3159319	0	0
ReadyAndValidImplyGrant_A	407543394	201264	0	0
ReqAndReadyImplyGrant_A	407543394	201264	0	0
ReqImpliesValid_A	407543394	541464	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	201264	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3159319	0	0
T1	23543	340	0	0
T2	13632	1	0	0
T3	10141	101	0	0
T7	307307	99	0	0
T8	395797	6903	0	0
T9	10051	169	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	108	0	0
T13	12884	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	541464	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	11	0	0
T7	307307	26	0	0
T8	395797	6663	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	9	0	0
T14	0	53	0	0
T15	0	315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	201264	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	109	0	0
T4	0	11	0	0
T7	307307	25	0	0
T8	395797	1344	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	110	0	0
T13	12884	9	0	0
T14	0	52	0	0
T15	0	226	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	211020	0	0
GntImpliesValid_A	407543394	211020	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	211020	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3125812	0	0
ReadyAndValidImplyGrant_A	407543394	211020	0	0
ReqAndReadyImplyGrant_A	407543394	211020	0	0
ReqImpliesValid_A	407543394	585492	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	211020	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3125812	0	0
T1	23543	255	0	0
T2	13632	1	0	0
T3	10141	107	0	0
T7	307307	78	0	0
T8	395797	3321	0	0
T9	10051	175	0	0
T10	4029	1	0	0
T11	4586	2	0	0
T12	7831	91	0	0
T13	12884	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	585492	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	124	0	0
T4	0	396	0	0
T7	307307	24	0	0
T8	395797	496	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	861	0	0
T12	7831	100	0	0
T13	12884	21	0	0
T14	0	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	211020	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	12	0	0
T7	307307	22	0	0
T8	395797	450	0	0
T9	10051	178	0	0
T10	4029	0	0	0
T11	4586	431	0	0
T12	7831	95	0	0
T13	12884	13	0	0
T14	0	41	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	198618	0	0
GntImpliesValid_A	407543394	198618	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	198618	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3139593	0	0
ReadyAndValidImplyGrant_A	407543394	198618	0	0
ReqAndReadyImplyGrant_A	407543394	198618	0	0
ReqImpliesValid_A	407543394	546454	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	198618	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3139593	0	0
T1	23543	328	0	0
T2	13632	1	0	0
T3	10141	108	0	0
T7	307307	51	0	0
T8	395797	4201	0	0
T9	10051	177	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	109	0	0
T13	12884	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	546454	0	0
T1	23543	48	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	229	0	0
T7	307307	23	0	0
T8	395797	2756	0	0
T9	10051	190	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	118	0	0
T13	12884	10	0	0
T14	0	61	0	0
T15	0	313	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198618	0	0
T1	23543	45	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	17	0	0
T7	307307	10	0	0
T8	395797	900	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	113	0	0
T13	12884	10	0	0
T14	0	49	0	0
T15	0	221	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	196496	0	0
GntImpliesValid_A	407543394	196496	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	196496	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3139257	0	0
ReadyAndValidImplyGrant_A	407543394	196496	0	0
ReqAndReadyImplyGrant_A	407543394	196496	0	0
ReqImpliesValid_A	407543394	542616	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	196496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3139257	0	0
T1	23543	229	0	0
T2	13632	1	0	0
T3	10141	101	0	0
T7	307307	45	0	0
T8	395797	3715	0	0
T9	10051	174	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	80	0	0
T13	12884	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	542616	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	7	0	0
T7	307307	21	0	0
T8	395797	532	0	0
T9	10051	191	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	83	0	0
T13	12884	12	0	0
T14	0	55	0	0
T15	0	327	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196496	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	7	0	0
T7	307307	11	0	0
T8	395797	463	0	0
T9	10051	182	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	81	0	0
T13	12884	10	0	0
T14	0	34	0	0
T15	0	241	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	208343	0	0
GntImpliesValid_A	407543394	208343	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	208343	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3171827	0	0
ReadyAndValidImplyGrant_A	407543394	208343	0	0
ReqAndReadyImplyGrant_A	407543394	208343	0	0
ReqImpliesValid_A	407543394	514070	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	208343	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3171827	0	0
T1	23543	235	0	0
T2	13632	1	0	0
T3	10141	112	0	0
T7	307307	54	0	0
T8	395797	6599	0	0
T9	10051	168	0	0
T10	4029	1	0	0
T11	4586	70	0	0
T12	7831	86	0	0
T13	12884	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	514070	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	125	0	0
T4	0	354	0	0
T7	307307	22	0	0
T8	395797	4315	0	0
T9	10051	183	0	0
T10	4029	0	0	0
T11	4586	959	0	0
T12	7831	89	0	0
T13	12884	15	0	0
T14	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208343	0	0
T1	23543	33	0	0
T2	13632	0	0	0
T3	10141	118	0	0
T4	0	13	0	0
T7	307307	18	0	0
T8	395797	1461	0	0
T9	10051	175	0	0
T10	4029	0	0	0
T11	4586	514	0	0
T12	7831	87	0	0
T13	12884	10	0	0
T14	0	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	218878	0	0
GntImpliesValid_A	407543394	218878	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	218878	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3203262	0	0
ReadyAndValidImplyGrant_A	407543394	218878	0	0
ReqAndReadyImplyGrant_A	407543394	218878	0	0
ReqImpliesValid_A	407543394	603623	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	218878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3203262	0	0
T1	23543	308	0	0
T2	13632	1357	0	0
T3	10141	93	0	0
T7	307307	70	0	0
T8	395797	3135	0	0
T9	10051	178	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	98	0	0
T13	12884	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	603623	0	0
T1	23543	38	0	0
T2	13632	1927	0	0
T3	10141	106	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	422	0	0
T9	10051	199	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	14	0	0
T14	0	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218878	0	0
T1	23543	38	0	0
T2	13632	527	0	0
T3	10141	99	0	0
T4	0	9	0	0
T7	307307	18	0	0
T8	395797	406	0	0
T9	10051	188	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	101	0	0
T13	12884	12	0	0
T14	0	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	196833	0	0
GntImpliesValid_A	407543394	196833	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	196833	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3091110	0	0
ReadyAndValidImplyGrant_A	407543394	196833	0	0
ReqAndReadyImplyGrant_A	407543394	196833	0	0
ReqImpliesValid_A	407543394	542180	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	196833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3091110	0	0
T1	23543	335	0	0
T2	13632	1	0	0
T3	10141	112	0	0
T7	307307	63	0	0
T8	395797	5619	0	0
T9	10051	152	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	91	0	0
T13	12884	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	542180	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	119	0	0
T4	0	18	0	0
T7	307307	23	0	0
T8	395797	1533	0	0
T9	10051	173	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	104	0	0
T13	12884	36	0	0
T14	0	63	0	0
T15	0	313	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	196833	0	0
T1	23543	38	0	0
T2	13632	0	0	0
T3	10141	115	0	0
T4	0	18	0	0
T7	307307	14	0	0
T8	395797	870	0	0
T9	10051	162	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	97	0	0
T13	12884	17	0	0
T14	0	43	0	0
T15	0	222	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	205348	0	0
GntImpliesValid_A	407543394	205348	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	205348	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3173963	0	0
ReadyAndValidImplyGrant_A	407543394	205348	0	0
ReqAndReadyImplyGrant_A	407543394	205348	0	0
ReqImpliesValid_A	407543394	589637	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	205348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3173963	0	0
T1	23543	194	0	0
T2	13632	1119	0	0
T3	10141	109	0	0
T7	307307	34	0	0
T8	395797	3853	0	0
T9	10051	154	0	0
T10	4029	7	0	0
T11	4586	1	0	0
T12	7831	100	0	0
T13	12884	131	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	589637	0	0
T1	23543	26	0	0
T2	13632	3930	0	0
T3	10141	116	0	0
T7	307307	9	0	0
T8	395797	6363	0	0
T9	10051	175	0	0
T10	4029	936	0	0
T11	4586	0	0	0
T12	7831	111	0	0
T13	12884	32	0	0
T14	0	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	205348	0	0
T1	23543	26	0	0
T2	13632	467	0	0
T3	10141	112	0	0
T7	307307	9	0	0
T8	395797	968	0	0
T9	10051	164	0	0
T10	4029	471	0	0
T11	4586	0	0	0
T12	7831	105	0	0
T13	12884	19	0	0
T14	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	218666	0	0
GntImpliesValid_A	407543394	218666	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	218666	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3241403	0	0
ReadyAndValidImplyGrant_A	407543394	218666	0	0
ReqAndReadyImplyGrant_A	407543394	218666	0	0
ReqImpliesValid_A	407543394	582203	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	218666	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3241403	0	0
T1	23543	306	0	0
T2	13632	1	0	0
T3	10141	200	0	0
T7	307307	70	0	0
T8	395797	7092	0	0
T9	10051	194	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	138	0	0
T13	12884	57	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	582203	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	225	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1949	0	0
T9	10051	207	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	153	0	0
T13	12884	11	0	0
T14	0	43	0	0
T15	0	315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	218666	0	0
T1	23543	41	0	0
T2	13632	0	0	0
T3	10141	212	0	0
T4	0	20	0	0
T7	307307	15	0	0
T8	395797	1117	0	0
T9	10051	200	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	145	0	0
T13	12884	9	0	0
T14	0	35	0	0
T15	0	217	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	204805	0	0
GntImpliesValid_A	407543394	204805	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	204805	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3183928	0	0
ReadyAndValidImplyGrant_A	407543394	204805	0	0
ReqAndReadyImplyGrant_A	407543394	204805	0	0
ReqImpliesValid_A	407543394	548773	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	204805	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3183928	0	0
T1	23543	209	0	0
T2	13632	1	0	0
T3	10141	122	0	0
T7	307307	71	0	0
T8	395797	3245	0	0
T9	10051	175	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	93	0	0
T13	12884	185	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	548773	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	139	0	0
T4	0	12	0	0
T7	307307	20	0	0
T8	395797	473	0	0
T9	10051	186	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	56	0	0
T14	0	28	0	0
T15	0	333	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204805	0	0
T1	23543	32	0	0
T2	13632	0	0	0
T3	10141	130	0	0
T4	0	12	0	0
T7	307307	17	0	0
T8	395797	436	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	25	0	0
T14	0	24	0	0
T15	0	231	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	204664	0	0
GntImpliesValid_A	407543394	204664	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	204664	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3195033	0	0
ReadyAndValidImplyGrant_A	407543394	204664	0	0
ReqAndReadyImplyGrant_A	407543394	204664	0	0
ReqImpliesValid_A	407543394	572307	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	204664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3195033	0	0
T1	23543	211	0	0
T2	13632	1	0	0
T3	10141	96	0	0
T7	307307	67	0	0
T8	395797	3179	0	0
T9	10051	198	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	74	0	0
T13	12884	117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	572307	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	107	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	502	0	0
T9	10051	213	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	79	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	428	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	204664	0	0
T1	23543	26	0	0
T2	13632	0	0	0
T3	10141	101	0	0
T4	0	13	0	0
T7	307307	14	0	0
T8	395797	439	0	0
T9	10051	205	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	76	0	0
T13	12884	14	0	0
T14	0	44	0	0
T15	0	253	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	198341	0	0
GntImpliesValid_A	407543394	198341	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	198341	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3104791	0	0
ReadyAndValidImplyGrant_A	407543394	198341	0	0
ReqAndReadyImplyGrant_A	407543394	198341	0	0
ReqImpliesValid_A	407543394	523744	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	198341	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3104791	0	0
T1	23543	144	0	0
T2	13632	1	0	0
T3	10141	126	0	0
T7	307307	71	0	0
T8	395797	3281	0	0
T9	10051	184	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	90	0	0
T13	12884	112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	523744	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	139	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	532	0	0
T9	10051	211	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	99	0	0
T13	12884	12	0	0
T14	0	43	0	0
T15	0	408	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	198341	0	0
T1	23543	25	0	0
T2	13632	0	0	0
T3	10141	132	0	0
T4	0	11	0	0
T7	307307	15	0	0
T8	395797	425	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	94	0	0
T13	12884	12	0	0
T14	0	42	0	0
T15	0	257	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	208669	0	0
GntImpliesValid_A	407543394	208669	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	208669	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3122077	0	0
ReadyAndValidImplyGrant_A	407543394	208669	0	0
ReqAndReadyImplyGrant_A	407543394	208669	0	0
ReqImpliesValid_A	407543394	580247	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	208669	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3122077	0	0
T1	23543	268	0	0
T2	13632	1	0	0
T3	10141	94	0	0
T7	307307	47	0	0
T8	395797	3256	0	0
T9	10051	169	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	95	0	0
T13	12884	83	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	580247	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	117	0	0
T4	0	365	0	0
T7	307307	9	0	0
T8	395797	469	0	0
T9	10051	192	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	102	0	0
T13	12884	11	0	0
T14	0	79	0	0
T15	0	296	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	208669	0	0
T1	23543	36	0	0
T2	13632	0	0	0
T3	10141	105	0	0
T4	0	17	0	0
T7	307307	9	0	0
T8	395797	456	0	0
T9	10051	180	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	98	0	0
T13	12884	11	0	0
T14	0	46	0	0
T15	0	210	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T3,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	202427	0	0
GntImpliesValid_A	407543394	202427	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	202427	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	3149752	0	0
ReadyAndValidImplyGrant_A	407543394	202427	0	0
ReqAndReadyImplyGrant_A	407543394	202427	0	0
ReqImpliesValid_A	407543394	542210	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	0	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	202427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	3149752	0	0
T1	23543	265	0	0
T2	13632	1	0	0
T3	10141	109	0	0
T7	307307	64	0	0
T8	395797	3288	0	0
T9	10051	186	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	86	0	0
T13	12884	175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	542210	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	112	0	0
T4	0	357	0	0
T7	307307	25	0	0
T8	395797	463	0	0
T9	10051	209	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	93	0	0
T13	12884	19	0	0
T14	0	48	0	0
T15	0	281	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	202427	0	0
T1	23543	37	0	0
T2	13632	0	0	0
T3	10141	110	0	0
T4	0	13	0	0
T7	307307	15	0	0
T8	395797	440	0	0
T9	10051	197	0	0
T10	4029	0	0	0
T11	4586	0	0	0
T12	7831	89	0	0
T13	12884	18	0	0
T14	0	33	0	0
T15	0	205	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	827928	0	0
GntImpliesValid_A	407543394	827928	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	827928	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	12030251	0	0
ReadyAndValidImplyGrant_A	407543394	827928	0	0
ReqAndReadyImplyGrant_A	407543394	827928	0	0
ReqImpliesValid_A	407543394	2281427	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	15594	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	827928	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	12030251	0	0
T1	23543	954	0	0
T2	13632	681	0	0
T3	10141	1	0	0
T7	307307	111	0	0
T8	395797	17250	0	0
T9	10051	1	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	1	0	0
T13	12884	287	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	2281427	0	0
T1	23543	178	0	0
T2	13632	159	0	0
T3	10141	405	0	0
T7	307307	43	0	0
T8	395797	4930	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	15594	0	900
T3	10141	4	0	1
T4	477330	0	0	1
T7	307307	0	0	1
T8	395797	23	0	1
T9	10051	14	0	1
T10	4029	295	0	1
T11	4586	0	0	1
T12	7831	5	0	1
T13	12884	0	0	1
T14	18380	0	0	1
T15	0	2	0	0
T16	0	14	0	0
T17	0	2	0	0
T19	0	52	0	0
T20	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	827928	0	0
T1	23543	153	0	0
T2	13632	109	0	0
T3	10141	405	0	0
T7	307307	33	0	0
T8	395797	3131	0	0
T9	10051	693	0	0
T10	4029	794	0	0
T11	4586	129	0	0
T12	7831	432	0	0
T13	12884	52	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407543394	407419119	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407543394	811748	0	0
GntImpliesValid_A	407543394	811748	0	0
GrantKnown_A	407543394	407419119	0	0
IdxKnown_A	407543394	407419119	0	0
IndexIsCorrect_A	407543394	811748	0	0
LockArbDecision_A	407543394	0	0	0
NoReadyValidNoGrant_A	407543394	343318934	0	0
ReadyAndValidImplyGrant_A	407543394	811748	0	0
ReqAndReadyImplyGrant_A	407543394	811748	0	0
ReqImpliesValid_A	407543394	13720974	0	0
ReqStaysHighUntilGranted0_M	407543394	0	0	0
RoundRobin_A	407543394	18836	0	900
ValidKnown_A	407543394	407419119	0	0
gen_data_port_assertion.DataFlow_A	407543394	811748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	343318934	0	0
T1	23543	20493	0	0
T2	13632	11450	0	0
T3	10141	1	0	0
T7	307307	255985	0	0
T8	395797	323659	0	0
T9	10051	1	0	0
T10	4029	1	0	0
T11	4586	1	0	0
T12	7831	1	0	0
T13	12884	11179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	13720974	0	0
T1	23543	963	0	0
T2	13632	1064	0	0
T3	10141	450	0	0
T7	307307	173	0	0
T8	395797	27645	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	561	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	18836	0	900
T3	10141	3	0	1
T4	477330	0	0	1
T7	307307	0	0	1
T8	395797	50	0	1
T9	10051	17	0	1
T10	4029	0	0	1
T11	4586	508	0	1
T12	7831	5	0	1
T13	12884	0	0	1
T14	18380	0	0	1
T15	0	2	0	0
T16	0	331	0	0
T17	0	6	0	0
T18	0	1	0	0
T19	0	50	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	407419119	0	0
T1	23543	23484	0	0
T2	13632	13610	0	0
T3	10141	10111	0	0
T7	307307	307266	0	0
T8	395797	395582	0	0
T9	10051	10026	0	0
T10	4029	4016	0	0
T11	4586	4524	0	0
T12	7831	7819	0	0
T13	12884	12847	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407543394	811748	0	0
T1	23543	129	0	0
T2	13632	129	0	0
T3	10141	450	0	0
T7	307307	40	0	0
T8	395797	3881	0	0
T9	10051	730	0	0
T10	4029	61	0	0
T11	4586	926	0	0
T12	7831	380	0	0
T13	12884	63	0	0