Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1537040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244180

1

T1

13

T2

7

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	603789	1			T1	36		T2	41		T3	41
values[0x0]	572711	1			T1	34		T2	7		T3	33
values[0x1]	604720	1			T1	36		T2	26		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1188726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

592494

1

T1

32

T2

27

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27497	1			T1	1		T2	3		T7	43
valid_sources[0x01]	27380	1			T1	7		T2	1		T3	4
valid_sources[0x02]	27142	1			T1	2		T2	2		T3	5
valid_sources[0x03]	27164	1			T1	4		T2	1		T3	4
valid_sources[0x04]	27791	1			T1	1		T2	1		T3	4
valid_sources[0x05]	27949	1			T1	1		T2	2		T3	6
valid_sources[0x06]	27687	1			T1	1		T7	48		T8	2
valid_sources[0x07]	28265	1			T1	1		T3	1		T7	44
valid_sources[0x08]	26688	1			T1	2		T7	56		T8	6
valid_sources[0x09]	27892	1			T1	1		T3	2		T7	48
valid_sources[0x0a]	28132	1			T1	1		T7	38		T8	1
valid_sources[0x0b]	28407	1			T1	3		T2	2		T7	54
valid_sources[0x0c]	27227	1			T7	56		T8	4		T4	31
valid_sources[0x0d]	28068	1			T1	2		T2	1		T7	35
valid_sources[0x0e]	27692	1			T2	3		T3	1		T7	46
valid_sources[0x0f]	26962	1			T1	2		T2	2		T7	43
valid_sources[0x10]	26926	1			T2	2		T7	38		T8	1
valid_sources[0x11]	28232	1			T1	1		T7	38		T8	2
valid_sources[0x12]	27938	1			T1	1		T2	2		T7	44
valid_sources[0x13]	27796	1			T1	2		T3	4		T7	36
valid_sources[0x14]	27897	1			T1	5		T2	1		T7	46
valid_sources[0x15]	28244	1			T1	1		T2	1		T7	29
valid_sources[0x16]	28680	1			T2	1		T7	31		T8	1
valid_sources[0x17]	28211	1			T1	3		T7	40		T8	3
valid_sources[0x18]	28095	1			T1	2		T2	3		T3	2
valid_sources[0x19]	29340	1			T2	2		T7	44		T8	2
valid_sources[0x1a]	27640	1			T1	4		T2	1		T7	37
valid_sources[0x1b]	27540	1			T1	1		T2	3		T7	38
valid_sources[0x1c]	28230	1			T2	2		T7	30		T8	3
valid_sources[0x1d]	28011	1			T1	2		T2	1		T7	47
valid_sources[0x1e]	27477	1			T1	2		T3	3		T7	51
valid_sources[0x1f]	28047	1			T7	34		T8	2		T4	18
valid_sources[0x20]	27194	1			T1	1		T2	2		T7	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25393

1

T1

1

T2

5

T7

43

values[0x0]

all_enables

biggest_size

193151

1

T1

12

T2

1

T3

10

values[0x1]

all_enables

biggest_size

25636

1

T2

1

T7

41

T8

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1547918	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251985

1

T1

19

T2

2

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	615724	1			T1	51		T2	51		T3	35
values[0x0]	567796	1			T1	44		T2	4		T3	44
values[0x1]	616383	1			T1	31		T2	42		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1187584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

612319

1

T1

41

T2

34

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27530	1			T1	9		T2	9		T3	4
valid_sources[0x01]	27686	1			T2	1		T3	1		T7	56
valid_sources[0x02]	28774	1			T2	2		T3	5		T7	49
valid_sources[0x03]	27663	1			T2	2		T3	1		T7	55
valid_sources[0x04]	28739	1			T1	6		T2	2		T3	1
valid_sources[0x05]	27972	1			T1	6		T7	40		T8	1
valid_sources[0x06]	27625	1			T2	2		T3	3		T7	44
valid_sources[0x07]	27352	1			T1	1		T2	4		T3	2
valid_sources[0x08]	28082	1			T2	1		T3	3		T7	57
valid_sources[0x09]	28784	1			T2	2		T7	56		T8	6
valid_sources[0x0a]	28791	1			T2	1		T3	2		T7	44
valid_sources[0x0b]	27634	1			T1	11		T7	66		T8	3
valid_sources[0x0c]	27869	1			T1	11		T7	63		T8	1
valid_sources[0x0d]	28662	1			T3	2		T7	44		T8	2
valid_sources[0x0e]	28120	1			T3	4		T7	51		T8	2
valid_sources[0x0f]	28235	1			T2	2		T7	43		T8	1
valid_sources[0x10]	28497	1			T1	1		T3	1		T7	34
valid_sources[0x11]	28204	1			T3	2		T7	47		T4	21
valid_sources[0x12]	28020	1			T2	2		T3	5		T7	34
valid_sources[0x13]	28805	1			T7	14		T8	1		T4	17
valid_sources[0x14]	27712	1			T3	2		T7	43		T8	4
valid_sources[0x15]	27956	1			T2	4		T3	2		T7	22
valid_sources[0x16]	28316	1			T2	1		T7	36		T8	4
valid_sources[0x17]	28450	1			T1	4		T7	32		T8	1
valid_sources[0x18]	28283	1			T2	3		T3	2		T7	39
valid_sources[0x19]	28849	1			T1	2		T2	1		T3	1
valid_sources[0x1a]	27579	1			T3	3		T7	43		T8	4
valid_sources[0x1b]	27971	1			T1	4		T2	1		T3	2
valid_sources[0x1c]	28676	1			T3	1		T7	54		T8	3
valid_sources[0x1d]	27773	1			T7	46		T8	2		T4	20
valid_sources[0x1e]	28178	1			T2	2		T3	1		T7	32
valid_sources[0x1f]	27488	1			T2	5		T3	3		T7	50
valid_sources[0x20]	28205	1			T1	3		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26357

1

T1

2

T2

1

T7

41

values[0x0]

all_enables

biggest_size

199378

1

T1

15

T2

1

T3

13

values[0x1]

all_enables

biggest_size

26250

1

T1

2

T3

1

T7

36

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1544610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

245753

1

T1

23

T2

10

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	608536	1			T1	60		T2	40		T3	20
values[0x0]	575097	1			T1	59		T2	8		T3	30
values[0x1]	606730	1			T1	57		T2	42		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596834

1

T1

62

T2

31

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27820	1			T1	5		T3	1		T7	67
valid_sources[0x01]	28697	1			T2	1		T7	29		T8	4
valid_sources[0x02]	27708	1			T2	1		T7	43		T8	5
valid_sources[0x03]	27876	1			T1	2		T2	1		T3	2
valid_sources[0x04]	27971	1			T1	2		T2	5		T3	3
valid_sources[0x05]	28732	1			T1	2		T2	1		T3	3
valid_sources[0x06]	27408	1			T7	39		T8	6		T4	22
valid_sources[0x07]	28538	1			T1	8		T2	3		T7	51
valid_sources[0x08]	27340	1			T1	4		T2	2		T3	2
valid_sources[0x09]	27750	1			T1	1		T2	1		T7	70
valid_sources[0x0a]	28726	1			T1	9		T2	2		T7	51
valid_sources[0x0b]	28650	1			T1	7		T2	1		T3	2
valid_sources[0x0c]	27630	1			T1	4		T2	1		T3	3
valid_sources[0x0d]	28304	1			T2	3		T7	31		T8	6
valid_sources[0x0e]	27794	1			T1	2		T2	1		T7	33
valid_sources[0x0f]	28182	1			T1	7		T2	1		T7	50
valid_sources[0x10]	27503	1			T1	1		T2	1		T3	4
valid_sources[0x11]	28175	1			T1	1		T2	1		T3	1
valid_sources[0x12]	28205	1			T1	9		T3	2		T7	47
valid_sources[0x13]	27780	1			T1	1		T2	1		T3	2
valid_sources[0x14]	26946	1			T2	2		T7	52		T8	3
valid_sources[0x15]	28564	1			T1	2		T2	3		T3	3
valid_sources[0x16]	27871	1			T2	1		T3	1		T7	44
valid_sources[0x17]	27933	1			T1	2		T2	2		T3	2
valid_sources[0x18]	28383	1			T1	1		T7	44		T4	2
valid_sources[0x19]	29492	1			T1	6		T2	1		T7	29
valid_sources[0x1a]	27317	1			T1	3		T2	2		T7	48
valid_sources[0x1b]	27553	1			T1	3		T2	3		T7	48
valid_sources[0x1c]	27845	1			T1	1		T2	1		T7	56
valid_sources[0x1d]	27473	1			T1	6		T2	3		T3	1
valid_sources[0x1e]	27239	1			T1	9		T7	55		T4	37
valid_sources[0x1f]	28947	1			T1	6		T2	3		T3	2
valid_sources[0x20]	27223	1			T1	5		T2	1		T7	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25776

1

T1

3

T2

5

T7

38

values[0x0]

all_enables

biggest_size

194341

1

T1

19

T2

2

T3

12

values[0x1]

all_enables

biggest_size

25636

1

T1

1

T2

3

T3

1