Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7740665	0	0
GntImpliesValid_A	2147483647	7740665	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7740665	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	447270113	0	0
ReadyAndValidImplyGrant_A	2147483647	7740665	0	0
ReqAndReadyImplyGrant_A	2147483647	7740665	0	0
ReqImpliesValid_A	2147483647	32250030	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	51992	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7740665	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53856	52272	0	0
T2	1186080	1144344	0	0
T3	4977096	4975944	0	0
T4	217656	216264	0	0
T7	1824936	1824792	0	0
T8	333312	332496	0	0
T9	61872	60096	0	0
T10	57384	55968	0	0
T11	5947632	5931384	0	0
T12	210288	201792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53856	52272	0	0
T2	1186080	1144344	0	0
T3	4977096	4975944	0	0
T4	217656	216264	0	0
T7	1824936	1824792	0	0
T8	333312	332496	0	0
T9	61872	60096	0	0
T10	57384	55968	0	0
T11	5947632	5931384	0	0
T12	210288	201792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53856	52272	0	0
T2	1186080	1144344	0	0
T3	4977096	4975944	0	0
T4	217656	216264	0	0
T7	1824936	1824792	0	0
T8	333312	332496	0	0
T9	61872	60096	0	0
T10	57384	55968	0	0
T11	5947632	5931384	0	0
T12	210288	201792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447270113	0	0
T1	53856	655	0	0
T2	1186080	71699	0	0
T3	4977096	174139	0	0
T4	217656	7288	0	0
T7	1824936	114777	0	0
T8	333312	9401	0	0
T9	61872	723	0	0
T10	57384	657	0	0
T11	5947632	352319	0	0
T12	210288	12867	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32250030	0	0
T1	53856	453	0	0
T2	1186080	11877	0	0
T3	4977096	564	0	0
T4	217656	5199	0	0
T7	1824936	18787	0	0
T8	333312	9981	0	0
T9	61872	560	0	0
T10	57384	593	0	0
T11	5947632	92853	0	0
T12	210288	1846	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51992	0	21600
T2	49420	1	0	1
T3	207379	0	0	1
T4	18138	18	0	2
T7	152078	1	0	2
T8	27776	33	0	2
T9	5156	0	0	2
T10	4782	0	0	2
T11	495636	3	0	2
T12	17524	0	0	2
T13	18222	29	0	2
T14	465916	7	0	1
T15	69033	1	0	1
T16	0	494	0	0
T17	0	10	0	0
T18	0	215	0	0
T19	0	2	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	53856	52272	0	0
T2	1186080	1144344	0	0
T3	4977096	4975944	0	0
T4	217656	216264	0	0
T7	1824936	1824792	0	0
T8	333312	332496	0	0
T9	61872	60096	0	0
T10	57384	55968	0	0
T11	5947632	5931384	0	0
T12	210288	201792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7740665	0	0
T1	53856	408	0	0
T2	1186080	4935	0	0
T3	4977096	295	0	0
T4	217656	4158	0	0
T7	1824936	8527	0	0
T8	333312	8671	0	0
T9	61872	479	0	0
T10	57384	513	0	0
T11	5947632	26066	0	0
T12	210288	880	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	853646	0	0
GntImpliesValid_A	417041611	853646	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	853646	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	11174293	0	0
ReadyAndValidImplyGrant_A	417041611	853646	0	0
ReqAndReadyImplyGrant_A	417041611	853646	0	0
ReqImpliesValid_A	417041611	2321642	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	853646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	11174293	0	0
T1	2244	37	0	0
T2	49420	3438	0	0
T3	207379	126	0	0
T4	9069	334	0	0
T7	76039	6773	0	0
T8	13888	698	0	0
T9	2578	46	0	0
T10	2391	36	0	0
T11	247818	20763	0	0
T12	8762	635	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2321642	0	0
T1	2244	50	0	0
T2	49420	738	0	0
T3	207379	42	0	0
T4	9069	539	0	0
T7	76039	1816	0	0
T8	13888	1243	0	0
T9	2578	81	0	0
T10	2391	65	0	0
T11	247818	8916	0	0
T12	8762	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	853646	0	0
T1	2244	43	0	0
T2	49420	510	0	0
T3	207379	33	0	0
T4	9069	436	0	0
T7	76039	958	0	0
T8	13888	970	0	0
T9	2578	63	0	0
T10	2391	50	0	0
T11	247818	3152	0	0
T12	8762	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	848695	0	0
GntImpliesValid_A	417041611	848695	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	848695	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	11363451	0	0
ReadyAndValidImplyGrant_A	417041611	848695	0	0
ReqAndReadyImplyGrant_A	417041611	848695	0	0
ReqImpliesValid_A	417041611	2274395	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	848695	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	11363451	0	0
T1	2244	40	0	0
T2	49420	3969	0	0
T3	207379	164	0	0
T4	9069	350	0	0
T7	76039	6526	0	0
T8	13888	752	0	0
T9	2578	38	0	0
T10	2391	54	0	0
T11	247818	18835	0	0
T12	8762	801	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2274395	0	0
T1	2244	65	0	0
T2	49420	846	0	0
T3	207379	65	0	0
T4	9069	567	0	0
T7	76039	1764	0	0
T8	13888	1333	0	0
T9	2578	59	0	0
T10	2391	89	0	0
T11	247818	11191	0	0
T12	8762	164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	848695	0	0
T1	2244	52	0	0
T2	49420	523	0	0
T3	207379	38	0	0
T4	9069	458	0	0
T7	76039	990	0	0
T8	13888	1042	0	0
T9	2578	48	0	0
T10	2391	71	0	0
T11	247818	3043	0	0
T12	8762	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	209921	0	0
GntImpliesValid_A	417041611	209921	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	209921	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2830099	0	0
ReadyAndValidImplyGrant_A	417041611	209921	0	0
ReqAndReadyImplyGrant_A	417041611	209921	0	0
ReqImpliesValid_A	417041611	535982	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	209921	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2830099	0	0
T1	2244	8	0	0
T2	49420	1037	0	0
T3	207379	53	0	0
T4	9069	116	0	0
T7	76039	1858	0	0
T8	13888	236	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	8439	0	0
T12	8762	153	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	535982	0	0
T1	2244	7	0	0
T2	49420	217	0	0
T3	207379	20	0	0
T4	9069	119	0	0
T7	76039	364	0	0
T8	13888	245	0	0
T9	2578	12	0	0
T10	2391	19	0	0
T11	247818	10245	0	0
T12	8762	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209921	0	0
T1	2244	7	0	0
T2	49420	151	0	0
T3	207379	10	0	0
T4	9069	117	0	0
T7	76039	251	0	0
T8	13888	240	0	0
T9	2578	11	0	0
T10	2391	18	0	0
T11	247818	1808	0	0
T12	8762	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	206658	0	0
GntImpliesValid_A	417041611	206658	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	206658	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2818107	0	0
ReadyAndValidImplyGrant_A	417041611	206658	0	0
ReqAndReadyImplyGrant_A	417041611	206658	0	0
ReqImpliesValid_A	417041611	499439	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	206658	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2818107	0	0
T1	2244	9	0	0
T2	49420	645	0	0
T3	207379	28	0	0
T4	9069	110	0	0
T7	76039	1640	0	0
T8	13888	226	0	0
T9	2578	19	0	0
T10	2391	20	0	0
T11	247818	3214	0	0
T12	8762	141	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	499439	0	0
T1	2244	8	0	0
T2	49420	108	0	0
T3	207379	13	0	0
T4	9069	137	0	0
T7	76039	249	0	0
T8	13888	259	0	0
T9	2578	20	0	0
T10	2391	19	0	0
T11	247818	483	0	0
T12	8762	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	206658	0	0
T1	2244	8	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	123	0	0
T7	76039	216	0	0
T8	13888	242	0	0
T9	2578	19	0	0
T10	2391	19	0	0
T11	247818	417	0	0
T12	8762	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	212667	0	0
GntImpliesValid_A	417041611	212667	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	212667	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	4660810	0	0
ReadyAndValidImplyGrant_A	417041611	212667	0	0
ReqAndReadyImplyGrant_A	417041611	212667	0	0
ReqImpliesValid_A	417041611	1190218	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	212667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	4660810	0	0
T1	2244	31	0	0
T2	49420	1436	0	0
T3	207379	81	0	0
T4	9069	764	0	0
T7	76039	989	0	0
T8	13888	1550	0	0
T9	2578	152	0	0
T10	2391	66	0	0
T11	247818	2327	0	0
T12	8762	238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	1190218	0	0
T1	2244	5	0	0
T2	49420	135	0	0
T3	207379	28	0	0
T4	9069	204	0	0
T7	76039	235	0	0
T8	13888	400	0	0
T9	2578	27	0	0
T10	2391	23	0	0
T11	247818	449	0	0
T12	8762	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	212667	0	0
T1	2244	5	0	0
T2	49420	108	0	0
T3	207379	7	0	0
T4	9069	120	0	0
T7	76039	224	0	0
T8	13888	226	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	402	0	0
T12	8762	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	202077	0	0
GntImpliesValid_A	417041611	202077	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	202077	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	4884596	0	0
ReadyAndValidImplyGrant_A	417041611	202077	0	0
ReqAndReadyImplyGrant_A	417041611	202077	0	0
ReqImpliesValid_A	417041611	1042540	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	202077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	4884596	0	0
T1	2244	113	0	0
T2	49420	834	0	0
T3	207379	67	0	0
T4	9069	1183	0	0
T7	76039	1569	0	0
T8	13888	1003	0	0
T9	2578	71	0	0
T10	2391	77	0	0
T11	247818	6283	0	0
T12	8762	185	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	1042540	0	0
T1	2244	34	0	0
T2	49420	89	0	0
T3	207379	7	0	0
T4	9069	310	0	0
T7	76039	344	0	0
T8	13888	351	0	0
T9	2578	25	0	0
T10	2391	18	0	0
T11	247818	7573	0	0
T12	8762	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	202077	0	0
T1	2244	15	0	0
T2	49420	83	0	0
T3	207379	7	0	0
T4	9069	133	0	0
T7	76039	250	0	0
T8	13888	225	0	0
T9	2578	12	0	0
T10	2391	12	0	0
T11	247818	874	0	0
T12	8762	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	211094	0	0
GntImpliesValid_A	417041611	211094	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	211094	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	4848950	0	0
ReadyAndValidImplyGrant_A	417041611	211094	0	0
ReqAndReadyImplyGrant_A	417041611	211094	0	0
ReqImpliesValid_A	417041611	1122972	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	211094	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	4848950	0	0
T1	2244	112	0	0
T2	49420	2317	0	0
T3	207379	256	0	0
T4	9069	818	0	0
T7	76039	1304	0	0
T8	13888	929	0	0
T9	2578	145	0	0
T10	2391	78	0	0
T11	247818	5289	0	0
T12	8762	405	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	1122972	0	0
T1	2244	11	0	0
T2	49420	220	0	0
T3	207379	43	0	0
T4	9069	215	0	0
T7	76039	269	0	0
T8	13888	332	0	0
T9	2578	22	0	0
T10	2391	36	0	0
T11	247818	6988	0	0
T12	8762	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	211094	0	0
T1	2244	11	0	0
T2	49420	100	0	0
T3	207379	11	0	0
T4	9069	112	0	0
T7	76039	238	0	0
T8	13888	233	0	0
T9	2578	14	0	0
T10	2391	10	0	0
T11	247818	1888	0	0
T12	8762	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	216321	0	0
GntImpliesValid_A	417041611	216321	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	216321	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	4671293	0	0
ReadyAndValidImplyGrant_A	417041611	216321	0	0
ReqAndReadyImplyGrant_A	417041611	216321	0	0
ReqImpliesValid_A	417041611	1209756	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	216321	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	4671293	0	0
T1	2244	125	0	0
T2	49420	1190	0	0
T3	207379	70	0	0
T4	9069	2050	0	0
T7	76039	1172	0	0
T8	13888	898	0	0
T9	2578	51	0	0
T10	2391	108	0	0
T11	247818	4329	0	0
T12	8762	136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	1209756	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	8	0	0
T4	9069	475	0	0
T7	76039	291	0	0
T8	13888	365	0	0
T9	2578	13	0	0
T10	2391	15	0	0
T11	247818	4040	0	0
T12	8762	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216321	0	0
T1	2244	15	0	0
T2	49420	93	0	0
T3	207379	8	0	0
T4	9069	114	0	0
T7	76039	262	0	0
T8	13888	246	0	0
T9	2578	9	0	0
T10	2391	15	0	0
T11	247818	947	0	0
T12	8762	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	217609	0	0
GntImpliesValid_A	417041611	217609	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	217609	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2862497	0	0
ReadyAndValidImplyGrant_A	417041611	217609	0	0
ReqAndReadyImplyGrant_A	417041611	217609	0	0
ReqImpliesValid_A	417041611	550222	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	217609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2862497	0	0
T1	2244	12	0	0
T2	49420	608	0	0
T3	207379	60	0	0
T4	9069	119	0	0
T7	76039	1711	0	0
T8	13888	214	0	0
T9	2578	12	0	0
T10	2391	20	0	0
T11	247818	3274	0	0
T12	8762	177	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	550222	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	16	0	0
T4	9069	136	0	0
T7	76039	288	0	0
T8	13888	241	0	0
T9	2578	11	0	0
T10	2391	21	0	0
T11	247818	489	0	0
T12	8762	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217609	0	0
T1	2244	11	0	0
T2	49420	88	0	0
T3	207379	13	0	0
T4	9069	127	0	0
T7	76039	230	0	0
T8	13888	227	0	0
T9	2578	11	0	0
T10	2391	20	0	0
T11	247818	421	0	0
T12	8762	23	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	225699	0	0
GntImpliesValid_A	417041611	225699	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	225699	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2836431	0	0
ReadyAndValidImplyGrant_A	417041611	225699	0	0
ReqAndReadyImplyGrant_A	417041611	225699	0	0
ReqImpliesValid_A	417041611	555584	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	225699	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2836431	0	0
T1	2244	11	0	0
T2	49420	832	0	0
T3	207379	21	0	0
T4	9069	115	0	0
T7	76039	1915	0	0
T8	13888	217	0	0
T9	2578	10	0	0
T10	2391	17	0	0
T11	247818	6598	0	0
T12	8762	144	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	555584	0	0
T1	2244	10	0	0
T2	49420	105	0	0
T3	207379	5	0	0
T4	9069	128	0	0
T7	76039	334	0	0
T8	13888	252	0	0
T9	2578	11	0	0
T10	2391	16	0	0
T11	247818	1697	0	0
T12	8762	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	225699	0	0
T1	2244	10	0	0
T2	49420	100	0	0
T3	207379	5	0	0
T4	9069	121	0	0
T7	76039	236	0	0
T8	13888	234	0	0
T9	2578	10	0	0
T10	2391	16	0	0
T11	247818	910	0	0
T12	8762	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	218023	0	0
GntImpliesValid_A	417041611	218023	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	218023	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2791637	0	0
ReadyAndValidImplyGrant_A	417041611	218023	0	0
ReqAndReadyImplyGrant_A	417041611	218023	0	0
ReqImpliesValid_A	417041611	529070	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	218023	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2791637	0	0
T1	2244	14	0	0
T2	49420	1722	0	0
T3	207379	14	0	0
T4	9069	125	0	0
T7	76039	1627	0	0
T8	13888	229	0	0
T9	2578	13	0	0
T10	2391	24	0	0
T11	247818	3265	0	0
T12	8762	135	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	529070	0	0
T1	2244	17	0	0
T2	49420	404	0	0
T3	207379	3	0	0
T4	9069	128	0	0
T7	76039	320	0	0
T8	13888	272	0	0
T9	2578	14	0	0
T10	2391	23	0	0
T11	247818	487	0	0
T12	8762	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218023	0	0
T1	2244	15	0	0
T2	49420	216	0	0
T3	207379	3	0	0
T4	9069	126	0	0
T7	76039	231	0	0
T8	13888	250	0	0
T9	2578	13	0	0
T10	2391	23	0	0
T11	247818	438	0	0
T12	8762	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	217209	0	0
GntImpliesValid_A	417041611	217209	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	217209	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2881646	0	0
ReadyAndValidImplyGrant_A	417041611	217209	0	0
ReqAndReadyImplyGrant_A	417041611	217209	0	0
ReqImpliesValid_A	417041611	543767	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	217209	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2881646	0	0
T1	2244	8	0	0
T2	49420	2277	0	0
T3	207379	34	0	0
T4	9069	95	0	0
T7	76039	1627	0	0
T8	13888	225	0	0
T9	2578	15	0	0
T10	2391	14	0	0
T11	247818	4373	0	0
T12	8762	804	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	543767	0	0
T1	2244	7	0	0
T2	49420	1073	0	0
T3	207379	7	0	0
T4	9069	104	0	0
T7	76039	276	0	0
T8	13888	252	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	4278	0	0
T12	8762	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	217209	0	0
T1	2244	7	0	0
T2	49420	413	0	0
T3	207379	7	0	0
T4	9069	99	0	0
T7	76039	217	0	0
T8	13888	238	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	878	0	0
T12	8762	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	218547	0	0
GntImpliesValid_A	417041611	218547	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	218547	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2823774	0	0
ReadyAndValidImplyGrant_A	417041611	218547	0	0
ReqAndReadyImplyGrant_A	417041611	218547	0	0
ReqImpliesValid_A	417041611	544754	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	218547	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2823774	0	0
T1	2244	8	0	0
T2	49420	679	0	0
T3	207379	28	0	0
T4	9069	102	0	0
T7	76039	1899	0	0
T8	13888	210	0	0
T9	2578	14	0	0
T10	2391	11	0	0
T11	247818	3059	0	0
T12	8762	126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	544754	0	0
T1	2244	7	0	0
T2	49420	90	0	0
T3	207379	4	0	0
T4	9069	107	0	0
T7	76039	361	0	0
T8	13888	239	0	0
T9	2578	17	0	0
T10	2391	14	0	0
T11	247818	517	0	0
T12	8762	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	218547	0	0
T1	2244	7	0	0
T2	49420	88	0	0
T3	207379	4	0	0
T4	9069	104	0	0
T7	76039	245	0	0
T8	13888	224	0	0
T9	2578	15	0	0
T10	2391	12	0	0
T11	247818	414	0	0
T12	8762	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	209204	0	0
GntImpliesValid_A	417041611	209204	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	209204	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2780112	0	0
ReadyAndValidImplyGrant_A	417041611	209204	0	0
ReqAndReadyImplyGrant_A	417041611	209204	0	0
ReqImpliesValid_A	417041611	510587	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	209204	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2780112	0	0
T1	2244	14	0	0
T2	49420	626	0	0
T3	207379	29	0	0
T4	9069	112	0	0
T7	76039	1548	0	0
T8	13888	229	0	0
T9	2578	12	0	0
T10	2391	6	0	0
T11	247818	3085	0	0
T12	8762	172	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	510587	0	0
T1	2244	13	0	0
T2	49420	96	0	0
T3	207379	7	0	0
T4	9069	129	0	0
T7	76039	298	0	0
T8	13888	242	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	452	0	0
T12	8762	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209204	0	0
T1	2244	13	0	0
T2	49420	91	0	0
T3	207379	5	0	0
T4	9069	120	0	0
T7	76039	229	0	0
T8	13888	235	0	0
T9	2578	11	0	0
T10	2391	5	0	0
T11	247818	401	0	0
T12	8762	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	215428	0	0
GntImpliesValid_A	417041611	215428	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	215428	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2812534	0	0
ReadyAndValidImplyGrant_A	417041611	215428	0	0
ReqAndReadyImplyGrant_A	417041611	215428	0	0
ReqImpliesValid_A	417041611	522264	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	215428	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2812534	0	0
T1	2244	16	0	0
T2	49420	824	0	0
T3	207379	39	0	0
T4	9069	118	0	0
T7	76039	1730	0	0
T8	13888	227	0	0
T9	2578	10	0	0
T10	2391	8	0	0
T11	247818	3010	0	0
T12	8762	112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	522264	0	0
T1	2244	15	0	0
T2	49420	122	0	0
T3	207379	15	0	0
T4	9069	129	0	0
T7	76039	355	0	0
T8	13888	246	0	0
T9	2578	11	0	0
T10	2391	7	0	0
T11	247818	431	0	0
T12	8762	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	215428	0	0
T1	2244	15	0	0
T2	49420	112	0	0
T3	207379	9	0	0
T4	9069	123	0	0
T7	76039	234	0	0
T8	13888	236	0	0
T9	2578	10	0	0
T10	2391	7	0	0
T11	247818	404	0	0
T12	8762	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	209391	0	0
GntImpliesValid_A	417041611	209391	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	209391	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2826139	0	0
ReadyAndValidImplyGrant_A	417041611	209391	0	0
ReqAndReadyImplyGrant_A	417041611	209391	0	0
ReqImpliesValid_A	417041611	513870	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	209391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2826139	0	0
T1	2244	11	0	0
T2	49420	615	0	0
T3	207379	29	0	0
T4	9069	107	0	0
T7	76039	1912	0	0
T8	13888	248	0	0
T9	2578	22	0	0
T10	2391	13	0	0
T11	247818	3295	0	0
T12	8762	155	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	513870	0	0
T1	2244	14	0	0
T2	49420	86	0	0
T3	207379	7	0	0
T4	9069	130	0	0
T7	76039	360	0	0
T8	13888	289	0	0
T9	2578	27	0	0
T10	2391	12	0	0
T11	247818	488	0	0
T12	8762	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209391	0	0
T1	2244	12	0	0
T2	49420	76	0	0
T3	207379	7	0	0
T4	9069	118	0	0
T7	76039	255	0	0
T8	13888	268	0	0
T9	2578	24	0	0
T10	2391	12	0	0
T11	247818	431	0	0
T12	8762	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	238282	0	0
GntImpliesValid_A	417041611	238282	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	238282	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2869607	0	0
ReadyAndValidImplyGrant_A	417041611	238282	0	0
ReqAndReadyImplyGrant_A	417041611	238282	0	0
ReqImpliesValid_A	417041611	609797	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	238282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2869607	0	0
T1	2244	14	0	0
T2	49420	896	0	0
T3	207379	27	0	0
T4	9069	121	0	0
T7	76039	1627	0	0
T8	13888	200	0	0
T9	2578	8	0	0
T10	2391	17	0	0
T11	247818	3619	0	0
T12	8762	159	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	609797	0	0
T1	2244	15	0	0
T2	49420	174	0	0
T3	207379	7	0	0
T4	9069	128	0	0
T7	76039	334	0	0
T8	13888	223	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	624	0	0
T12	8762	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	238282	0	0
T1	2244	14	0	0
T2	49420	111	0	0
T3	207379	7	0	0
T4	9069	124	0	0
T7	76039	232	0	0
T8	13888	211	0	0
T9	2578	7	0	0
T10	2391	16	0	0
T11	247818	489	0	0
T12	8762	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	214406	0	0
GntImpliesValid_A	417041611	214406	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	214406	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2789158	0	0
ReadyAndValidImplyGrant_A	417041611	214406	0	0
ReqAndReadyImplyGrant_A	417041611	214406	0	0
ReqImpliesValid_A	417041611	534468	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	214406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2789158	0	0
T1	2244	16	0	0
T2	49420	499	0	0
T3	207379	92	0	0
T4	9069	106	0	0
T7	76039	1843	0	0
T8	13888	228	0	0
T9	2578	14	0	0
T10	2391	9	0	0
T11	247818	3204	0	0
T12	8762	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	534468	0	0
T1	2244	15	0	0
T2	49420	140	0	0
T3	207379	14	0	0
T4	9069	123	0	0
T7	76039	372	0	0
T8	13888	255	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	475	0	0
T12	8762	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	214406	0	0
T1	2244	15	0	0
T2	49420	81	0	0
T3	207379	14	0	0
T4	9069	114	0	0
T7	76039	236	0	0
T8	13888	241	0	0
T9	2578	13	0	0
T10	2391	8	0	0
T11	247818	416	0	0
T12	8762	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	210488	0	0
GntImpliesValid_A	417041611	210488	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	210488	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2853926	0	0
ReadyAndValidImplyGrant_A	417041611	210488	0	0
ReqAndReadyImplyGrant_A	417041611	210488	0	0
ReqImpliesValid_A	417041611	526896	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	210488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2853926	0	0
T1	2244	8	0	0
T2	49420	675	0	0
T3	207379	32	0	0
T4	9069	108	0	0
T7	76039	1570	0	0
T8	13888	233	0	0
T9	2578	12	0	0
T10	2391	18	0	0
T11	247818	4165	0	0
T12	8762	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	526896	0	0
T1	2244	7	0	0
T2	49420	94	0	0
T3	207379	7	0	0
T4	9069	111	0	0
T7	76039	280	0	0
T8	13888	280	0	0
T9	2578	13	0	0
T10	2391	17	0	0
T11	247818	2246	0	0
T12	8762	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	210488	0	0
T1	2244	7	0	0
T2	49420	92	0	0
T3	207379	7	0	0
T4	9069	109	0	0
T7	76039	215	0	0
T8	13888	256	0	0
T9	2578	12	0	0
T10	2391	17	0	0
T11	247818	889	0	0
T12	8762	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	209384	0	0
GntImpliesValid_A	417041611	209384	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	209384	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2814398	0	0
ReadyAndValidImplyGrant_A	417041611	209384	0	0
ReqAndReadyImplyGrant_A	417041611	209384	0	0
ReqImpliesValid_A	417041611	517148	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	209384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2814398	0	0
T1	2244	15	0	0
T2	49420	608	0	0
T3	207379	38	0	0
T4	9069	102	0	0
T7	76039	1892	0	0
T8	13888	235	0	0
T9	2578	13	0	0
T10	2391	13	0	0
T11	247818	9128	0	0
T12	8762	136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	517148	0	0
T1	2244	14	0	0
T2	49420	86	0	0
T3	207379	8	0	0
T4	9069	109	0	0
T7	76039	335	0	0
T8	13888	258	0	0
T9	2578	16	0	0
T10	2391	14	0	0
T11	247818	4037	0	0
T12	8762	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	209384	0	0
T1	2244	14	0	0
T2	49420	83	0	0
T3	207379	8	0	0
T4	9069	105	0	0
T7	76039	231	0	0
T8	13888	246	0	0
T9	2578	14	0	0
T10	2391	13	0	0
T11	247818	1385	0	0
T12	8762	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	219276	0	0
GntImpliesValid_A	417041611	219276	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	219276	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2920213	0	0
ReadyAndValidImplyGrant_A	417041611	219276	0	0
ReqAndReadyImplyGrant_A	417041611	219276	0	0
ReqImpliesValid_A	417041611	552452	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	219276	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2920213	0	0
T1	2244	20	0	0
T2	49420	746	0	0
T3	207379	17	0	0
T4	9069	124	0	0
T7	76039	1803	0	0
T8	13888	189	0	0
T9	2578	15	0	0
T10	2391	19	0	0
T11	247818	4785	0	0
T12	8762	140	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	552452	0	0
T1	2244	21	0	0
T2	49420	109	0	0
T3	207379	3	0	0
T4	9069	149	0	0
T7	76039	329	0	0
T8	13888	216	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	4570	0	0
T12	8762	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	219276	0	0
T1	2244	20	0	0
T2	49420	98	0	0
T3	207379	3	0	0
T4	9069	136	0	0
T7	76039	246	0	0
T8	13888	202	0	0
T9	2578	14	0	0
T10	2391	18	0	0
T11	247818	909	0	0
T12	8762	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	216440	0	0
GntImpliesValid_A	417041611	216440	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	216440	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	2843679	0	0
ReadyAndValidImplyGrant_A	417041611	216440	0	0
ReqAndReadyImplyGrant_A	417041611	216440	0	0
ReqImpliesValid_A	417041611	533450	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	0	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	216440	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2843679	0	0
T1	2244	11	0	0
T2	49420	2126	0	0
T3	207379	18	0	0
T4	9069	107	0	0
T7	76039	1780	0	0
T8	13888	223	0	0
T9	2578	18	0	0
T10	2391	9	0	0
T11	247818	3446	0	0
T12	8762	173	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	533450	0	0
T1	2244	10	0	0
T2	49420	1891	0	0
T3	207379	3	0	0
T4	9069	112	0	0
T7	76039	395	0	0
T8	13888	240	0	0
T9	2578	21	0	0
T10	2391	10	0	0
T11	247818	585	0	0
T12	8762	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	216440	0	0
T1	2244	10	0	0
T2	49420	619	0	0
T3	207379	3	0	0
T4	9069	109	0	0
T7	76039	251	0	0
T8	13888	231	0	0
T9	2578	19	0	0
T10	2391	9	0	0
T11	247818	450	0	0
T12	8762	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	880345	0	0
GntImpliesValid_A	417041611	880345	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	880345	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	10698814	0	0
ReadyAndValidImplyGrant_A	417041611	880345	0	0
ReqAndReadyImplyGrant_A	417041611	880345	0	0
ReqImpliesValid_A	417041611	2193977	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	22823	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	880345	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	10698814	0	0
T1	2244	1	0	0
T2	49420	3434	0	0
T3	207379	122	0	0
T4	9069	1	0	0
T7	76039	5619	0	0
T8	13888	1	0	0
T9	2578	1	0	0
T10	2391	1	0	0
T11	247818	15472	0	0
T12	8762	703	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	2193977	0	0
T1	2244	41	0	0
T2	49420	683	0	0
T3	207379	57	0	0
T4	9069	440	0	0
T7	76039	1643	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	3630	0	0
T12	8762	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	22823	0	900
T4	9069	7	0	1
T7	76039	1	0	1
T8	13888	23	0	1
T9	2578	0	0	1
T10	2391	0	0	1
T11	247818	2	0	1
T12	8762	0	0	1
T13	9111	22	0	1
T14	465916	5	0	1
T15	69033	0	0	1
T17	0	3	0	0
T18	0	157	0	0
T19	0	2	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	880345	0	0
T1	2244	41	0	0
T2	49420	513	0	0
T3	207379	45	0	0
T4	9069	440	0	0
T7	76039	971	0	0
T8	13888	997	0	0
T9	2578	44	0	0
T10	2391	43	0	0
T11	247818	2367	0	0
T12	8762	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417041611	416927485	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	417041611	859855	0	0
GntImpliesValid_A	417041611	859855	0	0
GrantKnown_A	417041611	416927485	0	0
IdxKnown_A	417041611	416927485	0	0
IndexIsCorrect_A	417041611	859855	0	0
LockArbDecision_A	417041611	0	0	0
NoReadyValidNoGrant_A	417041611	349613949	0	0
ReadyAndValidImplyGrant_A	417041611	859855	0	0
ReqAndReadyImplyGrant_A	417041611	859855	0	0
ReqImpliesValid_A	417041611	12314780	0	0
ReqStaysHighUntilGranted0_M	417041611	0	0	0
RoundRobin_A	417041611	29169	0	900
ValidKnown_A	417041611	416927485	0	0
gen_data_port_assertion.DataFlow_A	417041611	859855	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	349613949	0	0
T1	2244	1	0	0
T2	49420	39666	0	0
T3	207379	172694	0	0
T4	9069	1	0	0
T7	76039	62843	0	0
T8	13888	1	0	0
T9	2578	1	0	0
T10	2391	1	0	0
T11	247818	209062	0	0
T12	8762	6792	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	12314780	0	0
T1	2244	41	0	0
T2	49420	4171	0	0
T3	207379	175	0	0
T4	9069	470	0	0
T7	76039	7175	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	17962	0	0
T12	8762	707	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	29169	0	900
T2	49420	1	0	1
T3	207379	0	0	1
T4	9069	11	0	1
T7	76039	0	0	1
T8	13888	10	0	1
T9	2578	0	0	1
T10	2391	0	0	1
T11	247818	1	0	1
T12	8762	0	0	1
T13	9111	7	0	1
T14	0	2	0	0
T15	0	1	0	0
T16	0	494	0	0
T17	0	7	0	0
T18	0	58	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	416927485	0	0
T1	2244	2178	0	0
T2	49420	47681	0	0
T3	207379	207331	0	0
T4	9069	9011	0	0
T7	76039	76033	0	0
T8	13888	13854	0	0
T9	2578	2504	0	0
T10	2391	2332	0	0
T11	247818	247141	0	0
T12	8762	8408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417041611	859855	0	0
T1	2244	41	0	0
T2	49420	500	0	0
T3	207379	33	0	0
T4	9069	470	0	0
T7	76039	879	0	0
T8	13888	951	0	0
T9	2578	57	0	0
T10	2391	72	0	0
T11	247818	2333	0	0
T12	8762	96	0	0