Module Definition
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Module : tlul_socket_1n
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.27 100.00 97.06 100.00 100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_s1n_57 97.92 100.00 91.67 100.00 100.00
tb.dut.u_s1n_32 98.88 100.00 95.51 100.00 100.00
tb.dut.u_s1n_27 99.65 100.00 98.61 100.00 100.00

Line Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Line Coverage for Module self-instances :
SCORELINE
99.65 100.00
tb.dut.u_s1n_27

Line No.TotalCoveredPercent
TOTAL8787100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
ALWAYS11699100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
ALWAYS18066100.00
CONT_ASSIGN18911100.00
ALWAYS19244100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24111100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 1 1
113 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
MISSING_ELSE
123 1 1
124 1 1
125 1 1
MISSING_ELSE
132 1 1
145 1 1
155 4 4
157 4 4
158 4 4
159 4 4
160 4 4
161 4 4
162 4 4
163 4 4
164 4 4
167 4 4
171 4 4
180 1 1
181 1 1
183 2 2
MISSING_ELSE
185 2 2
MISSING_ELSE
189 1 1
192 1 1
193 1 1
194 2 2
MISSING_ELSE
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
230 1 1
231 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1


Line Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Line Coverage for Module self-instances :
SCORELINE
98.88 100.00
tb.dut.u_s1n_32

SCORELINE
97.92 100.00
tb.dut.u_s1n_57

Line No.TotalCoveredPercent
TOTAL307307100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11311100.00
ALWAYS11699100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15811100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17111100.00
ALWAYS18066100.00
CONT_ASSIGN18911100.00
ALWAYS19244100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23511100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24111100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
112 1 1
113 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
121 1 1
MISSING_ELSE
123 1 1
124 1 1
125 1 1
MISSING_ELSE
132 1 1
145 1 1
155 24 24
157 24 24
158 24 24
159 24 24
160 24 24
161 24 24
162 24 24
163 24 24
164 24 24
167 24 24
171 24 24
180 1 1
181 1 1
183 2 2
MISSING_ELSE
185 2 2
MISSING_ELSE
189 1 1
192 1 1
193 1 1
194 2 2
MISSING_ELSE
197 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
230 1 1
231 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1


Cond Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Cond Coverage for Module self-instances :
SCORECOND
99.65 98.61
tb.dut.u_s1n_27

TotalCoveredPercent
Conditions727198.61
Logical727198.61
Non-Logical00
Event00

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(0))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(1))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(2))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 3'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 3'(3))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT21,T22,T23
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT11,T12,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT11,T12,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 3'(idx))
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT7,T8,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 3'(idx))
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 3'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------
-1--2--3-StatusTests
011CoveredT7,T8,T4
101CoveredT1,T2,T3
110CoveredT2,T11,T12
111CoveredT2,T7,T11

Cond Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Cond Coverage for Module self-instances :
SCORECOND
98.88 95.51
tb.dut.u_s1n_32

SCORECOND
97.92 91.67
tb.dut.u_s1n_57

TotalCoveredPercent
Conditions31229895.51
Logical31229895.51
Non-Logical00
Event00

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(0))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(1))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(2))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(3))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(4)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(4))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(5)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(5))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(6)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(6))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(7)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(7))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(8)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(8))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(9)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(9))
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(10)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(10))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(11)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(11))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(12)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(12))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(13)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(13))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(14)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(14))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(15)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(15))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(16)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(16))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(17)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(17))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(18)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(18))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(19)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(19))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(20)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(20))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(21)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(21))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(22)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(22))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 5'(23)) & ((~hold_all_requests)))
             ------------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 5'(23))
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[4].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT2,T25,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[5].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT2,T7,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[6].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[7].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[8].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT27
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[9].dev_select)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[10].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[11].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT2,T7,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[12].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[13].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[14].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT29
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[15].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[16].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[17].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT25,T30,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[18].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT2,T7,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[19].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT2,T25,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[20].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[21].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01CoveredT32
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[22].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[23].dev_select)
             -------1------   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[4].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[5].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[6].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[7].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[8].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[9].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[10].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[11].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[12].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[13].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[14].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[15].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[16].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[17].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[18].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[19].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[20].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[21].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[22].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[23].dev_select ? tl_t_o.a_user : blanked_auser)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 5'(idx))
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 5'(idx))
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 5'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T7
101CoveredT1,T2,T3
110CoveredT2,T11,T12
111CoveredT2,T8,T4

Branch Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Branch Coverage for Module self-instances :
SCOREBRANCH
99.65 100.00
tb.dut.u_s1n_27

Line No.TotalCoveredPercent
Branches 27 27 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
IF 116 5 5 100.00
IF 183 2 2 100.00
IF 185 2 2 100.00
IF 194 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 119 if (accept_t_req) -3-: 120 if ((!accept_t_rsp)) -4-: 124 if (accept_t_rsp)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Covered T1,T2,T7
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if ((dev_select_t == 3'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 if (hold_all_requests)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((dev_select_outstanding == 3'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Branch Coverage for Module self-instances :
SCOREBRANCH
98.88 100.00
tb.dut.u_s1n_32

SCOREBRANCH
97.92 100.00
tb.dut.u_s1n_57

Line No.TotalCoveredPercent
Branches 107 107 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
TERNARY 164 2 2 100.00
TERNARY 167 2 2 100.00
IF 116 5 5 100.00
IF 183 2 2 100.00
IF 185 2 2 100.00
IF 194 2 2 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[0].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[1].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[2].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[3].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[4].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[4].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[5].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[5].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[6].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[6].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[7].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[7].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[8].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[8].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[9].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[9].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[10].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[10].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[11].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[11].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[12].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[12].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[13].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[13].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[14].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[14].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[15].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[15].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[16].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[16].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[17].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[17].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[18].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[18].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[19].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[19].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[20].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[20].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[21].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[21].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[22].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[22].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 164 (gen_u_o[23].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 167 (gen_u_o[23].dev_select) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 116 if ((!rst_ni)) -2-: 119 if (accept_t_req) -3-: 120 if ((!accept_t_rsp)) -4-: 124 if (accept_t_rsp)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 - Covered T2,T7,T8
0 0 - 1 Covered T1,T2,T3
0 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 183 if ((dev_select_t == 5'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 if (hold_all_requests)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((dev_select_outstanding == 5'(idx)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_socket_1n
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NotOverflowed_A 1251124833 1250782455 0 0
maxN 2700 2700 0 0


NotOverflowed_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1251124833 1250782455 0 0
T1 6732 6534 0 0
T2 148260 143043 0 0
T3 622137 621993 0 0
T4 27207 27033 0 0
T7 228117 228099 0 0
T8 41664 41562 0 0
T9 7734 7512 0 0
T10 7173 6996 0 0
T11 743454 741423 0 0
T12 26286 25224 0 0

maxN
NameAttemptsReal SuccessesFailuresIncomplete
Total 2700 2700 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T9 3 3 0 0
T10 3 3 0 0
T11 3 3 0 0
T12 3 3 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%