Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1449759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

230330

1

T1

217

T2

14

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	570477	1			T1	534		T2	56		T3	35
values[0x0]	537739	1			T1	506		T2	54		T3	30
values[0x1]	571873	1			T1	562		T2	55		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1120184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

559905

1

T1

546

T2

54

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26770	1			T1	65		T3	1		T7	1
valid_sources[0x01]	26329	1			T1	9		T2	27		T3	8
valid_sources[0x02]	26931	1			T1	57		T2	10		T3	3
valid_sources[0x03]	25172	1			T1	35		T7	16		T8	23
valid_sources[0x04]	25830	1			T1	17		T2	7		T7	1
valid_sources[0x05]	25374	1			T1	10		T3	2		T7	43
valid_sources[0x06]	26064	1			T1	4		T7	53		T8	36
valid_sources[0x07]	26583	1			T1	7		T7	10		T9	2
valid_sources[0x08]	26369	1			T1	58		T3	1		T7	97
valid_sources[0x09]	26276	1			T1	11		T7	9		T8	17
valid_sources[0x0a]	27238	1			T1	29		T2	1		T8	15
valid_sources[0x0b]	25896	1			T1	12		T3	9		T7	14
valid_sources[0x0c]	25912	1			T1	5		T2	3		T8	14
valid_sources[0x0d]	26519	1			T1	28		T7	32		T8	52
valid_sources[0x0e]	26049	1			T1	17		T7	4		T8	44
valid_sources[0x0f]	26653	1			T1	21		T2	10		T3	1
valid_sources[0x10]	26362	1			T1	23		T3	1		T7	14
valid_sources[0x11]	25331	1			T1	4		T7	45		T8	44
valid_sources[0x12]	26734	1			T1	22		T3	3		T7	11
valid_sources[0x13]	25747	1			T1	21		T3	2		T7	64
valid_sources[0x14]	26456	1			T1	32		T2	1		T7	3
valid_sources[0x15]	26301	1			T1	6		T3	5		T7	44
valid_sources[0x16]	26137	1			T1	29		T7	20		T8	30
valid_sources[0x17]	26293	1			T1	47		T3	3		T7	7
valid_sources[0x18]	27295	1			T1	16		T7	3		T8	28
valid_sources[0x19]	27226	1			T1	60		T2	2		T7	40
valid_sources[0x1a]	26422	1			T1	23		T7	79		T8	30
valid_sources[0x1b]	25826	1			T1	48		T2	14		T7	30
valid_sources[0x1c]	26998	1			T1	41		T7	45		T8	13
valid_sources[0x1d]	26490	1			T1	23		T3	3		T7	4
valid_sources[0x1e]	26233	1			T1	10		T3	1		T7	34
valid_sources[0x1f]	25633	1			T1	21		T3	2		T7	21
valid_sources[0x20]	25270	1			T1	13		T7	4		T8	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24279

1

T1

22

T2

2

T3

1

values[0x0]

all_enables

biggest_size

181616

1

T1

174

T2

11

T3

9

values[0x1]

all_enables

biggest_size

24435

1

T1

21

T2

1

T7

28

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1463718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

237424

1

T1

213

T2

26

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	582646	1			T1	534		T2	46		T3	32
values[0x0]	535403	1			T1	492		T2	55		T3	39
values[0x1]	583093	1			T1	573		T2	35		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1123313	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

577829

1

T1

499

T2

55

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25976	1			T1	32		T2	4		T3	7
valid_sources[0x01]	26962	1			T1	26		T3	4		T7	16
valid_sources[0x02]	26178	1			T1	29		T3	1		T7	32
valid_sources[0x03]	25894	1			T1	28		T3	2		T7	12
valid_sources[0x04]	26982	1			T1	17		T2	2		T3	2
valid_sources[0x05]	26734	1			T1	30		T3	3		T7	58
valid_sources[0x06]	25993	1			T1	28		T2	2		T7	18
valid_sources[0x07]	25830	1			T1	24		T2	6		T7	34
valid_sources[0x08]	27186	1			T1	31		T7	24		T8	13
valid_sources[0x09]	27363	1			T1	24		T2	12		T3	3
valid_sources[0x0a]	27049	1			T1	40		T7	34		T8	13
valid_sources[0x0b]	27039	1			T1	24		T2	2		T7	20
valid_sources[0x0c]	26854	1			T1	21		T2	1		T7	43
valid_sources[0x0d]	27217	1			T1	25		T2	4		T3	2
valid_sources[0x0e]	26814	1			T1	15		T3	4		T7	14
valid_sources[0x0f]	27018	1			T1	34		T2	5		T3	2
valid_sources[0x10]	26164	1			T1	27		T2	2		T3	1
valid_sources[0x11]	26258	1			T1	25		T2	12		T3	3
valid_sources[0x12]	26879	1			T1	30		T7	27		T8	42
valid_sources[0x13]	26257	1			T1	22		T3	3		T7	13
valid_sources[0x14]	27257	1			T1	30		T7	38		T8	12
valid_sources[0x15]	26239	1			T1	30		T3	3		T7	25
valid_sources[0x16]	26355	1			T1	18		T7	21		T8	41
valid_sources[0x17]	26506	1			T1	20		T7	12		T8	14
valid_sources[0x18]	26948	1			T1	35		T2	5		T3	2
valid_sources[0x19]	26285	1			T1	26		T3	3		T7	12
valid_sources[0x1a]	26086	1			T1	20		T2	2		T3	4
valid_sources[0x1b]	27154	1			T1	22		T7	20		T8	9
valid_sources[0x1c]	27181	1			T1	28		T2	2		T7	32
valid_sources[0x1d]	26451	1			T1	22		T7	25		T8	40
valid_sources[0x1e]	26227	1			T1	25		T2	1		T3	1
valid_sources[0x1f]	26356	1			T1	22		T2	11		T7	24
valid_sources[0x20]	27234	1			T1	28		T7	19		T8	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25054

1

T1

18

T2

2

T3

3

values[0x0]

all_enables

biggest_size

187444

1

T1

174

T2

23

T3

18

values[0x1]

all_enables

biggest_size

24926

1

T1

21

T2

1

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231774

1

T1

204

T2

24

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	573768	1			T1	555		T2	62		T3	63
values[0x0]	543119	1			T1	532		T2	52		T3	47
values[0x1]	574047	1			T1	501		T2	75		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

562683

1

T1

523

T2

58

T3

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27363	1			T1	1		T3	3		T7	20
valid_sources[0x01]	26148	1			T1	19		T3	2		T7	36
valid_sources[0x02]	25224	1			T1	6		T3	3		T7	32
valid_sources[0x03]	26029	1			T1	45		T2	13		T3	3
valid_sources[0x04]	26776	1			T1	8		T3	2		T7	11
valid_sources[0x05]	27381	1			T1	29		T3	2		T7	14
valid_sources[0x06]	25953	1			T1	21		T3	2		T7	15
valid_sources[0x07]	25723	1			T1	57		T3	3		T7	34
valid_sources[0x08]	27059	1			T1	29		T3	1		T7	29
valid_sources[0x09]	26285	1			T1	13		T3	3		T7	43
valid_sources[0x0a]	26570	1			T1	14		T3	3		T7	20
valid_sources[0x0b]	25535	1			T1	19		T3	2		T7	19
valid_sources[0x0c]	26468	1			T1	36		T3	2		T7	24
valid_sources[0x0d]	27125	1			T1	36		T3	3		T7	31
valid_sources[0x0e]	25645	1			T1	43		T3	7		T7	23
valid_sources[0x0f]	26307	1			T1	28		T2	2		T3	3
valid_sources[0x10]	25949	1			T1	39		T3	1		T7	38
valid_sources[0x11]	26493	1			T1	12		T7	22		T8	26
valid_sources[0x12]	26897	1			T1	32		T3	2		T7	33
valid_sources[0x13]	26451	1			T1	30		T2	5		T3	7
valid_sources[0x14]	26349	1			T1	1		T3	4		T7	29
valid_sources[0x15]	26824	1			T1	8		T3	2		T7	28
valid_sources[0x16]	27130	1			T1	40		T2	33		T3	1
valid_sources[0x17]	26451	1			T1	79		T3	2		T7	25
valid_sources[0x18]	26505	1			T1	14		T2	13		T3	2
valid_sources[0x19]	26563	1			T1	47		T2	17		T3	1
valid_sources[0x1a]	26805	1			T1	30		T3	2		T7	34
valid_sources[0x1b]	26558	1			T1	29		T3	3		T7	25
valid_sources[0x1c]	26535	1			T1	31		T3	2		T7	20
valid_sources[0x1d]	26531	1			T1	10		T3	1		T7	13
valid_sources[0x1e]	26732	1			T1	13		T2	18		T3	1
valid_sources[0x1f]	26059	1			T1	26		T3	2		T7	15
valid_sources[0x20]	25964	1			T1	41		T3	3		T7	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24275

1

T1

20

T2

3

T3

1

values[0x0]

all_enables

biggest_size

182908

1

T1

167

T2

15

T3

10

values[0x1]

all_enables

biggest_size

24591

1

T1

17

T2

6

T3

2