Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7708142	0	0
GntImpliesValid_A	2147483647	7708142	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7708142	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	458236320	0	0
ReadyAndValidImplyGrant_A	2147483647	7708142	0	0
ReqAndReadyImplyGrant_A	2147483647	7708142	0	0
ReqImpliesValid_A	2147483647	33330942	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	55934	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7708142	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4111920	4111776	0	0
T2	48912	48384	0	0
T3	5883720	5883336	0	0
T4	2896896	2895456	0	0
T7	1142256	1141728	0	0
T8	1102416	1100760	0	0
T9	8044584	8044128	0	0
T10	267312	266712	0	0
T11	1255896	1255608	0	0
T12	207000	206592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4111920	4111776	0	0
T2	48912	48384	0	0
T3	5883720	5883336	0	0
T4	2896896	2895456	0	0
T7	1142256	1141728	0	0
T8	1102416	1100760	0	0
T9	8044584	8044128	0	0
T10	267312	266712	0	0
T11	1255896	1255608	0	0
T12	207000	206592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4111920	4111776	0	0
T2	48912	48384	0	0
T3	5883720	5883336	0	0
T4	2896896	2895456	0	0
T7	1142256	1141728	0	0
T8	1102416	1100760	0	0
T9	8044584	8044128	0	0
T10	267312	266712	0	0
T11	1255896	1255608	0	0
T12	207000	206592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	458236320	0	0
T1	4111920	165390	0	0
T2	48912	585	0	0
T3	5883720	205590	0	0
T4	2896896	123048	0	0
T7	1142256	70294	0	0
T8	1102416	77032	0	0
T9	8044584	442870	0	0
T10	267312	6542	0	0
T11	1255896	71310	0	0
T12	207000	10088	0	0
T13	0	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33330942	0	0
T1	4111920	8183	0	0
T2	48912	543	0	0
T3	5883720	537	0	0
T4	2896896	81547	0	0
T7	1142256	11561	0	0
T8	1102416	10709	0	0
T9	8044584	61278	0	0
T10	267312	5310	0	0
T11	1255896	8170	0	0
T12	207000	821	0	0
T13	0	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55934	0	21600
T4	241408	153	0	2
T7	47594	2	0	1
T8	45934	0	0	1
T9	670382	7	0	2
T10	22276	14	0	2
T11	104658	2	0	2
T12	17250	0	0	2
T13	536554	0	0	2
T14	22208	9	0	2
T15	181831	4	0	1
T16	0	10	0	0
T17	0	6	0	0
T18	0	25	0	0
T19	0	15	0	0
T20	625524	0	0	2
T21	52677	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4111920	4111776	0	0
T2	48912	48384	0	0
T3	5883720	5883336	0	0
T4	2896896	2895456	0	0
T7	1142256	1141728	0	0
T8	1102416	1100760	0	0
T9	8044584	8044128	0	0
T10	267312	266712	0	0
T11	1255896	1255608	0	0
T12	207000	206592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7708142	0	0
T1	4111920	4788	0	0
T2	48912	490	0	0
T3	5883720	332	0	0
T4	2896896	9734	0	0
T7	1142256	4994	0	0
T8	1102416	4296	0	0
T9	8044584	26237	0	0
T10	267312	5037	0	0
T11	1255896	4001	0	0
T12	207000	390	0	0
T13	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	850963	0	0
GntImpliesValid_A	427896015	850963	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	850963	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	11302031	0	0
ReadyAndValidImplyGrant_A	427896015	850963	0	0
ReqAndReadyImplyGrant_A	427896015	850963	0	0
ReqImpliesValid_A	427896015	2298225	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	850963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	11302031	0	0
T1	171330	2138	0	0
T2	2038	42	0	0
T3	245155	159	0	0
T4	120704	5152	0	0
T7	47594	4379	0	0
T8	45934	3737	0	0
T9	335191	23648	0	0
T10	11138	552	0	0
T11	52329	3282	0	0
T12	8625	273	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2298225	0	0
T1	171330	701	0	0
T2	2038	71	0	0
T3	245155	43	0	0
T4	120704	1166	0	0
T7	47594	1130	0	0
T8	45934	911	0	0
T9	335191	6595	0	0
T10	11138	675	0	0
T11	52329	624	0	0
T12	8625	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	850963	0	0
T1	171330	518	0	0
T2	2038	56	0	0
T3	245155	35	0	0
T4	120704	699	0	0
T7	47594	573	0	0
T8	45934	504	0	0
T9	335191	3289	0	0
T10	11138	613	0	0
T11	52329	449	0	0
T12	8625	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	865688	0	0
GntImpliesValid_A	427896015	865688	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	865688	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	11624727	0	0
ReadyAndValidImplyGrant_A	427896015	865688	0	0
ReqAndReadyImplyGrant_A	427896015	865688	0	0
ReqImpliesValid_A	427896015	2468719	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	865688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	11624727	0	0
T1	171330	2237	0	0
T2	2038	36	0	0
T3	245155	112	0	0
T4	120704	4893	0	0
T7	47594	3897	0	0
T8	45934	3343	0	0
T9	335191	23503	0	0
T10	11138	508	0	0
T11	52329	3310	0	0
T12	8625	293	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2468719	0	0
T1	171330	798	0	0
T2	2038	57	0	0
T3	245155	35	0	0
T4	120704	1177	0	0
T7	47594	1062	0	0
T8	45934	883	0	0
T9	335191	6910	0	0
T10	11138	599	0	0
T11	52329	744	0	0
T12	8625	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	865688	0	0
T1	171330	545	0	0
T2	2038	46	0	0
T3	245155	27	0	0
T4	120704	684	0	0
T7	47594	541	0	0
T8	45934	504	0	0
T9	335191	3271	0	0
T10	11138	553	0	0
T11	52329	442	0	0
T12	8625	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	223335	0	0
GntImpliesValid_A	427896015	223335	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	223335	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2849974	0	0
ReadyAndValidImplyGrant_A	427896015	223335	0	0
ReqAndReadyImplyGrant_A	427896015	223335	0	0
ReqImpliesValid_A	427896015	588691	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	223335	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2849974	0	0
T1	171330	499	0	0
T2	2038	17	0	0
T3	245155	39	0	0
T4	120704	1	0	0
T7	47594	1167	0	0
T8	45934	873	0	0
T9	335191	4402	0	0
T10	11138	139	0	0
T11	52329	671	0	0
T12	8625	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	588691	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	272	0	0
T8	45934	173	0	0
T9	335191	665	0	0
T10	11138	142	0	0
T11	52329	116	0	0
T12	8625	9	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	223335	0	0
T1	171330	123	0	0
T2	2038	16	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	105	0	0
T9	335191	590	0	0
T10	11138	140	0	0
T11	52329	88	0	0
T12	8625	9	0	0
T13	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	220529	0	0
GntImpliesValid_A	427896015	220529	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	220529	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2784584	0	0
ReadyAndValidImplyGrant_A	427896015	220529	0	0
ReqAndReadyImplyGrant_A	427896015	220529	0	0
ReqImpliesValid_A	427896015	609444	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	220529	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2784584	0	0
T1	171330	567	0	0
T2	2038	20	0	0
T3	245155	36	0	0
T4	120704	933	0	0
T7	47594	1023	0	0
T8	45934	980	0	0
T9	335191	4672	0	0
T10	11138	126	0	0
T11	52329	933	0	0
T12	8625	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	609444	0	0
T1	171330	198	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	5150	0	0
T7	47594	215	0	0
T8	45934	189	0	0
T9	335191	727	0	0
T10	11138	129	0	0
T11	52329	202	0	0
T12	8625	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	220529	0	0
T1	171330	137	0	0
T2	2038	19	0	0
T3	245155	11	0	0
T4	120704	549	0	0
T7	47594	127	0	0
T8	45934	139	0	0
T9	335191	609	0	0
T10	11138	127	0	0
T11	52329	128	0	0
T12	8625	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	216552	0	0
GntImpliesValid_A	427896015	216552	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	216552	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	5447527	0	0
ReadyAndValidImplyGrant_A	427896015	216552	0	0
ReqAndReadyImplyGrant_A	427896015	216552	0	0
ReqImpliesValid_A	427896015	1244476	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	216552	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	5447527	0	0
T1	171330	1026	0	0
T2	2038	99	0	0
T3	245155	65	0	0
T4	120704	1108	0	0
T7	47594	1358	0	0
T8	45934	2340	0	0
T9	335191	3405	0	0
T10	11138	930	0	0
T11	52329	676	0	0
T12	8625	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	1244476	0	0
T1	171330	221	0	0
T2	2038	25	0	0
T3	245155	8	0	0
T4	120704	8459	0	0
T7	47594	225	0	0
T8	45934	332	0	0
T9	335191	685	0	0
T10	11138	195	0	0
T11	52329	172	0	0
T12	8625	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	216552	0	0
T1	171330	142	0	0
T2	2038	18	0	0
T3	245155	8	0	0
T4	120704	397	0	0
T7	47594	145	0	0
T8	45934	111	0	0
T9	335191	651	0	0
T10	11138	161	0	0
T11	52329	135	0	0
T12	8625	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	198647	0	0
GntImpliesValid_A	427896015	198647	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	198647	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	4495442	0	0
ReadyAndValidImplyGrant_A	427896015	198647	0	0
ReqAndReadyImplyGrant_A	427896015	198647	0	0
ReqImpliesValid_A	427896015	979006	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	198647	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	4495442	0	0
T1	171330	2278	0	0
T2	2038	51	0	0
T3	245155	41	0	0
T4	120704	356	0	0
T7	47594	1783	0	0
T8	45934	4959	0	0
T9	335191	7981	0	0
T10	11138	659	0	0
T11	52329	569	0	0
T12	8625	109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	979006	0	0
T1	171330	278	0	0
T2	2038	16	0	0
T3	245155	5	0	0
T4	120704	27351	0	0
T7	47594	244	0	0
T8	45934	433	0	0
T9	335191	1739	0	0
T10	11138	182	0	0
T11	52329	114	0	0
T12	8625	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	198647	0	0
T1	171330	119	0	0
T2	2038	11	0	0
T3	245155	5	0	0
T4	120704	544	0	0
T7	47594	135	0	0
T8	45934	115	0	0
T9	335191	1033	0	0
T10	11138	154	0	0
T11	52329	95	0	0
T12	8625	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	196525	0	0
GntImpliesValid_A	427896015	196525	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	196525	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	5621236	0	0
ReadyAndValidImplyGrant_A	427896015	196525	0	0
ReqAndReadyImplyGrant_A	427896015	196525	0	0
ReqImpliesValid_A	427896015	1234165	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	196525	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	5621236	0	0
T1	171330	3515	0	0
T2	2038	63	0	0
T3	245155	154	0	0
T4	120704	0	0	0
T7	47594	955	0	0
T8	45934	4579	0	0
T9	335191	3127	0	0
T10	11138	1160	0	0
T11	52329	1573	0	0
T12	8625	105	0	0
T13	0	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	1234165	0	0
T1	171330	414	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	198	0	0
T8	45934	301	0	0
T9	335191	697	0	0
T10	11138	183	0	0
T11	52329	192	0	0
T12	8625	29	0	0
T13	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	196525	0	0
T1	171330	128	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	135	0	0
T8	45934	113	0	0
T9	335191	639	0	0
T10	11138	151	0	0
T11	52329	108	0	0
T12	8625	22	0	0
T13	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	213253	0	0
GntImpliesValid_A	427896015	213253	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	213253	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	5054444	0	0
ReadyAndValidImplyGrant_A	427896015	213253	0	0
ReqAndReadyImplyGrant_A	427896015	213253	0	0
ReqImpliesValid_A	427896015	1152575	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	213253	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	5054444	0	0
T1	171330	877	0	0
T2	2038	47	0	0
T3	245155	114	0	0
T4	120704	0	0	0
T7	47594	648	0	0
T8	45934	2378	0	0
T9	335191	3996	0	0
T10	11138	521	0	0
T11	52329	503	0	0
T12	8625	130	0	0
T13	0	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	1152575	0	0
T1	171330	195	0	0
T2	2038	22	0	0
T3	245155	23	0	0
T4	120704	0	0	0
T7	47594	127	0	0
T8	45934	330	0	0
T9	335191	706	0	0
T10	11138	153	0	0
T11	52329	98	0	0
T12	8625	12	0	0
T13	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213253	0	0
T1	171330	129	0	0
T2	2038	13	0	0
T3	245155	10	0	0
T4	120704	0	0	0
T7	47594	120	0	0
T8	45934	115	0	0
T9	335191	643	0	0
T10	11138	130	0	0
T11	52329	93	0	0
T12	8625	12	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	212364	0	0
GntImpliesValid_A	427896015	212364	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	212364	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2870078	0	0
ReadyAndValidImplyGrant_A	427896015	212364	0	0
ReqAndReadyImplyGrant_A	427896015	212364	0	0
ReqImpliesValid_A	427896015	601712	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	212364	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2870078	0	0
T1	171330	563	0	0
T2	2038	14	0	0
T3	245155	32	0	0
T4	120704	1	0	0
T7	47594	1021	0	0
T8	45934	967	0	0
T9	335191	4833	0	0
T10	11138	147	0	0
T11	52329	851	0	0
T12	8625	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	601712	0	0
T1	171330	129	0	0
T2	2038	17	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	213	0	0
T8	45934	210	0	0
T9	335191	742	0	0
T10	11138	152	0	0
T11	52329	149	0	0
T12	8625	21	0	0
T13	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212364	0	0
T1	171330	122	0	0
T2	2038	15	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	145	0	0
T8	45934	130	0	0
T9	335191	638	0	0
T10	11138	149	0	0
T11	52329	104	0	0
T12	8625	13	0	0
T13	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	231633	0	0
GntImpliesValid_A	427896015	231633	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	231633	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2780616	0	0
ReadyAndValidImplyGrant_A	427896015	231633	0	0
ReqAndReadyImplyGrant_A	427896015	231633	0	0
ReqImpliesValid_A	427896015	663699	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	231633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2780616	0	0
T1	171330	586	0	0
T2	2038	21	0	0
T3	245155	42	0	0
T4	120704	1	0	0
T7	47594	1039	0	0
T8	45934	878	0	0
T9	335191	4898	0	0
T10	11138	136	0	0
T11	52329	759	0	0
T12	8625	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	663699	0	0
T1	171330	138	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	159	0	0
T8	45934	184	0	0
T9	335191	717	0	0
T10	11138	141	0	0
T11	52329	140	0	0
T12	8625	26	0	0
T13	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	231633	0	0
T1	171330	128	0	0
T2	2038	20	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	113	0	0
T9	335191	647	0	0
T10	11138	138	0	0
T11	52329	108	0	0
T12	8625	11	0	0
T13	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	213423	0	0
GntImpliesValid_A	427896015	213423	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	213423	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2835003	0	0
ReadyAndValidImplyGrant_A	427896015	213423	0	0
ReqAndReadyImplyGrant_A	427896015	213423	0	0
ReqImpliesValid_A	427896015	590306	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	213423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2835003	0	0
T1	171330	633	0	0
T2	2038	15	0	0
T3	245155	31	0	0
T4	120704	2000	0	0
T7	47594	999	0	0
T8	45934	937	0	0
T9	335191	4501	0	0
T10	11138	135	0	0
T11	52329	840	0	0
T12	8625	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	590306	0	0
T1	171330	175	0	0
T2	2038	16	0	0
T3	245155	6	0	0
T4	120704	3927	0	0
T7	47594	220	0	0
T8	45934	181	0	0
T9	335191	614	0	0
T10	11138	136	0	0
T11	52329	165	0	0
T12	8625	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213423	0	0
T1	171330	138	0	0
T2	2038	15	0	0
T3	245155	6	0	0
T4	120704	948	0	0
T7	47594	134	0	0
T8	45934	135	0	0
T9	335191	584	0	0
T10	11138	135	0	0
T11	52329	126	0	0
T12	8625	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	209626	0	0
GntImpliesValid_A	427896015	209626	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	209626	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2731954	0	0
ReadyAndValidImplyGrant_A	427896015	209626	0	0
ReqAndReadyImplyGrant_A	427896015	209626	0	0
ReqImpliesValid_A	427896015	507198	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	209626	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2731954	0	0
T1	171330	532	0	0
T2	2038	9	0	0
T3	245155	86	0	0
T4	120704	934	0	0
T7	47594	1039	0	0
T8	45934	848	0	0
T9	335191	4536	0	0
T10	11138	134	0	0
T11	52329	901	0	0
T12	8625	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	507198	0	0
T1	171330	157	0	0
T2	2038	8	0	0
T3	245155	25	0	0
T4	120704	1427	0	0
T7	47594	230	0	0
T8	45934	144	0	0
T9	335191	682	0	0
T10	11138	143	0	0
T11	52329	172	0	0
T12	8625	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	209626	0	0
T1	171330	132	0	0
T2	2038	8	0	0
T3	245155	18	0	0
T4	120704	433	0	0
T7	47594	148	0	0
T8	45934	108	0	0
T9	335191	633	0	0
T10	11138	138	0	0
T11	52329	112	0	0
T12	8625	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	213452	0	0
GntImpliesValid_A	427896015	213452	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	213452	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2749421	0	0
ReadyAndValidImplyGrant_A	427896015	213452	0	0
ReqAndReadyImplyGrant_A	427896015	213452	0	0
ReqImpliesValid_A	427896015	622797	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	213452	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2749421	0	0
T1	171330	476	0	0
T2	2038	17	0	0
T3	245155	35	0	0
T4	120704	1	0	0
T7	47594	1012	0	0
T8	45934	955	0	0
T9	335191	4997	0	0
T10	11138	127	0	0
T11	52329	919	0	0
T12	8625	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	622797	0	0
T1	171330	152	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	240	0	0
T8	45934	183	0	0
T9	335191	666	0	0
T10	11138	130	0	0
T11	52329	145	0	0
T12	8625	15	0	0
T13	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213452	0	0
T1	171330	120	0	0
T2	2038	16	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	146	0	0
T8	45934	128	0	0
T9	335191	639	0	0
T10	11138	128	0	0
T11	52329	120	0	0
T12	8625	15	0	0
T13	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	213521	0	0
GntImpliesValid_A	427896015	213521	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	213521	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2798515	0	0
ReadyAndValidImplyGrant_A	427896015	213521	0	0
ReqAndReadyImplyGrant_A	427896015	213521	0	0
ReqImpliesValid_A	427896015	562963	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	213521	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2798515	0	0
T1	171330	630	0	0
T2	2038	19	0	0
T3	245155	37	0	0
T4	120704	1947	0	0
T7	47594	1072	0	0
T8	45934	910	0	0
T9	335191	4964	0	0
T10	11138	139	0	0
T11	52329	944	0	0
T12	8625	136	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	562963	0	0
T1	171330	182	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	16168	0	0
T7	47594	193	0	0
T8	45934	166	0	0
T9	335191	658	0	0
T10	11138	142	0	0
T11	52329	125	0	0
T12	8625	26	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	213521	0	0
T1	171330	145	0	0
T2	2038	18	0	0
T3	245155	10	0	0
T4	120704	1563	0	0
T7	47594	153	0	0
T8	45934	118	0	0
T9	335191	610	0	0
T10	11138	140	0	0
T11	52329	121	0	0
T12	8625	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	207731	0	0
GntImpliesValid_A	427896015	207731	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	207731	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2762424	0	0
ReadyAndValidImplyGrant_A	427896015	207731	0	0
ReqAndReadyImplyGrant_A	427896015	207731	0	0
ReqImpliesValid_A	427896015	549902	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	207731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2762424	0	0
T1	171330	542	0	0
T2	2038	15	0	0
T3	245155	36	0	0
T4	120704	1	0	0
T7	47594	1025	0	0
T8	45934	882	0	0
T9	335191	4847	0	0
T10	11138	137	0	0
T11	52329	723	0	0
T12	8625	114	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	549902	0	0
T1	171330	143	0	0
T2	2038	14	0	0
T3	245155	12	0	0
T4	120704	0	0	0
T7	47594	200	0	0
T8	45934	123	0	0
T9	335191	675	0	0
T10	11138	146	0	0
T11	52329	96	0	0
T12	8625	20	0	0
T13	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207731	0	0
T1	171330	124	0	0
T2	2038	14	0	0
T3	245155	9	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	108	0	0
T9	335191	624	0	0
T10	11138	141	0	0
T11	52329	88	0	0
T12	8625	10	0	0
T13	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	204573	0	0
GntImpliesValid_A	427896015	204573	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	204573	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2810977	0	0
ReadyAndValidImplyGrant_A	427896015	204573	0	0
ReqAndReadyImplyGrant_A	427896015	204573	0	0
ReqImpliesValid_A	427896015	506844	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	204573	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2810977	0	0
T1	171330	585	0	0
T2	2038	17	0	0
T3	245155	68	0	0
T4	120704	1	0	0
T7	47594	1047	0	0
T8	45934	841	0	0
T9	335191	5004	0	0
T10	11138	130	0	0
T11	52329	920	0	0
T12	8625	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	506844	0	0
T1	171330	150	0	0
T2	2038	16	0	0
T3	245155	17	0	0
T4	120704	0	0	0
T7	47594	156	0	0
T8	45934	168	0	0
T9	335191	700	0	0
T10	11138	129	0	0
T11	52329	149	0	0
T12	8625	8	0	0
T13	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	204573	0	0
T1	171330	140	0	0
T2	2038	16	0	0
T3	245155	16	0	0
T4	120704	0	0	0
T7	47594	131	0	0
T8	45934	107	0	0
T9	335191	629	0	0
T10	11138	129	0	0
T11	52329	121	0	0
T12	8625	8	0	0
T13	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	239752	0	0
GntImpliesValid_A	427896015	239752	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	239752	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2937269	0	0
ReadyAndValidImplyGrant_A	427896015	239752	0	0
ReqAndReadyImplyGrant_A	427896015	239752	0	0
ReqImpliesValid_A	427896015	608089	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	239752	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2937269	0	0
T1	171330	468	0	0
T2	2038	13	0	0
T3	245155	39	0	0
T4	120704	1	0	0
T7	47594	1137	0	0
T8	45934	908	0	0
T9	335191	6383	0	0
T10	11138	179	0	0
T11	52329	1311	0	0
T12	8625	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	608089	0	0
T1	171330	140	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	189	0	0
T8	45934	143	0	0
T9	335191	1068	0	0
T10	11138	196	0	0
T11	52329	267	0	0
T12	8625	43	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	239752	0	0
T1	171330	114	0	0
T2	2038	12	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	142	0	0
T8	45934	110	0	0
T9	335191	831	0	0
T10	11138	187	0	0
T11	52329	187	0	0
T12	8625	12	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	202799	0	0
GntImpliesValid_A	427896015	202799	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	202799	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2766256	0	0
ReadyAndValidImplyGrant_A	427896015	202799	0	0
ReqAndReadyImplyGrant_A	427896015	202799	0	0
ReqImpliesValid_A	427896015	496036	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	202799	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2766256	0	0
T1	171330	552	0	0
T2	2038	14	0	0
T3	245155	16	0	0
T4	120704	1	0	0
T7	47594	808	0	0
T8	45934	870	0	0
T9	335191	4577	0	0
T10	11138	115	0	0
T11	52329	836	0	0
T12	8625	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	496036	0	0
T1	171330	146	0	0
T2	2038	13	0	0
T3	245155	8	0	0
T4	120704	0	0	0
T7	47594	166	0	0
T8	45934	138	0	0
T9	335191	722	0	0
T10	11138	120	0	0
T11	52329	188	0	0
T12	8625	8	0	0
T13	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	202799	0	0
T1	171330	127	0	0
T2	2038	13	0	0
T3	245155	5	0	0
T4	120704	0	0	0
T7	47594	121	0	0
T8	45934	110	0	0
T9	335191	615	0	0
T10	11138	117	0	0
T11	52329	115	0	0
T12	8625	8	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	207909	0	0
GntImpliesValid_A	427896015	207909	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	207909	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2875351	0	0
ReadyAndValidImplyGrant_A	427896015	207909	0	0
ReqAndReadyImplyGrant_A	427896015	207909	0	0
ReqImpliesValid_A	427896015	558659	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	207909	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2875351	0	0
T1	171330	519	0	0
T2	2038	18	0	0
T3	245155	15	0	0
T4	120704	1	0	0
T7	47594	1194	0	0
T8	45934	636	0	0
T9	335191	4612	0	0
T10	11138	125	0	0
T11	52329	778	0	0
T12	8625	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	558659	0	0
T1	171330	160	0	0
T2	2038	19	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	165	0	0
T8	45934	146	0	0
T9	335191	655	0	0
T10	11138	128	0	0
T11	52329	111	0	0
T12	8625	9	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207909	0	0
T1	171330	122	0	0
T2	2038	18	0	0
T3	245155	7	0	0
T4	120704	0	0	0
T7	47594	140	0	0
T8	45934	97	0	0
T9	335191	623	0	0
T10	11138	126	0	0
T11	52329	100	0	0
T12	8625	9	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	212641	0	0
GntImpliesValid_A	427896015	212641	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	212641	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2755476	0	0
ReadyAndValidImplyGrant_A	427896015	212641	0	0
ReqAndReadyImplyGrant_A	427896015	212641	0	0
ReqImpliesValid_A	427896015	564890	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	212641	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2755476	0	0
T1	171330	598	0	0
T2	2038	14	0	0
T3	245155	50	0	0
T4	120704	1	0	0
T7	47594	1008	0	0
T8	45934	860	0	0
T9	335191	5028	0	0
T10	11138	133	0	0
T11	52329	824	0	0
T12	8625	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	564890	0	0
T1	171330	186	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	173	0	0
T8	45934	229	0	0
T9	335191	789	0	0
T10	11138	138	0	0
T11	52329	134	0	0
T12	8625	16	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	212641	0	0
T1	171330	153	0	0
T2	2038	13	0	0
T3	245155	13	0	0
T4	120704	0	0	0
T7	47594	136	0	0
T8	45934	124	0	0
T9	335191	649	0	0
T10	11138	135	0	0
T11	52329	108	0	0
T12	8625	13	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	208980	0	0
GntImpliesValid_A	427896015	208980	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	208980	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2712945	0	0
ReadyAndValidImplyGrant_A	427896015	208980	0	0
ReqAndReadyImplyGrant_A	427896015	208980	0	0
ReqImpliesValid_A	427896015	517960	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	208980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2712945	0	0
T1	171330	587	0	0
T2	2038	11	0	0
T3	245155	29	0	0
T4	120704	1287	0	0
T7	47594	852	0	0
T8	45934	979	0	0
T9	335191	6637	0	0
T10	11138	165	0	0
T11	52329	866	0	0
T12	8625	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	517960	0	0
T1	171330	168	0	0
T2	2038	14	0	0
T3	245155	13	0	0
T4	120704	2210	0	0
T7	47594	153	0	0
T8	45934	189	0	0
T9	335191	2098	0	0
T10	11138	168	0	0
T11	52329	142	0	0
T12	8625	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	208980	0	0
T1	171330	143	0	0
T2	2038	12	0	0
T3	245155	8	0	0
T4	120704	558	0	0
T7	47594	121	0	0
T8	45934	125	0	0
T9	335191	1109	0	0
T10	11138	166	0	0
T11	52329	114	0	0
T12	8625	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	207217	0	0
GntImpliesValid_A	427896015	207217	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	207217	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	2746251	0	0
ReadyAndValidImplyGrant_A	427896015	207217	0	0
ReqAndReadyImplyGrant_A	427896015	207217	0	0
ReqImpliesValid_A	427896015	546077	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	0	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	207217	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2746251	0	0
T1	171330	573	0	0
T2	2038	11	0	0
T3	245155	69	0	0
T4	120704	843	0	0
T7	47594	962	0	0
T8	45934	899	0	0
T9	335191	4553	0	0
T10	11138	143	0	0
T11	52329	709	0	0
T12	8625	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	546077	0	0
T1	171330	175	0	0
T2	2038	10	0	0
T3	245155	23	0	0
T4	120704	1792	0	0
T7	47594	210	0	0
T8	45934	208	0	0
T9	335191	644	0	0
T10	11138	150	0	0
T11	52329	112	0	0
T12	8625	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	207217	0	0
T1	171330	145	0	0
T2	2038	10	0	0
T3	245155	13	0	0
T4	120704	442	0	0
T7	47594	140	0	0
T8	45934	120	0	0
T9	335191	581	0	0
T10	11138	146	0	0
T11	52329	94	0	0
T12	8625	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	866636	0	0
GntImpliesValid_A	427896015	866636	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	866636	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	10539521	0	0
ReadyAndValidImplyGrant_A	427896015	866636	0	0
ReqAndReadyImplyGrant_A	427896015	866636	0	0
ReqImpliesValid_A	427896015	2166836	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	21076	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	866636	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	10539521	0	0
T1	171330	1918	0	0
T2	2038	1	0	0
T3	245155	135	0	0
T4	120704	5751	0	0
T7	47594	3385	0	0
T8	45934	3060	0	0
T9	335191	17216	0	0
T10	11138	1	0	0
T11	52329	2785	0	0
T12	8625	192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	2166836	0	0
T1	171330	752	0	0
T2	2038	55	0	0
T3	245155	59	0	0
T4	120704	3646	0	0
T7	47594	916	0	0
T8	45934	933	0	0
T9	335191	3640	0	0
T10	11138	515	0	0
T11	52329	717	0	0
T12	8625	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	21076	0	900
T4	120704	77	0	1
T9	335191	1	0	1
T10	11138	8	0	1
T11	52329	1	0	1
T12	8625	0	0	1
T13	268277	0	0	1
T14	11104	4	0	1
T15	181831	2	0	1
T16	0	7	0	0
T17	0	4	0	0
T18	0	14	0	0
T19	0	15	0	0
T20	312762	0	0	1
T21	52677	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	866636	0	0
T1	171330	586	0	0
T2	2038	55	0	0
T3	245155	45	0	0
T4	120704	1500	0	0
T7	47594	537	0	0
T8	45934	477	0	0
T9	335191	2761	0	0
T10	11138	515	0	0
T11	52329	458	0	0
T12	8625	36	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427896015	427765368	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427896015	870393	0	0
GntImpliesValid_A	427896015	870393	0	0
GrantKnown_A	427896015	427765368	0	0
IdxKnown_A	427896015	427765368	0	0
IndexIsCorrect_A	427896015	870393	0	0
LockArbDecision_A	427896015	0	0	0
NoReadyValidNoGrant_A	427896015	359384298	0	0
ReadyAndValidImplyGrant_A	427896015	870393	0	0
ReqAndReadyImplyGrant_A	427896015	870393	0	0
ReqImpliesValid_A	427896015	12691673	0	0
ReqStaysHighUntilGranted0_M	427896015	0	0	0
RoundRobin_A	427896015	34858	0	900
ValidKnown_A	427896015	427765368	0	0
gen_data_port_assertion.DataFlow_A	427896015	870393	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	359384298	0	0
T1	171330	142491	0	0
T2	2038	1	0	0
T3	245155	204150	0	0
T4	120704	97834	0	0
T7	47594	37484	0	0
T8	45934	38413	0	0
T9	335191	280550	0	0
T10	11138	1	0	0
T11	52329	44827	0	0
T12	8625	7584	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	12691673	0	0
T1	171330	2285	0	0
T2	2038	42	0	0
T3	245155	167	0	0
T4	120704	9074	0	0
T7	47594	4505	0	0
T8	45934	3812	0	0
T9	335191	27484	0	0
T10	11138	518	0	0
T11	52329	3096	0	0
T12	8625	277	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	34858	0	900
T4	120704	76	0	1
T7	47594	2	0	1
T8	45934	0	0	1
T9	335191	6	0	1
T10	11138	6	0	1
T11	52329	1	0	1
T12	8625	0	0	1
T13	268277	0	0	1
T14	11104	5	0	1
T15	0	2	0	0
T16	0	3	0	0
T17	0	2	0	0
T18	0	11	0	0
T20	312762	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	427765368	0	0
T1	171330	171324	0	0
T2	2038	2016	0	0
T3	245155	245139	0	0
T4	120704	120644	0	0
T7	47594	47572	0	0
T8	45934	45865	0	0
T9	335191	335172	0	0
T10	11138	11113	0	0
T11	52329	52317	0	0
T12	8625	8608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427896015	870393	0	0
T1	171330	508	0	0
T2	2038	42	0	0
T3	245155	38	0	0
T4	120704	1417	0	0
T7	47594	598	0	0
T8	45934	480	0	0
T9	335191	3339	0	0
T10	11138	518	0	0
T11	52329	387	0	0
T12	8625	40	0	0