Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1569999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249372

1

T1

40

T2

30

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	617840	1			T1	192		T2	56		T3	45
values[0x0]	583962	1			T1	36		T2	59		T3	5
values[0x1]	617569	1			T1	218		T2	48		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1213345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606026

1

T1

151

T2

59

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29474	1			T1	11		T2	1		T3	1
valid_sources[0x01]	28985	1			T1	9		T2	2		T3	2
valid_sources[0x02]	28458	1			T1	6		T2	1		T3	1
valid_sources[0x03]	28526	1			T1	9		T3	3		T7	13
valid_sources[0x04]	28933	1			T1	10		T2	2		T3	1
valid_sources[0x05]	28549	1			T1	8		T2	1		T3	5
valid_sources[0x06]	28129	1			T1	11		T2	2		T3	2
valid_sources[0x07]	28606	1			T1	5		T2	8		T3	3
valid_sources[0x08]	27808	1			T1	4		T2	1		T3	1
valid_sources[0x09]	29163	1			T1	12		T2	2		T3	2
valid_sources[0x0a]	28502	1			T1	7		T2	2		T3	1
valid_sources[0x0b]	27374	1			T1	7		T2	3		T7	5
valid_sources[0x0c]	28634	1			T1	3		T2	4		T3	2
valid_sources[0x0d]	28598	1			T1	6		T2	1		T3	1
valid_sources[0x0e]	29046	1			T1	7		T2	1		T3	3
valid_sources[0x0f]	27677	1			T1	4		T2	7		T7	12
valid_sources[0x10]	27759	1			T1	1		T2	1		T7	16
valid_sources[0x11]	27566	1			T1	6		T2	5		T3	1
valid_sources[0x12]	28234	1			T1	7		T2	4		T7	15
valid_sources[0x13]	27996	1			T1	4		T2	2		T3	2
valid_sources[0x14]	28212	1			T1	6		T2	1		T3	1
valid_sources[0x15]	28612	1			T1	6		T2	3		T3	2
valid_sources[0x16]	28648	1			T1	9		T2	3		T7	9
valid_sources[0x17]	28322	1			T1	6		T7	10		T8	52
valid_sources[0x18]	29412	1			T1	6		T2	1		T3	2
valid_sources[0x19]	28451	1			T1	10		T2	3		T3	1
valid_sources[0x1a]	28566	1			T1	9		T2	1		T3	1
valid_sources[0x1b]	27664	1			T1	4		T2	3		T3	1
valid_sources[0x1c]	29013	1			T1	8		T2	6		T3	1
valid_sources[0x1d]	28301	1			T1	10		T2	3		T3	2
valid_sources[0x1e]	28903	1			T1	5		T2	6		T3	2
valid_sources[0x1f]	27912	1			T1	9		T2	4		T7	17
valid_sources[0x20]	28525	1			T1	5		T2	3		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26682

1

T1

13

T2

4

T3

7

values[0x0]

all_enables

biggest_size

196476

1

T1

15

T2

19

T3

1

values[0x1]

all_enables

biggest_size

26214

1

T1

12

T2

7

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1584948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258357

1

T1

40

T2

21

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	630640	1			T1	202		T2	44		T3	23
values[0x0]	581523	1			T1	29		T2	38		T3	2
values[0x1]	631142	1			T1	224		T2	46		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1216151	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

627154

1

T1

178

T2

41

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28384	1			T1	10		T2	3		T7	21
valid_sources[0x01]	28709	1			T1	7		T2	1		T3	1
valid_sources[0x02]	28671	1			T1	7		T2	2		T7	12
valid_sources[0x03]	29571	1			T1	11		T7	13		T8	57
valid_sources[0x04]	28647	1			T1	9		T7	9		T8	38
valid_sources[0x05]	28856	1			T1	10		T2	5		T3	1
valid_sources[0x06]	28709	1			T1	13		T7	9		T8	49
valid_sources[0x07]	27951	1			T1	5		T7	17		T8	57
valid_sources[0x08]	28685	1			T1	7		T2	5		T3	2
valid_sources[0x09]	28768	1			T1	9		T2	1		T3	1
valid_sources[0x0a]	28257	1			T1	7		T2	4		T7	14
valid_sources[0x0b]	27660	1			T1	4		T2	4		T7	16
valid_sources[0x0c]	29086	1			T1	4		T3	3		T7	10
valid_sources[0x0d]	28810	1			T1	5		T7	6		T8	48
valid_sources[0x0e]	28669	1			T1	9		T2	3		T3	4
valid_sources[0x0f]	28809	1			T1	6		T2	1		T3	1
valid_sources[0x10]	28264	1			T1	3		T3	1		T7	11
valid_sources[0x11]	29076	1			T1	13		T2	1		T7	14
valid_sources[0x12]	28741	1			T1	11		T3	1		T7	9
valid_sources[0x13]	28710	1			T1	6		T2	1		T3	2
valid_sources[0x14]	28612	1			T1	4		T2	1		T3	1
valid_sources[0x15]	28854	1			T1	2		T2	3		T3	2
valid_sources[0x16]	28428	1			T1	7		T2	1		T3	1
valid_sources[0x17]	29218	1			T1	11		T2	2		T3	3
valid_sources[0x18]	28038	1			T1	6		T2	2		T3	1
valid_sources[0x19]	29303	1			T1	7		T2	7		T3	1
valid_sources[0x1a]	29004	1			T1	6		T2	10		T3	1
valid_sources[0x1b]	28794	1			T1	10		T2	1		T7	11
valid_sources[0x1c]	29132	1			T1	7		T2	2		T3	1
valid_sources[0x1d]	28826	1			T1	7		T2	1		T7	12
valid_sources[0x1e]	29038	1			T1	3		T2	1		T3	1
valid_sources[0x1f]	29625	1			T1	8		T2	1		T3	1
valid_sources[0x20]	28226	1			T1	11		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27211

1

T1

22

T2

4

T3

3

values[0x0]

all_enables

biggest_size

203971

1

T1

9

T2

15

T3

2

values[0x1]

all_enables

biggest_size

27175

1

T1

9

T2

2

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1577291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250281

1

T1

50

T2

18

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	619166	1			T1	198		T2	36		T3	33
values[0x0]	587751	1			T1	28		T2	46		T3	3
values[0x1]	620655	1			T1	194		T2	30		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1220073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607499

1

T1

159

T2

35

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29024	1			T3	4		T7	9		T8	37
valid_sources[0x01]	29385	1			T1	7		T3	3		T7	14
valid_sources[0x02]	28283	1			T1	3		T3	2		T7	8
valid_sources[0x03]	28015	1			T1	10		T3	2		T7	12
valid_sources[0x04]	28534	1			T1	11		T3	1		T7	10
valid_sources[0x05]	27888	1			T1	5		T7	16		T8	67
valid_sources[0x06]	28387	1			T1	6		T2	2		T3	1
valid_sources[0x07]	28895	1			T1	7		T2	21		T3	1
valid_sources[0x08]	28825	1			T1	3		T3	1		T7	8
valid_sources[0x09]	28803	1			T1	8		T2	1		T7	4
valid_sources[0x0a]	28268	1			T1	12		T7	5		T8	62
valid_sources[0x0b]	28538	1			T1	7		T3	2		T7	14
valid_sources[0x0c]	28658	1			T1	3		T7	9		T8	23
valid_sources[0x0d]	28633	1			T1	6		T3	1		T7	15
valid_sources[0x0e]	28558	1			T1	6		T2	4		T3	3
valid_sources[0x0f]	28668	1			T1	5		T3	1		T7	7
valid_sources[0x10]	28041	1			T1	3		T7	19		T8	44
valid_sources[0x11]	29151	1			T1	5		T3	1		T7	13
valid_sources[0x12]	28699	1			T1	10		T3	3		T7	10
valid_sources[0x13]	27805	1			T1	10		T3	1		T7	13
valid_sources[0x14]	28503	1			T1	3		T3	4		T7	12
valid_sources[0x15]	28734	1			T1	11		T7	5		T8	59
valid_sources[0x16]	28455	1			T1	7		T3	2		T7	9
valid_sources[0x17]	29153	1			T1	18		T7	21		T8	28
valid_sources[0x18]	28747	1			T1	1		T7	15		T8	74
valid_sources[0x19]	29100	1			T1	10		T7	4		T8	22
valid_sources[0x1a]	28831	1			T1	11		T7	7		T8	49
valid_sources[0x1b]	27698	1			T1	5		T7	10		T8	49
valid_sources[0x1c]	28859	1			T1	4		T3	1		T7	20
valid_sources[0x1d]	28674	1			T1	2		T3	1		T7	4
valid_sources[0x1e]	28941	1			T1	9		T2	1		T3	1
valid_sources[0x1f]	28490	1			T1	4		T3	1		T7	15
valid_sources[0x20]	28862	1			T1	1		T3	2		T7	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26647

1

T1

18

T2

2

T3

1

values[0x0]

all_enables

biggest_size

197089

1

T1

15

T2

15

T7

22

values[0x1]

all_enables

biggest_size

26545

1

T1

17

T2

1

T3

2