Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8014605	0	0
GntImpliesValid_A	2147483647	8014605	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8014605	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	482908711	0	0
ReadyAndValidImplyGrant_A	2147483647	8014605	0	0
ReqAndReadyImplyGrant_A	2147483647	8014605	0	0
ReqImpliesValid_A	2147483647	36718115	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49383	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8014605	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1309944	1308912	0	0
T2	7350792	7349472	0	0
T3	1198464	1196688	0	0
T7	12615600	12612576	0	0
T8	6368064	6367968	0	0
T9	260376	259848	0	0
T10	52752	51240	0	0
T11	443232	442752	0	0
T12	267264	266616	0	0
T13	96072	95904	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1309944	1308912	0	0
T2	7350792	7349472	0	0
T3	1198464	1196688	0	0
T7	12615600	12612576	0	0
T8	6368064	6367968	0	0
T9	260376	259848	0	0
T10	52752	51240	0	0
T11	443232	442752	0	0
T12	267264	266616	0	0
T13	96072	95904	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1309944	1308912	0	0
T2	7350792	7349472	0	0
T3	1198464	1196688	0	0
T7	12615600	12612576	0	0
T8	6368064	6367968	0	0
T9	260376	259848	0	0
T10	52752	51240	0	0
T11	443232	442752	0	0
T12	267264	266616	0	0
T13	96072	95904	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482908711	0	0
T1	1309944	21807	0	0
T2	7350792	256789	0	0
T3	1198464	77496	0	0
T7	12615600	762214	0	0
T8	6368064	254389	0	0
T9	260376	4682	0	0
T10	52752	556	0	0
T11	443232	8116	0	0
T12	267264	7444	0	0
T13	96072	4952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36718115	0	0
T1	1309944	39909	0	0
T2	7350792	669	0	0
T3	1198464	11133	0	0
T7	12615600	165127	0	0
T8	6368064	14182	0	0
T9	260376	4155	0	0
T10	52752	536	0	0
T11	443232	7049	0	0
T12	267264	8565	0	0
T13	96072	602	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49383	0	21600
T1	109162	337	0	2
T2	612566	0	0	2
T3	99872	2	0	2
T7	1051300	14	0	2
T8	530672	1	0	2
T9	21698	14	0	2
T10	4396	0	0	2
T11	36936	17	0	2
T12	22272	23	0	2
T13	8006	0	0	2
T14	0	29	0	0
T15	0	40	0	0
T16	0	7	0	0
T17	0	19	0	0
T18	0	42	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1309944	1308912	0	0
T2	7350792	7349472	0	0
T3	1198464	1196688	0	0
T7	12615600	12612576	0	0
T8	6368064	6367968	0	0
T9	260376	259848	0	0
T10	52752	51240	0	0
T11	443232	442752	0	0
T12	267264	266616	0	0
T13	96072	95904	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8014605	0	0
T1	1309944	24255	0	0
T2	7350792	403	0	0
T3	1198464	4605	0	0
T7	12615600	46492	0	0
T8	6368064	8575	0	0
T9	260376	4045	0	0
T10	52752	480	0	0
T11	443232	6899	0	0
T12	267264	7466	0	0
T13	96072	248	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	896449	0	0
GntImpliesValid_A	439319273	896449	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	896449	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	12960263	0	0
ReadyAndValidImplyGrant_A	439319273	896449	0	0
ReqAndReadyImplyGrant_A	439319273	896449	0	0
ReqImpliesValid_A	439319273	2608548	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	896449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	12960263	0	0
T1	54581	1795	0	0
T2	306283	200	0	0
T3	49936	3632	0	0
T7	525650	33775	0	0
T8	265336	3997	0	0
T9	10849	422	0	0
T10	2198	40	0	0
T11	18468	719	0	0
T12	11136	605	0	0
T13	4003	222	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	2608548	0	0
T1	54581	2706	0	0
T2	306283	62	0	0
T3	49936	950	0	0
T7	525650	9807	0	0
T8	265336	1306	0	0
T9	10849	449	0	0
T10	2198	63	0	0
T11	18468	774	0	0
T12	11136	1056	0	0
T13	4003	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	896449	0	0
T1	54581	2250	0	0
T2	306283	48	0	0
T3	49936	523	0	0
T7	525650	5344	0	0
T8	265336	943	0	0
T9	10849	435	0	0
T10	2198	51	0	0
T11	18468	746	0	0
T12	11136	830	0	0
T13	4003	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	893514	0	0
GntImpliesValid_A	439319273	893514	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	893514	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	13052485	0	0
ReadyAndValidImplyGrant_A	439319273	893514	0	0
ReqAndReadyImplyGrant_A	439319273	893514	0	0
ReqImpliesValid_A	439319273	2674063	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	893514	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	13052485	0	0
T1	54581	1872	0	0
T2	306283	151	0	0
T3	49936	3550	0	0
T7	525650	33482	0	0
T8	265336	4037	0	0
T9	10849	437	0	0
T10	2198	35	0	0
T11	18468	732	0	0
T12	11136	628	0	0
T13	4003	165	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	2674063	0	0
T1	54581	4451	0	0
T2	306283	33	0	0
T3	49936	733	0	0
T7	525650	15112	0	0
T8	265336	1293	0	0
T9	10849	466	0	0
T10	2198	54	0	0
T11	18468	777	0	0
T12	11136	1167	0	0
T13	4003	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	893514	0	0
T1	54581	3161	0	0
T2	306283	30	0	0
T3	49936	484	0	0
T7	525650	5167	0	0
T8	265336	969	0	0
T9	10849	451	0	0
T10	2198	44	0	0
T11	18468	754	0	0
T12	11136	897	0	0
T13	4003	27	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	209935	0	0
GntImpliesValid_A	439319273	209935	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	209935	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3228926	0	0
ReadyAndValidImplyGrant_A	439319273	209935	0	0
ReqAndReadyImplyGrant_A	439319273	209935	0	0
ReqImpliesValid_A	439319273	558049	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	209935	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3228926	0	0
T1	54581	458	0	0
T2	306283	36	0	0
T3	49936	863	0	0
T7	525650	8594	0	0
T8	265336	991	0	0
T9	10849	110	0	0
T10	2198	16	0	0
T11	18468	174	0	0
T12	11136	207	0	0
T13	4003	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	558049	0	0
T1	54581	2375	0	0
T2	306283	8	0	0
T3	49936	216	0	0
T7	525650	3143	0	0
T8	265336	260	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	252	0	0
T13	4003	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	209935	0	0
T1	54581	1416	0	0
T2	306283	8	0	0
T3	49936	128	0	0
T7	525650	1268	0	0
T8	265336	230	0	0
T9	10849	111	0	0
T10	2198	15	0	0
T11	18468	173	0	0
T12	11136	229	0	0
T13	4003	2	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	220869	0	0
GntImpliesValid_A	439319273	220869	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	220869	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3294684	0	0
ReadyAndValidImplyGrant_A	439319273	220869	0	0
ReqAndReadyImplyGrant_A	439319273	220869	0	0
ReqImpliesValid_A	439319273	585216	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	220869	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3294684	0	0
T1	54581	389	0	0
T2	306283	57	0	0
T3	49936	845	0	0
T7	525650	8337	0	0
T8	265336	865	0	0
T9	10849	122	0	0
T10	2198	17	0	0
T11	18468	199	0	0
T12	11136	180	0	0
T13	4003	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	585216	0	0
T1	54581	414	0	0
T2	306283	20	0	0
T3	49936	132	0	0
T7	525650	3501	0	0
T8	265336	267	0	0
T9	10849	129	0	0
T10	2198	22	0	0
T11	18468	198	0	0
T12	11136	203	0	0
T13	4003	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220869	0	0
T1	54581	401	0	0
T2	306283	14	0	0
T3	49936	117	0	0
T7	525650	1269	0	0
T8	265336	219	0	0
T9	10849	125	0	0
T10	2198	19	0	0
T11	18468	198	0	0
T12	11136	191	0	0
T13	4003	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	213167	0	0
GntImpliesValid_A	439319273	213167	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	213167	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	5376859	0	0
ReadyAndValidImplyGrant_A	439319273	213167	0	0
ReqAndReadyImplyGrant_A	439319273	213167	0	0
ReqImpliesValid_A	439319273	1139122	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	213167	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	5376859	0	0
T1	54581	2718	0	0
T2	306283	148	0	0
T3	49936	2768	0	0
T7	525650	13986	0	0
T8	265336	1543	0	0
T9	10849	471	0	0
T10	2198	83	0	0
T11	18468	871	0	0
T12	11136	687	0	0
T13	4003	51	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	1139122	0	0
T1	54581	4582	0	0
T2	306283	9	0	0
T3	49936	457	0	0
T7	525650	3825	0	0
T8	265336	291	0	0
T9	10849	129	0	0
T10	2198	19	0	0
T11	18468	211	0	0
T12	11136	335	0	0
T13	4003	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	213167	0	0
T1	54581	941	0	0
T2	306283	9	0	0
T3	49936	130	0	0
T7	525650	1249	0	0
T8	265336	225	0	0
T9	10849	113	0	0
T10	2198	15	0	0
T11	18468	191	0	0
T12	11136	208	0	0
T13	4003	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	215646	0	0
GntImpliesValid_A	439319273	215646	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	215646	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	6184570	0	0
ReadyAndValidImplyGrant_A	439319273	215646	0	0
ReqAndReadyImplyGrant_A	439319273	215646	0	0
ReqImpliesValid_A	439319273	1249568	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	215646	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	6184570	0	0
T1	54581	2457	0	0
T2	306283	222	0	0
T3	49936	2154	0	0
T7	525650	7880	0	0
T8	265336	1469	0	0
T9	10849	521	0	0
T10	2198	53	0	0
T11	18468	809	0	0
T12	11136	888	0	0
T13	4003	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	1249568	0	0
T1	54581	4394	0	0
T2	306283	15	0	0
T3	49936	242	0	0
T7	525650	899	0	0
T8	265336	315	0	0
T9	10849	155	0	0
T10	2198	10	0	0
T11	18468	199	0	0
T12	11136	232	0	0
T13	4003	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215646	0	0
T1	54581	1002	0	0
T2	306283	14	0	0
T3	49936	110	0	0
T7	525650	769	0	0
T8	265336	227	0	0
T9	10849	127	0	0
T10	2198	10	0	0
T11	18468	192	0	0
T12	11136	173	0	0
T13	4003	2	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	214019	0	0
GntImpliesValid_A	439319273	214019	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	214019	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	5647999	0	0
ReadyAndValidImplyGrant_A	439319273	214019	0	0
ReqAndReadyImplyGrant_A	439319273	214019	0	0
ReqImpliesValid_A	439319273	1127638	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	214019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	5647999	0	0
T1	54581	2825	0	0
T2	306283	71	0	0
T3	49936	3979	0	0
T7	525650	51567	0	0
T8	265336	1660	0	0
T9	10849	507	0	0
T10	2198	44	0	0
T11	18468	748	0	0
T12	11136	846	0	0
T13	4003	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	1127638	0	0
T1	54581	744	0	0
T2	306283	8	0	0
T3	49936	485	0	0
T7	525650	3320	0	0
T8	265336	380	0	0
T9	10849	117	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	327	0	0
T13	4003	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214019	0	0
T1	54581	478	0	0
T2	306283	8	0	0
T3	49936	126	0	0
T7	525650	730	0	0
T8	265336	258	0	0
T9	10849	107	0	0
T10	2198	9	0	0
T11	18468	182	0	0
T12	11136	199	0	0
T13	4003	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	224511	0	0
GntImpliesValid_A	439319273	224511	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	224511	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	6435732	0	0
ReadyAndValidImplyGrant_A	439319273	224511	0	0
ReqAndReadyImplyGrant_A	439319273	224511	0	0
ReqImpliesValid_A	439319273	1521552	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	224511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	6435732	0	0
T1	54581	2996	0	0
T2	306283	140	0	0
T3	49936	1582	0	0
T7	525650	15851	0	0
T8	265336	1514	0	0
T9	10849	490	0	0
T10	2198	61	0	0
T11	18468	1155	0	0
T12	11136	763	0	0
T13	4003	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	1521552	0	0
T1	54581	4382	0	0
T2	306283	20	0	0
T3	49936	220	0	0
T7	525650	12220	0	0
T8	265336	306	0	0
T9	10849	125	0	0
T10	2198	25	0	0
T11	18468	210	0	0
T12	11136	305	0	0
T13	4003	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224511	0	0
T1	54581	871	0	0
T2	306283	13	0	0
T3	49936	127	0	0
T7	525650	1774	0	0
T8	265336	221	0	0
T9	10849	114	0	0
T10	2198	14	0	0
T11	18468	181	0	0
T12	11136	206	0	0
T13	4003	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	224215	0	0
GntImpliesValid_A	439319273	224215	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	224215	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3265772	0	0
ReadyAndValidImplyGrant_A	439319273	224215	0	0
ReqAndReadyImplyGrant_A	439319273	224215	0	0
ReqImpliesValid_A	439319273	638623	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	224215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3265772	0	0
T1	54581	442	0	0
T2	306283	40	0	0
T3	49936	848	0	0
T7	525650	6241	0	0
T8	265336	1047	0	0
T9	10849	96	0	0
T10	2198	23	0	0
T11	18468	194	0	0
T12	11136	190	0	0
T13	4003	147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	638623	0	0
T1	54581	487	0	0
T2	306283	20	0	0
T3	49936	165	0	0
T7	525650	1041	0	0
T8	265336	306	0	0
T9	10849	95	0	0
T10	2198	24	0	0
T11	18468	197	0	0
T12	11136	209	0	0
T13	4003	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224215	0	0
T1	54581	464	0	0
T2	306283	12	0	0
T3	49936	125	0	0
T7	525650	841	0	0
T8	265336	245	0	0
T9	10849	95	0	0
T10	2198	23	0	0
T11	18468	195	0	0
T12	11136	199	0	0
T13	4003	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	229863	0	0
GntImpliesValid_A	439319273	229863	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	229863	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3237119	0	0
ReadyAndValidImplyGrant_A	439319273	229863	0	0
ReqAndReadyImplyGrant_A	439319273	229863	0	0
ReqImpliesValid_A	439319273	618641	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	229863	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3237119	0	0
T1	54581	469	0	0
T2	306283	62	0	0
T3	49936	1126	0	0
T7	525650	7897	0	0
T8	265336	1074	0	0
T9	10849	115	0	0
T10	2198	14	0	0
T11	18468	200	0	0
T12	11136	191	0	0
T13	4003	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	618641	0	0
T1	54581	1432	0	0
T2	306283	19	0	0
T3	49936	209	0	0
T7	525650	9941	0	0
T8	265336	317	0	0
T9	10849	118	0	0
T10	2198	19	0	0
T11	18468	201	0	0
T12	11136	216	0	0
T13	4003	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229863	0	0
T1	54581	950	0	0
T2	306283	13	0	0
T3	49936	146	0	0
T7	525650	1753	0	0
T8	265336	236	0	0
T9	10849	116	0	0
T10	2198	16	0	0
T11	18468	200	0	0
T12	11136	203	0	0
T13	4003	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	220563	0	0
GntImpliesValid_A	439319273	220563	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	220563	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3180160	0	0
ReadyAndValidImplyGrant_A	439319273	220563	0	0
ReqAndReadyImplyGrant_A	439319273	220563	0	0
ReqImpliesValid_A	439319273	610810	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	220563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3180160	0	0
T1	54581	463	0	0
T2	306283	45	0	0
T3	49936	1023	0	0
T7	525650	7254	0	0
T8	265336	1144	0	0
T9	10849	113	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	183	0	0
T13	4003	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	610810	0	0
T1	54581	1572	0	0
T2	306283	15	0	0
T3	49936	163	0	0
T7	525650	4998	0	0
T8	265336	327	0	0
T9	10849	118	0	0
T10	2198	12	0	0
T11	18468	197	0	0
T12	11136	200	0	0
T13	4003	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220563	0	0
T1	54581	1017	0	0
T2	306283	14	0	0
T3	49936	136	0	0
T7	525650	1274	0	0
T8	265336	254	0	0
T9	10849	115	0	0
T10	2198	11	0	0
T11	18468	196	0	0
T12	11136	191	0	0
T13	4003	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	229341	0	0
GntImpliesValid_A	439319273	229341	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	229341	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3267517	0	0
ReadyAndValidImplyGrant_A	439319273	229341	0	0
ReqAndReadyImplyGrant_A	439319273	229341	0	0
ReqImpliesValid_A	439319273	620186	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	229341	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3267517	0	0
T1	54581	440	0	0
T2	306283	34	0	0
T3	49936	930	0	0
T7	525650	9499	0	0
T8	265336	1089	0	0
T9	10849	109	0	0
T10	2198	16	0	0
T11	18468	205	0	0
T12	11136	195	0	0
T13	4003	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	620186	0	0
T1	54581	475	0	0
T2	306283	7	0	0
T3	49936	152	0	0
T7	525650	2100	0	0
T8	265336	312	0	0
T9	10849	108	0	0
T10	2198	17	0	0
T11	18468	208	0	0
T12	11136	228	0	0
T13	4003	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	229341	0	0
T1	54581	457	0	0
T2	306283	7	0	0
T3	49936	128	0	0
T7	525650	1315	0	0
T8	265336	251	0	0
T9	10849	108	0	0
T10	2198	16	0	0
T11	18468	206	0	0
T12	11136	211	0	0
T13	4003	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	214930	0	0
GntImpliesValid_A	439319273	214930	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	214930	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3243379	0	0
ReadyAndValidImplyGrant_A	439319273	214930	0	0
ReqAndReadyImplyGrant_A	439319273	214930	0	0
ReqImpliesValid_A	439319273	564789	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	214930	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3243379	0	0
T1	54581	419	0	0
T2	306283	68	0	0
T3	49936	945	0	0
T7	525650	12715	0	0
T8	265336	1171	0	0
T9	10849	126	0	0
T10	2198	18	0	0
T11	18468	186	0	0
T12	11136	177	0	0
T13	4003	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	564789	0	0
T1	54581	464	0	0
T2	306283	19	0	0
T3	49936	186	0	0
T7	525650	4956	0	0
T8	265336	322	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	199	0	0
T12	11136	204	0	0
T13	4003	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214930	0	0
T1	54581	441	0	0
T2	306283	16	0	0
T3	49936	133	0	0
T7	525650	1858	0	0
T8	265336	258	0	0
T9	10849	125	0	0
T10	2198	17	0	0
T11	18468	192	0	0
T12	11136	190	0	0
T13	4003	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	224597	0	0
GntImpliesValid_A	439319273	224597	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	224597	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3223767	0	0
ReadyAndValidImplyGrant_A	439319273	224597	0	0
ReqAndReadyImplyGrant_A	439319273	224597	0	0
ReqImpliesValid_A	439319273	590791	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	224597	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3223767	0	0
T1	54581	403	0	0
T2	306283	28	0	0
T3	49936	1084	0	0
T7	525650	8948	0	0
T8	265336	972	0	0
T9	10849	108	0	0
T10	2198	10	0	0
T11	18468	184	0	0
T12	11136	211	0	0
T13	4003	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	590791	0	0
T1	54581	440	0	0
T2	306283	10	0	0
T3	49936	198	0	0
T7	525650	3841	0	0
T8	265336	276	0	0
T9	10849	109	0	0
T10	2198	9	0	0
T11	18468	189	0	0
T12	11136	232	0	0
T13	4003	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	224597	0	0
T1	54581	421	0	0
T2	306283	6	0	0
T3	49936	139	0	0
T7	525650	1725	0	0
T8	265336	241	0	0
T9	10849	108	0	0
T10	2198	9	0	0
T11	18468	186	0	0
T12	11136	221	0	0
T13	4003	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	226434	0	0
GntImpliesValid_A	439319273	226434	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	226434	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3246273	0	0
ReadyAndValidImplyGrant_A	439319273	226434	0	0
ReqAndReadyImplyGrant_A	439319273	226434	0	0
ReqImpliesValid_A	439319273	602056	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	226434	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3246273	0	0
T1	54581	439	0	0
T2	306283	67	0	0
T3	49936	860	0	0
T7	525650	6811	0	0
T8	265336	1017	0	0
T9	10849	112	0	0
T10	2198	23	0	0
T11	18468	190	0	0
T12	11136	187	0	0
T13	4003	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	602056	0	0
T1	54581	468	0	0
T2	306283	12	0	0
T3	49936	149	0	0
T7	525650	2940	0	0
T8	265336	286	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	191	0	0
T12	11136	204	0	0
T13	4003	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	226434	0	0
T1	54581	453	0	0
T2	306283	12	0	0
T3	49936	114	0	0
T7	525650	1262	0	0
T8	265336	235	0	0
T9	10849	111	0	0
T10	2198	22	0	0
T11	18468	190	0	0
T12	11136	195	0	0
T13	4003	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	215620	0	0
GntImpliesValid_A	439319273	215620	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	215620	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3166292	0	0
ReadyAndValidImplyGrant_A	439319273	215620	0	0
ReqAndReadyImplyGrant_A	439319273	215620	0	0
ReqImpliesValid_A	439319273	597606	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	215620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3166292	0	0
T1	54581	425	0	0
T2	306283	48	0	0
T3	49936	912	0	0
T7	525650	5750	0	0
T8	265336	1021	0	0
T9	10849	108	0	0
T10	2198	12	0	0
T11	18468	216	0	0
T12	11136	208	0	0
T13	4003	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	597606	0	0
T1	54581	450	0	0
T2	306283	9	0	0
T3	49936	179	0	0
T7	525650	838	0	0
T8	265336	261	0	0
T9	10849	109	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	231	0	0
T13	4003	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215620	0	0
T1	54581	437	0	0
T2	306283	9	0	0
T3	49936	125	0	0
T7	525650	765	0	0
T8	265336	231	0	0
T9	10849	108	0	0
T10	2198	11	0	0
T11	18468	215	0	0
T12	11136	219	0	0
T13	4003	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	243852	0	0
GntImpliesValid_A	439319273	243852	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	243852	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3289288	0	0
ReadyAndValidImplyGrant_A	439319273	243852	0	0
ReqAndReadyImplyGrant_A	439319273	243852	0	0
ReqImpliesValid_A	439319273	642482	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	243852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3289288	0	0
T1	54581	567	0	0
T2	306283	62	0	0
T3	49936	1027	0	0
T7	525650	6381	0	0
T8	265336	1037	0	0
T9	10849	131	0	0
T10	2198	13	0	0
T11	18468	172	0	0
T12	11136	178	0	0
T13	4003	85	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	642482	0	0
T1	54581	1392	0	0
T2	306283	20	0	0
T3	49936	146	0	0
T7	525650	858	0	0
T8	265336	284	0	0
T9	10849	132	0	0
T10	2198	12	0	0
T11	18468	177	0	0
T12	11136	187	0	0
T13	4003	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	243852	0	0
T1	54581	979	0	0
T2	306283	18	0	0
T3	49936	119	0	0
T7	525650	815	0	0
T8	265336	225	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	174	0	0
T12	11136	182	0	0
T13	4003	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	214915	0	0
GntImpliesValid_A	439319273	214915	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	214915	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3212402	0	0
ReadyAndValidImplyGrant_A	439319273	214915	0	0
ReqAndReadyImplyGrant_A	439319273	214915	0	0
ReqImpliesValid_A	439319273	570335	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	214915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3212402	0	0
T1	54581	495	0	0
T2	306283	35	0	0
T3	49936	953	0	0
T7	525650	6376	0	0
T8	265336	986	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	201	0	0
T12	11136	212	0	0
T13	4003	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	570335	0	0
T1	54581	1514	0	0
T2	306283	11	0	0
T3	49936	140	0	0
T7	525650	855	0	0
T8	265336	291	0	0
T9	10849	120	0	0
T10	2198	10	0	0
T11	18468	204	0	0
T12	11136	227	0	0
T13	4003	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	214915	0	0
T1	54581	1004	0	0
T2	306283	11	0	0
T3	49936	130	0	0
T7	525650	788	0	0
T8	265336	238	0	0
T9	10849	119	0	0
T10	2198	9	0	0
T11	18468	202	0	0
T12	11136	219	0	0
T13	4003	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	233086	0	0
GntImpliesValid_A	439319273	233086	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	233086	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3241281	0	0
ReadyAndValidImplyGrant_A	439319273	233086	0	0
ReqAndReadyImplyGrant_A	439319273	233086	0	0
ReqImpliesValid_A	439319273	626426	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	233086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3241281	0	0
T1	54581	420	0	0
T2	306283	38	0	0
T3	49936	778	0	0
T7	525650	6742	0	0
T8	265336	989	0	0
T9	10849	115	0	0
T10	2198	18	0	0
T11	18468	191	0	0
T12	11136	167	0	0
T13	4003	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	626426	0	0
T1	54581	457	0	0
T2	306283	15	0	0
T3	49936	170	0	0
T7	525650	4853	0	0
T8	265336	282	0	0
T9	10849	116	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	184	0	0
T13	4003	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	233086	0	0
T1	54581	438	0	0
T2	306283	10	0	0
T3	49936	111	0	0
T7	525650	1199	0	0
T8	265336	244	0	0
T9	10849	115	0	0
T10	2198	17	0	0
T11	18468	190	0	0
T12	11136	175	0	0
T13	4003	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	223957	0	0
GntImpliesValid_A	439319273	223957	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	223957	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3247157	0	0
ReadyAndValidImplyGrant_A	439319273	223957	0	0
ReqAndReadyImplyGrant_A	439319273	223957	0	0
ReqImpliesValid_A	439319273	635218	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	223957	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3247157	0	0
T1	54581	425	0	0
T2	306283	27	0	0
T3	49936	834	0	0
T7	525650	8005	0	0
T8	265336	1072	0	0
T9	10849	132	0	0
T10	2198	12	0	0
T11	18468	211	0	0
T12	11136	191	0	0
T13	4003	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	635218	0	0
T1	54581	442	0	0
T2	306283	5	0	0
T3	49936	160	0	0
T7	525650	9420	0	0
T8	265336	325	0	0
T9	10849	131	0	0
T10	2198	13	0	0
T11	18468	214	0	0
T12	11136	226	0	0
T13	4003	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	223957	0	0
T1	54581	433	0	0
T2	306283	5	0	0
T3	49936	123	0	0
T7	525650	1748	0	0
T8	265336	247	0	0
T9	10849	131	0	0
T10	2198	12	0	0
T11	18468	212	0	0
T12	11136	208	0	0
T13	4003	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	220603	0	0
GntImpliesValid_A	439319273	220603	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	220603	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3270068	0	0
ReadyAndValidImplyGrant_A	439319273	220603	0	0
ReqAndReadyImplyGrant_A	439319273	220603	0	0
ReqImpliesValid_A	439319273	584478	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	220603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3270068	0	0
T1	54581	433	0	0
T2	306283	40	0	0
T3	49936	964	0	0
T7	525650	9086	0	0
T8	265336	961	0	0
T9	10849	111	0	0
T10	2198	12	0	0
T11	18468	170	0	0
T12	11136	179	0	0
T13	4003	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	584478	0	0
T1	54581	464	0	0
T2	306283	10	0	0
T3	49936	208	0	0
T7	525650	4123	0	0
T8	265336	240	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	171	0	0
T12	11136	208	0	0
T13	4003	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	220603	0	0
T1	54581	448	0	0
T2	306283	10	0	0
T3	49936	140	0	0
T7	525650	1775	0	0
T8	265336	219	0	0
T9	10849	110	0	0
T10	2198	11	0	0
T11	18468	170	0	0
T12	11136	193	0	0
T13	4003	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	215971	0	0
GntImpliesValid_A	439319273	215971	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	215971	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	3239317	0	0
ReadyAndValidImplyGrant_A	439319273	215971	0	0
ReqAndReadyImplyGrant_A	439319273	215971	0	0
ReqImpliesValid_A	439319273	620262	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	0	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	215971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	3239317	0	0
T1	54581	455	0	0
T2	306283	61	0	0
T3	49936	1100	0	0
T7	525650	9033	0	0
T8	265336	1023	0	0
T9	10849	105	0	0
T10	2198	14	0	0
T11	18468	191	0	0
T12	11136	169	0	0
T13	4003	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	620262	0	0
T1	54581	476	0	0
T2	306283	26	0	0
T3	49936	189	0	0
T7	525650	13202	0	0
T8	265336	284	0	0
T9	10849	104	0	0
T10	2198	15	0	0
T11	18468	190	0	0
T12	11136	178	0	0
T13	4003	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	215971	0	0
T1	54581	465	0	0
T2	306283	17	0	0
T3	49936	141	0	0
T7	525650	2169	0	0
T8	265336	229	0	0
T9	10849	104	0	0
T10	2198	14	0	0
T11	18468	190	0	0
T12	11136	173	0	0
T13	4003	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	883494	0	0
GntImpliesValid_A	439319273	883494	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	883494	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	12392410	0	0
ReadyAndValidImplyGrant_A	439319273	883494	0	0
ReqAndReadyImplyGrant_A	439319273	883494	0	0
ReqImpliesValid_A	439319273	2437683	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	14860	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	883494	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	12392410	0	0
T1	54581	1	0	0
T2	306283	136	0	0
T3	49936	3331	0	0
T7	525650	31388	0	0
T8	265336	2952	0	0
T9	10849	1	0	0
T10	2198	1	0	0
T11	18468	1	0	0
T12	11136	1	0	0
T13	4003	208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	2437683	0	0
T1	54581	3074	0	0
T2	306283	51	0	0
T3	49936	801	0	0
T7	525650	13817	0	0
T8	265336	1146	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	14860	0	900
T1	54581	317	0	1
T2	306283	0	0	1
T3	49936	0	0	1
T7	525650	13	0	1
T8	265336	1	0	1
T9	10849	4	0	1
T10	2198	0	0	1
T11	18468	8	0	1
T12	11136	15	0	1
T13	4003	0	0	1
T14	0	9	0	0
T15	0	5	0	0
T16	0	2	0	0
T17	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	883494	0	0
T1	54581	3074	0	0
T2	306283	50	0	0
T3	49936	508	0	0
T7	525650	5305	0	0
T8	265336	926	0	0
T9	10849	429	0	0
T10	2198	43	0	0
T11	18468	782	0	0
T12	11136	880	0	0
T13	4003	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	439319273	439192946	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	439319273	905054	0	0
GntImpliesValid_A	439319273	905054	0	0
GrantKnown_A	439319273	439192946	0	0
IdxKnown_A	439319273	439192946	0	0
IndexIsCorrect_A	439319273	905054	0	0
LockArbDecision_A	439319273	0	0	0
NoReadyValidNoGrant_A	439319273	369004991	0	0
ReadyAndValidImplyGrant_A	439319273	905054	0	0
ReqAndReadyImplyGrant_A	439319273	905054	0	0
ReqImpliesValid_A	439319273	14293973	0	0
ReqStaysHighUntilGranted0_M	439319273	0	0	0
RoundRobin_A	439319273	34523	0	900
ValidKnown_A	439319273	439192946	0	0
gen_data_port_assertion.DataFlow_A	439319273	905054	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	369004991	0	0
T1	54581	1	0	0
T2	306283	254973	0	0
T3	49936	41408	0	0
T7	525650	446616	0	0
T8	265336	220758	0	0
T9	10849	1	0	0
T10	2198	1	0	0
T11	18468	1	0	0
T12	11136	1	0	0
T13	4003	3405	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	14293973	0	0
T1	54581	2254	0	0
T2	306283	245	0	0
T3	49936	4483	0	0
T7	525650	35517	0	0
T8	265336	4505	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	34523	0	900
T1	54581	20	0	1
T2	306283	0	0	1
T3	49936	2	0	1
T7	525650	1	0	1
T8	265336	0	0	1
T9	10849	10	0	1
T10	2198	0	0	1
T11	18468	9	0	1
T12	11136	8	0	1
T13	4003	0	0	1
T14	0	20	0	0
T15	0	35	0	0
T16	0	5	0	0
T18	0	42	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	439192946	0	0
T1	54581	54538	0	0
T2	306283	306228	0	0
T3	49936	49862	0	0
T7	525650	525524	0	0
T8	265336	265332	0	0
T9	10849	10827	0	0
T10	2198	2135	0	0
T11	18468	18448	0	0
T12	11136	11109	0	0
T13	4003	3996	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439319273	905054	0	0
T1	54581	2254	0	0
T2	306283	49	0	0
T3	49936	542	0	0
T7	525650	4330	0	0
T8	265336	1004	0	0
T9	10849	437	0	0
T10	2198	60	0	0
T11	18468	782	0	0
T12	11136	874	0	0
T13	4003	38	0	0