Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1594658	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253244

1

T1

2574

T2

9

T3

262

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627426	1			T1	6464		T2	36		T3	554
values[0x0]	593639	1			T1	6130		T2	31		T3	617
values[0x1]	626837	1			T1	6177		T2	38		T3	620

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1234142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613760

1

T1

6231

T2

34

T3

628

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28390	1			T1	315		T3	27		T8	31
valid_sources[0x01]	28428	1			T1	238		T3	26		T8	40
valid_sources[0x02]	28287	1			T1	318		T2	7		T3	28
valid_sources[0x03]	28717	1			T1	275		T2	6		T3	28
valid_sources[0x04]	28609	1			T1	240		T2	1		T3	37
valid_sources[0x05]	28360	1			T1	311		T3	26		T7	1
valid_sources[0x06]	28913	1			T1	272		T2	3		T3	26
valid_sources[0x07]	28507	1			T1	289		T2	4		T3	25
valid_sources[0x08]	28619	1			T1	243		T2	3		T3	16
valid_sources[0x09]	28031	1			T1	237		T3	28		T8	26
valid_sources[0x0a]	29806	1			T1	302		T3	26		T7	1
valid_sources[0x0b]	29011	1			T1	238		T3	28		T8	28
valid_sources[0x0c]	28966	1			T1	237		T3	31		T8	28
valid_sources[0x0d]	29123	1			T1	320		T2	1		T3	10
valid_sources[0x0e]	28686	1			T1	261		T2	11		T3	51
valid_sources[0x0f]	29851	1			T1	373		T2	1		T3	19
valid_sources[0x10]	29176	1			T1	248		T3	28		T7	1
valid_sources[0x11]	28786	1			T1	259		T2	1		T3	29
valid_sources[0x12]	30351	1			T1	400		T3	32		T7	2
valid_sources[0x13]	29827	1			T1	277		T3	36		T8	30
valid_sources[0x14]	28978	1			T1	314		T3	22		T7	1
valid_sources[0x15]	28956	1			T1	227		T2	6		T3	30
valid_sources[0x16]	28244	1			T1	285		T2	1		T3	16
valid_sources[0x17]	29053	1			T1	284		T2	1		T3	23
valid_sources[0x18]	28682	1			T1	263		T3	31		T7	1
valid_sources[0x19]	28435	1			T1	354		T2	1		T3	22
valid_sources[0x1a]	28692	1			T1	228		T3	35		T7	1
valid_sources[0x1b]	29354	1			T1	312		T3	36		T7	1
valid_sources[0x1c]	28750	1			T1	290		T3	38		T7	1
valid_sources[0x1d]	28607	1			T1	333		T2	2		T3	21
valid_sources[0x1e]	28419	1			T1	277		T2	2		T3	34
valid_sources[0x1f]	29337	1			T1	307		T2	1		T3	33
valid_sources[0x20]	28558	1			T1	289		T2	1		T3	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26712

1

T1

277

T2

1

T3

28

values[0x0]

all_enables

biggest_size

199854

1

T1

2059

T2

7

T3

210

values[0x1]

all_enables

biggest_size

26678

1

T1

238

T2

1

T3

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1612487	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264087

1

T1

2597

T2

12

T3

281

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640901	1			T1	6223		T2	35		T3	676
values[0x0]	593776	1			T1	6070		T2	23		T3	678
values[0x1]	641897	1			T1	6309		T2	47		T3	653

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1237568	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

639006

1

T1

6258

T2

32

T3

665

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28630	1			T1	253		T2	2		T3	39
valid_sources[0x01]	29228	1			T1	223		T2	1		T3	41
valid_sources[0x02]	28795	1			T1	330		T2	3		T3	39
valid_sources[0x03]	29893	1			T1	270		T2	1		T3	29
valid_sources[0x04]	28642	1			T1	288		T2	1		T3	46
valid_sources[0x05]	29427	1			T1	360		T2	2		T3	29
valid_sources[0x06]	28536	1			T1	210		T2	2		T3	21
valid_sources[0x07]	28892	1			T1	351		T2	2		T3	10
valid_sources[0x08]	29671	1			T1	195		T2	2		T3	34
valid_sources[0x09]	29821	1			T1	276		T3	32		T7	5
valid_sources[0x0a]	29824	1			T1	270		T2	2		T3	12
valid_sources[0x0b]	29440	1			T1	219		T2	2		T3	39
valid_sources[0x0c]	29898	1			T1	247		T2	2		T3	21
valid_sources[0x0d]	29556	1			T1	320		T2	2		T3	28
valid_sources[0x0e]	28957	1			T1	231		T2	2		T3	60
valid_sources[0x0f]	29703	1			T1	336		T2	1		T3	39
valid_sources[0x10]	28979	1			T1	345		T2	2		T3	68
valid_sources[0x11]	28783	1			T1	205		T3	27		T7	2
valid_sources[0x12]	29096	1			T1	357		T2	2		T3	29
valid_sources[0x13]	29332	1			T1	294		T3	51		T7	5
valid_sources[0x14]	29665	1			T1	338		T2	1		T3	9
valid_sources[0x15]	29201	1			T1	242		T2	6		T3	32
valid_sources[0x16]	29511	1			T1	323		T3	33		T10	1
valid_sources[0x17]	29056	1			T1	326		T2	1		T3	50
valid_sources[0x18]	29472	1			T1	260		T2	2		T3	37
valid_sources[0x19]	28787	1			T1	304		T3	29		T7	1
valid_sources[0x1a]	29486	1			T1	221		T2	5		T3	21
valid_sources[0x1b]	29769	1			T1	275		T2	1		T3	18
valid_sources[0x1c]	29061	1			T1	305		T2	2		T3	15
valid_sources[0x1d]	28722	1			T1	305		T2	2		T3	16
valid_sources[0x1e]	29605	1			T1	254		T2	4		T3	40
valid_sources[0x1f]	29559	1			T1	275		T2	5		T3	8
valid_sources[0x20]	29548	1			T1	308		T3	27		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27721

1

T1

267

T2

1

T3

34

values[0x0]

all_enables

biggest_size

208701

1

T1

2089

T2

8

T3

216

values[0x1]

all_enables

biggest_size

27665

1

T1

241

T2

3

T3

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1607688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255999

1

T1

2678

T2

19

T3

216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	632167	1			T1	6386		T2	55		T3	556
values[0x0]	600708	1			T1	6282		T2	53		T3	568
values[0x1]	630812	1			T1	6364		T2	44		T3	543

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1242351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

621336

1

T1

6410

T2

46

T3

530

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29010	1			T1	299		T2	1		T3	31
valid_sources[0x01]	29160	1			T1	233		T2	6		T3	34
valid_sources[0x02]	28233	1			T1	290		T2	4		T3	17
valid_sources[0x03]	29233	1			T1	297		T2	1		T3	29
valid_sources[0x04]	29704	1			T1	299		T3	17		T7	2
valid_sources[0x05]	29209	1			T1	354		T2	3		T3	16
valid_sources[0x06]	29149	1			T1	277		T2	4		T3	22
valid_sources[0x07]	28731	1			T1	293		T2	2		T3	22
valid_sources[0x08]	28934	1			T1	225		T3	25		T7	1
valid_sources[0x09]	29041	1			T1	247		T2	3		T3	25
valid_sources[0x0a]	29199	1			T1	260		T2	2		T3	21
valid_sources[0x0b]	28710	1			T1	258		T3	29		T7	3
valid_sources[0x0c]	28567	1			T1	306		T2	6		T3	16
valid_sources[0x0d]	29312	1			T1	309		T2	1		T3	29
valid_sources[0x0e]	29246	1			T1	255		T2	1		T3	18
valid_sources[0x0f]	29204	1			T1	379		T2	2		T3	28
valid_sources[0x10]	30108	1			T1	277		T2	1		T3	31
valid_sources[0x11]	29096	1			T1	267		T2	5		T3	19
valid_sources[0x12]	29546	1			T1	394		T2	3		T3	27
valid_sources[0x13]	29353	1			T1	311		T3	24		T8	16
valid_sources[0x14]	29755	1			T1	343		T2	1		T3	29
valid_sources[0x15]	30230	1			T1	234		T2	4		T3	24
valid_sources[0x16]	28774	1			T1	258		T2	4		T3	20
valid_sources[0x17]	28301	1			T1	310		T2	6		T3	30
valid_sources[0x18]	29570	1			T1	232		T2	4		T3	22
valid_sources[0x19]	28611	1			T1	364		T2	2		T3	33
valid_sources[0x1a]	27864	1			T1	242		T2	4		T3	31
valid_sources[0x1b]	29393	1			T1	277		T3	29		T8	18
valid_sources[0x1c]	28737	1			T1	309		T2	1		T3	25
valid_sources[0x1d]	29230	1			T1	353		T2	4		T3	27
valid_sources[0x1e]	29734	1			T1	298		T2	3		T3	30
valid_sources[0x1f]	29401	1			T1	314		T3	29		T7	1
valid_sources[0x20]	29595	1			T1	320		T2	6		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27075

1

T1

260

T2

3

T3

16

values[0x0]

all_enables

biggest_size

202316

1

T1

2162

T2

14

T3

181

values[0x1]

all_enables

biggest_size

26608

1

T1

256

T2

2

T3

19