Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7924786	0	0
GntImpliesValid_A	2147483647	7924786	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7924786	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	429933060	0	0
ReadyAndValidImplyGrant_A	2147483647	7924786	0	0
ReqAndReadyImplyGrant_A	2147483647	7924786	0	0
ReqImpliesValid_A	2147483647	31257731	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	54257	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7924786	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12365136	12364128	0	0
T2	180336	179952	0	0
T3	1248216	1248048	0	0
T7	1300464	1300152	0	0
T8	149592	149304	0	0
T9	1389216	1389096	0	0
T10	5016216	5014128	0	0
T11	1102440	1101192	0	0
T12	135168	134880	0	0
T13	8451120	8451096	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12365136	12364128	0	0
T2	180336	179952	0	0
T3	1248216	1248048	0	0
T7	1300464	1300152	0	0
T8	149592	149304	0	0
T9	1389216	1389096	0	0
T10	5016216	5014128	0	0
T11	1102440	1101192	0	0
T12	135168	134880	0	0
T13	8451120	8451096	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12365136	12364128	0	0
T2	180336	179952	0	0
T3	1248216	1248048	0	0
T7	1300464	1300152	0	0
T8	149592	149304	0	0
T9	1389216	1389096	0	0
T10	5016216	5014128	0	0
T11	1102440	1101192	0	0
T12	135168	134880	0	0
T13	8451120	8451096	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	429933060	0	0
T1	12365136	698128	0	0
T2	180336	8777	0	0
T3	1248216	74881	0	0
T7	1300464	82073	0	0
T8	149592	2860	0	0
T9	1389216	75544	0	0
T10	5016216	178317	0	0
T11	1102440	75467	0	0
T12	135168	7610	0	0
T13	8451120	320417	0	0
T14	0	3614	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31257731	0	0
T1	12365136	116754	0	0
T2	180336	799	0	0
T3	1248216	12635	0	0
T7	1300464	13477	0	0
T8	149592	2944	0	0
T9	1389216	8277	0	0
T10	5016216	1449	0	0
T11	1102440	12249	0	0
T12	135168	748	0	0
T13	8451120	22891	0	0
T14	0	2709	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54257	0	21600
T1	1030428	61	0	2
T2	15028	0	0	2
T3	104018	1	0	2
T7	108372	2	0	2
T8	12466	7	0	2
T9	115768	0	0	2
T10	418018	0	0	2
T11	91870	2	0	2
T12	11264	0	0	2
T13	704260	12	0	2
T15	0	21	0	0
T16	0	17	0	0
T17	0	7	0	0
T18	0	1492	0	0
T19	0	34	0	0
T20	0	16	0	0
T21	0	22	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12365136	12364128	0	0
T2	180336	179952	0	0
T3	1248216	1248048	0	0
T7	1300464	1300152	0	0
T8	149592	149304	0	0
T9	1389216	1389096	0	0
T10	5016216	5014128	0	0
T11	1102440	1101192	0	0
T12	135168	134880	0	0
T13	8451120	8451096	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7924786	0	0
T1	12365136	47640	0	0
T2	180336	362	0	0
T3	1248216	5465	0	0
T7	1300464	6006	0	0
T8	149592	2708	0	0
T9	1389216	4159	0	0
T10	5016216	837	0	0
T11	1102440	5424	0	0
T12	135168	426	0	0
T13	8451120	8768	0	0
T14	0	167	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	889907	0	0
GntImpliesValid_A	407018650	889907	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	889907	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	10276245	0	0
ReadyAndValidImplyGrant_A	407018650	889907	0	0
ReqAndReadyImplyGrant_A	407018650	889907	0	0
ReqImpliesValid_A	407018650	2314664	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	889907	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	10276245	0	0
T1	515214	39160	0	0
T2	7514	276	0	0
T3	52009	4574	0	0
T7	54186	4982	0	0
T8	6233	232	0	0
T9	57884	3085	0	0
T10	209009	429	0	0
T11	45935	4400	0	0
T12	5632	263	0	0
T13	352130	2767	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2314664	0	0
T1	515214	11325	0	0
T2	7514	48	0	0
T3	52009	1312	0	0
T7	54186	1273	0	0
T8	6233	323	0	0
T9	57884	586	0	0
T10	209009	133	0	0
T11	45935	1194	0	0
T12	5632	75	0	0
T13	352130	962	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	889907	0	0
T1	515214	5514	0	0
T2	7514	34	0	0
T3	52009	656	0	0
T7	54186	712	0	0
T8	6233	277	0	0
T9	57884	427	0	0
T10	209009	96	0	0
T11	45935	618	0	0
T12	5632	47	0	0
T13	352130	683	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	881727	0	0
GntImpliesValid_A	407018650	881727	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	881727	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	10160380	0	0
ReadyAndValidImplyGrant_A	407018650	881727	0	0
ReqAndReadyImplyGrant_A	407018650	881727	0	0
ReqImpliesValid_A	407018650	2218864	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	881727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	10160380	0	0
T1	515214	36222	0	0
T2	7514	296	0	0
T3	52009	4921	0	0
T7	54186	4918	0	0
T8	6233	259	0	0
T9	57884	3279	0	0
T10	209009	381	0	0
T11	45935	4322	0	0
T12	5632	207	0	0
T13	352130	2979	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2218864	0	0
T1	515214	7350	0	0
T2	7514	42	0	0
T3	52009	1122	0	0
T7	54186	1122	0	0
T8	6233	330	0	0
T9	57884	638	0	0
T10	209009	116	0	0
T11	45935	1039	0	0
T12	5632	72	0	0
T13	352130	1003	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	881727	0	0
T1	515214	4821	0	0
T2	7514	41	0	0
T3	52009	634	0	0
T7	54186	656	0	0
T8	6233	294	0	0
T9	57884	443	0	0
T10	209009	92	0	0
T11	45935	581	0	0
T12	5632	39	0	0
T13	352130	688	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	219618	0	0
GntImpliesValid_A	407018650	219618	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	219618	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2550094	0	0
ReadyAndValidImplyGrant_A	407018650	219618	0	0
ReqAndReadyImplyGrant_A	407018650	219618	0	0
ReqImpliesValid_A	407018650	543251	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	219618	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2550094	0	0
T1	515214	10400	0	0
T2	7514	37	0	0
T3	52009	1062	0	0
T7	54186	1135	0	0
T8	6233	74	0	0
T9	57884	728	0	0
T10	209009	130	0	0
T11	45935	1091	0	0
T12	5632	124	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	543251	0	0
T1	515214	4731	0	0
T2	7514	19	0	0
T3	52009	227	0	0
T7	54186	195	0	0
T8	6233	89	0	0
T9	57884	98	0	0
T10	209009	29	0	0
T11	45935	239	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219618	0	0
T1	515214	1600	0	0
T2	7514	10	0	0
T3	52009	146	0	0
T7	54186	165	0	0
T8	6233	81	0	0
T9	57884	94	0	0
T10	209009	25	0	0
T11	45935	148	0	0
T12	5632	14	0	0
T13	352130	0	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	220127	0	0
GntImpliesValid_A	407018650	220127	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	220127	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2558737	0	0
ReadyAndValidImplyGrant_A	407018650	220127	0	0
ReqAndReadyImplyGrant_A	407018650	220127	0	0
ReqImpliesValid_A	407018650	533941	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	220127	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2558737	0	0
T1	515214	8386	0	0
T2	7514	35	0	0
T3	52009	989	0	0
T7	54186	1382	0	0
T8	6233	70	0	0
T9	57884	749	0	0
T10	209009	90	0	0
T11	45935	1213	0	0
T12	5632	138	0	0
T13	352130	1669	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	533941	0	0
T1	515214	1225	0	0
T2	7514	8	0	0
T3	52009	204	0	0
T7	54186	274	0	0
T8	6233	75	0	0
T9	57884	177	0	0
T10	209009	35	0	0
T11	45935	216	0	0
T12	5632	15	0	0
T13	352130	1201	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220127	0	0
T1	515214	1067	0	0
T2	7514	8	0	0
T3	52009	139	0	0
T7	54186	192	0	0
T8	6233	72	0	0
T9	57884	103	0	0
T10	209009	27	0	0
T11	45935	156	0	0
T12	5632	15	0	0
T13	352130	499	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	212121	0	0
GntImpliesValid_A	407018650	212121	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	212121	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	4894786	0	0
ReadyAndValidImplyGrant_A	407018650	212121	0	0
ReqAndReadyImplyGrant_A	407018650	212121	0	0
ReqImpliesValid_A	407018650	1191309	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	212121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	4894786	0	0
T1	515214	7615	0	0
T2	7514	21	0	0
T3	52009	553	0	0
T7	54186	672	0	0
T8	6233	279	0	0
T9	57884	388	0	0
T10	209009	704	0	0
T11	45935	1572	0	0
T12	5632	86	0	0
T13	352130	3728	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	1191309	0	0
T1	515214	2709	0	0
T2	7514	4	0	0
T3	52009	171	0	0
T7	54186	188	0	0
T8	6233	113	0	0
T9	57884	110	0	0
T10	209009	97	0	0
T11	45935	279	0	0
T12	5632	14	0	0
T13	352130	2143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212121	0	0
T1	515214	1598	0	0
T2	7514	4	0	0
T3	52009	145	0	0
T7	54186	154	0	0
T8	6233	88	0	0
T9	57884	101	0	0
T10	209009	17	0	0
T11	45935	126	0	0
T12	5632	11	0	0
T13	352130	450	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	225051	0	0
GntImpliesValid_A	407018650	225051	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	225051	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	4310020	0	0
ReadyAndValidImplyGrant_A	407018650	225051	0	0
ReqAndReadyImplyGrant_A	407018650	225051	0	0
ReqImpliesValid_A	407018650	1142889	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	225051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	4310020	0	0
T1	515214	9174	0	0
T2	7514	67	0	0
T3	52009	515	0	0
T7	54186	1678	0	0
T8	6233	382	0	0
T9	57884	484	0	0
T10	209009	524	0	0
T11	45935	1774	0	0
T12	5632	58	0	0
T13	352130	1239	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	1142889	0	0
T1	515214	1279	0	0
T2	7514	15	0	0
T3	52009	150	0	0
T7	54186	342	0	0
T8	6233	96	0	0
T9	57884	141	0	0
T10	209009	76	0	0
T11	45935	322	0	0
T12	5632	10	0	0
T13	352130	937	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225051	0	0
T1	515214	1063	0	0
T2	7514	13	0	0
T3	52009	125	0	0
T7	54186	167	0	0
T8	6233	76	0	0
T9	57884	128	0	0
T10	209009	24	0	0
T11	45935	166	0	0
T12	5632	10	0	0
T13	352130	431	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	225875	0	0
GntImpliesValid_A	407018650	225875	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	225875	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	4618163	0	0
ReadyAndValidImplyGrant_A	407018650	225875	0	0
ReqAndReadyImplyGrant_A	407018650	225875	0	0
ReqImpliesValid_A	407018650	1231545	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	225875	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	4618163	0	0
T1	515214	6745	0	0
T2	7514	44	0	0
T3	52009	730	0	0
T7	54186	871	0	0
T8	6233	239	0	0
T9	57884	580	0	0
T10	209009	301	0	0
T11	45935	2811	0	0
T12	5632	89	0	0
T13	352130	0	0	0
T14	0	2328	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	1231545	0	0
T1	515214	3414	0	0
T2	7514	7	0	0
T3	52009	175	0	0
T7	54186	200	0	0
T8	6233	107	0	0
T9	57884	129	0	0
T10	209009	37	0	0
T11	45935	491	0	0
T12	5632	24	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	225875	0	0
T1	515214	1576	0	0
T2	7514	7	0	0
T3	52009	129	0	0
T7	54186	169	0	0
T8	6233	77	0	0
T9	57884	124	0	0
T10	209009	32	0	0
T11	45935	165	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	205717	0	0
GntImpliesValid_A	407018650	205717	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	205717	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	5011492	0	0
ReadyAndValidImplyGrant_A	407018650	205717	0	0
ReqAndReadyImplyGrant_A	407018650	205717	0	0
ReqImpliesValid_A	407018650	1087586	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	205717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	5011492	0	0
T1	515214	6701	0	0
T2	7514	93	0	0
T3	52009	604	0	0
T7	54186	934	0	0
T8	6233	249	0	0
T9	57884	542	0	0
T10	209009	364	0	0
T11	45935	2185	0	0
T12	5632	71	0	0
T13	352130	0	0	0
T14	0	1286	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	1087586	0	0
T1	515214	1144	0	0
T2	7514	15	0	0
T3	52009	176	0	0
T7	54186	196	0	0
T8	6233	75	0	0
T9	57884	142	0	0
T10	209009	51	0	0
T11	45935	335	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	205717	0	0
T1	515214	1046	0	0
T2	7514	15	0	0
T3	52009	135	0	0
T7	54186	158	0	0
T8	6233	58	0	0
T9	57884	120	0	0
T10	209009	19	0	0
T11	45935	156	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	207205	0	0
GntImpliesValid_A	407018650	207205	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	207205	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2491263	0	0
ReadyAndValidImplyGrant_A	407018650	207205	0	0
ReqAndReadyImplyGrant_A	407018650	207205	0	0
ReqImpliesValid_A	407018650	501837	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	207205	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2491263	0	0
T1	515214	7782	0	0
T2	7514	140	0	0
T3	52009	1243	0	0
T7	54186	969	0	0
T8	6233	72	0	0
T9	57884	1007	0	0
T10	209009	104	0	0
T11	45935	1052	0	0
T12	5632	153	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	501837	0	0
T1	515214	1217	0	0
T2	7514	31	0	0
T3	52009	200	0	0
T7	54186	238	0	0
T8	6233	77	0	0
T9	57884	165	0	0
T10	209009	26	0	0
T11	45935	204	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	207205	0	0
T1	515214	1036	0	0
T2	7514	15	0	0
T3	52009	160	0	0
T7	54186	139	0	0
T8	6233	74	0	0
T9	57884	121	0	0
T10	209009	22	0	0
T11	45935	153	0	0
T12	5632	21	0	0
T13	352130	0	0	0
T14	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	212398	0	0
GntImpliesValid_A	407018650	212398	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	212398	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2534746	0	0
ReadyAndValidImplyGrant_A	407018650	212398	0	0
ReqAndReadyImplyGrant_A	407018650	212398	0	0
ReqImpliesValid_A	407018650	484216	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	212398	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2534746	0	0
T1	515214	8386	0	0
T2	7514	62	0	0
T3	52009	1160	0	0
T7	54186	1249	0	0
T8	6233	82	0	0
T9	57884	836	0	0
T10	209009	117	0	0
T11	45935	1006	0	0
T12	5632	70	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	484216	0	0
T1	515214	1279	0	0
T2	7514	10	0	0
T3	52009	217	0	0
T7	54186	250	0	0
T8	6233	83	0	0
T9	57884	150	0	0
T10	209009	24	0	0
T11	45935	168	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	212398	0	0
T1	515214	1090	0	0
T2	7514	10	0	0
T3	52009	158	0	0
T7	54186	169	0	0
T8	6233	82	0	0
T9	57884	117	0	0
T10	209009	24	0	0
T11	45935	139	0	0
T12	5632	11	0	0
T13	352130	0	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	228305	0	0
GntImpliesValid_A	407018650	228305	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	228305	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2616152	0	0
ReadyAndValidImplyGrant_A	407018650	228305	0	0
ReqAndReadyImplyGrant_A	407018650	228305	0	0
ReqImpliesValid_A	407018650	573854	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	228305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2616152	0	0
T1	515214	12394	0	0
T2	7514	50	0	0
T3	52009	1068	0	0
T7	54186	1234	0	0
T8	6233	75	0	0
T9	57884	904	0	0
T10	209009	84	0	0
T11	45935	997	0	0
T12	5632	117	0	0
T13	352130	1604	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	573854	0	0
T1	515214	3627	0	0
T2	7514	12	0	0
T3	52009	210	0	0
T7	54186	252	0	0
T8	6233	82	0	0
T9	57884	144	0	0
T10	209009	22	0	0
T11	45935	187	0	0
T12	5632	16	0	0
T13	352130	1164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	228305	0	0
T1	515214	1982	0	0
T2	7514	7	0	0
T3	52009	155	0	0
T7	54186	159	0	0
T8	6233	78	0	0
T9	57884	120	0	0
T10	209009	20	0	0
T11	45935	141	0	0
T12	5632	15	0	0
T13	352130	496	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	214967	0	0
GntImpliesValid_A	407018650	214967	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	214967	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2574278	0	0
ReadyAndValidImplyGrant_A	407018650	214967	0	0
ReqAndReadyImplyGrant_A	407018650	214967	0	0
ReqImpliesValid_A	407018650	533446	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	214967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2574278	0	0
T1	515214	9806	0	0
T2	7514	78	0	0
T3	52009	1038	0	0
T7	54186	1152	0	0
T8	6233	62	0	0
T9	57884	937	0	0
T10	209009	110	0	0
T11	45935	1196	0	0
T12	5632	83	0	0
T13	352130	1583	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	533446	0	0
T1	515214	4046	0	0
T2	7514	9	0	0
T3	52009	225	0	0
T7	54186	254	0	0
T8	6233	61	0	0
T9	57884	134	0	0
T10	209009	36	0	0
T11	45935	222	0	0
T12	5632	9	0	0
T13	352130	1276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214967	0	0
T1	515214	1472	0	0
T2	7514	9	0	0
T3	52009	134	0	0
T7	54186	161	0	0
T8	6233	61	0	0
T9	57884	124	0	0
T10	209009	26	0	0
T11	45935	157	0	0
T12	5632	9	0	0
T13	352130	492	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	226859	0	0
GntImpliesValid_A	407018650	226859	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	226859	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2519947	0	0
ReadyAndValidImplyGrant_A	407018650	226859	0	0
ReqAndReadyImplyGrant_A	407018650	226859	0	0
ReqImpliesValid_A	407018650	585508	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	226859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2519947	0	0
T1	515214	13367	0	0
T2	7514	135	0	0
T3	52009	1053	0	0
T7	54186	1141	0	0
T8	6233	70	0	0
T9	57884	880	0	0
T10	209009	97	0	0
T11	45935	1254	0	0
T12	5632	149	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	585508	0	0
T1	515214	7568	0	0
T2	7514	32	0	0
T3	52009	182	0	0
T7	54186	261	0	0
T8	6233	81	0	0
T9	57884	125	0	0
T10	209009	22	0	0
T11	45935	228	0	0
T12	5632	27	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	226859	0	0
T1	515214	2170	0	0
T2	7514	17	0	0
T3	52009	136	0	0
T7	54186	157	0	0
T8	6233	75	0	0
T9	57884	112	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	219606	0	0
GntImpliesValid_A	407018650	219606	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	219606	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2577565	0	0
ReadyAndValidImplyGrant_A	407018650	219606	0	0
ReqAndReadyImplyGrant_A	407018650	219606	0	0
ReqImpliesValid_A	407018650	543456	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	219606	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2577565	0	0
T1	515214	10872	0	0
T2	7514	96	0	0
T3	52009	1336	0	0
T7	54186	1106	0	0
T8	6233	73	0	0
T9	57884	1012	0	0
T10	209009	97	0	0
T11	45935	1164	0	0
T12	5632	138	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	543456	0	0
T1	515214	3161	0	0
T2	7514	16	0	0
T3	52009	239	0	0
T7	54186	317	0	0
T8	6233	80	0	0
T9	57884	158	0	0
T10	209009	33	0	0
T11	45935	177	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219606	0	0
T1	515214	1558	0	0
T2	7514	15	0	0
T3	52009	162	0	0
T7	54186	154	0	0
T8	6233	76	0	0
T9	57884	132	0	0
T10	209009	26	0	0
T11	45935	156	0	0
T12	5632	17	0	0
T13	352130	0	0	0
T14	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	217880	0	0
GntImpliesValid_A	407018650	217880	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	217880	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2586262	0	0
ReadyAndValidImplyGrant_A	407018650	217880	0	0
ReqAndReadyImplyGrant_A	407018650	217880	0	0
ReqImpliesValid_A	407018650	519809	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	217880	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2586262	0	0
T1	515214	8231	0	0
T2	7514	135	0	0
T3	52009	1027	0	0
T7	54186	1286	0	0
T8	6233	74	0	0
T9	57884	689	0	0
T10	209009	106	0	0
T11	45935	1056	0	0
T12	5632	63	0	0
T13	352130	2910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	519809	0	0
T1	515214	1243	0	0
T2	7514	19	0	0
T3	52009	193	0	0
T7	54186	238	0	0
T8	6233	79	0	0
T9	57884	113	0	0
T10	209009	20	0	0
T11	45935	218	0	0
T12	5632	32	0	0
T13	352130	2278	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217880	0	0
T1	515214	1067	0	0
T2	7514	13	0	0
T3	52009	139	0	0
T7	54186	158	0	0
T8	6233	76	0	0
T9	57884	94	0	0
T10	209009	20	0	0
T11	45935	135	0	0
T12	5632	12	0	0
T13	352130	923	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	214495	0	0
GntImpliesValid_A	407018650	214495	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	214495	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2598371	0	0
ReadyAndValidImplyGrant_A	407018650	214495	0	0
ReqAndReadyImplyGrant_A	407018650	214495	0	0
ReqImpliesValid_A	407018650	546130	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	214495	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2598371	0	0
T1	515214	8442	0	0
T2	7514	56	0	0
T3	52009	981	0	0
T7	54186	1208	0	0
T8	6233	71	0	0
T9	57884	904	0	0
T10	209009	85	0	0
T11	45935	1161	0	0
T12	5632	114	0	0
T13	352130	1909	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	546130	0	0
T1	515214	1332	0	0
T2	7514	8	0	0
T3	52009	215	0	0
T7	54186	243	0	0
T8	6233	76	0	0
T9	57884	164	0	0
T10	209009	30	0	0
T11	45935	185	0	0
T12	5632	28	0	0
T13	352130	1256	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	214495	0	0
T1	515214	1080	0	0
T2	7514	8	0	0
T3	52009	128	0	0
T7	54186	170	0	0
T8	6233	73	0	0
T9	57884	121	0	0
T10	209009	25	0	0
T11	45935	151	0	0
T12	5632	16	0	0
T13	352130	564	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	239529	0	0
GntImpliesValid_A	407018650	239529	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	239529	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2700719	0	0
ReadyAndValidImplyGrant_A	407018650	239529	0	0
ReqAndReadyImplyGrant_A	407018650	239529	0	0
ReqImpliesValid_A	407018650	583268	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	239529	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2700719	0	0
T1	515214	9501	0	0
T2	7514	79	0	0
T3	52009	996	0	0
T7	54186	1163	0	0
T8	6233	136	0	0
T9	57884	1511	0	0
T10	209009	84	0	0
T11	45935	1212	0	0
T12	5632	151	0	0
T13	352130	4784	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	583268	0	0
T1	515214	1484	0	0
T2	7514	12	0	0
T3	52009	182	0	0
T7	54186	238	0	0
T8	6233	151	0	0
T9	57884	333	0	0
T10	209009	28	0	0
T11	45935	242	0	0
T12	5632	16	0	0
T13	352130	3532	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	239529	0	0
T1	515214	1251	0	0
T2	7514	12	0	0
T3	52009	128	0	0
T7	54186	164	0	0
T8	6233	143	0	0
T9	57884	202	0	0
T10	209009	22	0	0
T11	45935	165	0	0
T12	5632	16	0	0
T13	352130	1483	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	219997	0	0
GntImpliesValid_A	407018650	219997	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	219997	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2556463	0	0
ReadyAndValidImplyGrant_A	407018650	219997	0	0
ReqAndReadyImplyGrant_A	407018650	219997	0	0
ReqImpliesValid_A	407018650	530678	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	219997	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2556463	0	0
T1	515214	10899	0	0
T2	7514	27	0	0
T3	52009	1030	0	0
T7	54186	1174	0	0
T8	6233	68	0	0
T9	57884	945	0	0
T10	209009	82	0	0
T11	45935	1008	0	0
T12	5632	55	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	530678	0	0
T1	515214	2271	0	0
T2	7514	5	0	0
T3	52009	177	0	0
T7	54186	195	0	0
T8	6233	73	0	0
T9	57884	157	0	0
T10	209009	26	0	0
T11	45935	205	0	0
T12	5632	19	0	0
T13	352130	0	0	0
T14	0	319	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	219997	0	0
T1	515214	1437	0	0
T2	7514	5	0	0
T3	52009	142	0	0
T7	54186	166	0	0
T8	6233	70	0	0
T9	57884	120	0	0
T10	209009	23	0	0
T11	45935	148	0	0
T12	5632	10	0	0
T13	352130	0	0	0
T14	0	25	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	217121	0	0
GntImpliesValid_A	407018650	217121	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	217121	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2543196	0	0
ReadyAndValidImplyGrant_A	407018650	217121	0	0
ReqAndReadyImplyGrant_A	407018650	217121	0	0
ReqImpliesValid_A	407018650	513216	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	217121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2543196	0	0
T1	515214	7725	0	0
T2	7514	84	0	0
T3	52009	1034	0	0
T7	54186	1337	0	0
T8	6233	63	0	0
T9	57884	896	0	0
T10	209009	87	0	0
T11	45935	1146	0	0
T12	5632	108	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	513216	0	0
T1	515214	1179	0	0
T2	7514	11	0	0
T3	52009	264	0	0
T7	54186	270	0	0
T8	6233	74	0	0
T9	57884	167	0	0
T10	209009	26	0	0
T11	45935	251	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	217121	0	0
T1	515214	1000	0	0
T2	7514	11	0	0
T3	52009	164	0	0
T7	54186	172	0	0
T8	6233	68	0	0
T9	57884	126	0	0
T10	209009	24	0	0
T11	45935	158	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	224493	0	0
GntImpliesValid_A	407018650	224493	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	224493	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2613013	0	0
ReadyAndValidImplyGrant_A	407018650	224493	0	0
ReqAndReadyImplyGrant_A	407018650	224493	0	0
ReqImpliesValid_A	407018650	548979	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	224493	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2613013	0	0
T1	515214	7741	0	0
T2	7514	91	0	0
T3	52009	1270	0	0
T7	54186	1310	0	0
T8	6233	81	0	0
T9	57884	1006	0	0
T10	209009	132	0	0
T11	45935	995	0	0
T12	5632	98	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	548979	0	0
T1	515214	1143	0	0
T2	7514	26	0	0
T3	52009	245	0	0
T7	54186	212	0	0
T8	6233	86	0	0
T9	57884	138	0	0
T10	209009	33	0	0
T11	45935	195	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	526	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	224493	0	0
T1	515214	1030	0	0
T2	7514	14	0	0
T3	52009	162	0	0
T7	54186	175	0	0
T8	6233	83	0	0
T9	57884	126	0	0
T10	209009	27	0	0
T11	45935	145	0	0
T12	5632	12	0	0
T13	352130	0	0	0
T14	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	216564	0	0
GntImpliesValid_A	407018650	216564	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	216564	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2521833	0	0
ReadyAndValidImplyGrant_A	407018650	216564	0	0
ReqAndReadyImplyGrant_A	407018650	216564	0	0
ReqImpliesValid_A	407018650	514600	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	216564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2521833	0	0
T1	515214	7545	0	0
T2	7514	77	0	0
T3	52009	1124	0	0
T7	54186	1319	0	0
T8	6233	80	0	0
T9	57884	671	0	0
T10	209009	84	0	0
T11	45935	1113	0	0
T12	5632	108	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	514600	0	0
T1	515214	1169	0	0
T2	7514	21	0	0
T3	52009	248	0	0
T7	54186	230	0	0
T8	6233	89	0	0
T9	57884	118	0	0
T10	209009	21	0	0
T11	45935	168	0	0
T12	5632	16	0	0
T13	352130	0	0	0
T14	0	598	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	216564	0	0
T1	515214	1017	0	0
T2	7514	11	0	0
T3	52009	145	0	0
T7	54186	175	0	0
T8	6233	84	0	0
T9	57884	102	0	0
T10	209009	21	0	0
T11	45935	143	0	0
T12	5632	13	0	0
T13	352130	0	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	220806	0	0
GntImpliesValid_A	407018650	220806	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	220806	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	2596885	0	0
ReadyAndValidImplyGrant_A	407018650	220806	0	0
ReqAndReadyImplyGrant_A	407018650	220806	0	0
ReqImpliesValid_A	407018650	533042	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	0	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	220806	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2596885	0	0
T1	515214	8266	0	0
T2	7514	74	0	0
T3	52009	1062	0	0
T7	54186	1236	0	0
T8	6233	67	0	0
T9	57884	888	0	0
T10	209009	103	0	0
T11	45935	1206	0	0
T12	5632	45	0	0
T13	352130	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	533042	0	0
T1	515214	1243	0	0
T2	7514	10	0	0
T3	52009	191	0	0
T7	54186	318	0	0
T8	6233	70	0	0
T9	57884	148	0	0
T10	209009	40	0	0
T11	45935	216	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	1164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	220806	0	0
T1	515214	1094	0	0
T2	7514	10	0	0
T3	52009	139	0	0
T7	54186	178	0	0
T8	6233	68	0	0
T9	57884	113	0	0
T10	209009	28	0	0
T11	45935	162	0	0
T12	5632	7	0	0
T13	352130	0	0	0
T14	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	880393	0	0
GntImpliesValid_A	407018650	880393	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	880393	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	9562587	0	0
ReadyAndValidImplyGrant_A	407018650	880393	0	0
ReqAndReadyImplyGrant_A	407018650	880393	0	0
ReqImpliesValid_A	407018650	2081616	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	21432	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	880393	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	9562587	0	0
T1	515214	32044	0	0
T2	7514	227	0	0
T3	52009	4408	0	0
T7	54186	3900	0	0
T8	6233	1	0	0
T9	57884	2823	0	0
T10	209009	297	0	0
T11	45935	3913	0	0
T12	5632	202	0	0
T13	352130	2290	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	2081616	0	0
T1	515214	7006	0	0
T2	7514	34	0	0
T3	52009	1101	0	0
T7	54186	989	0	0
T8	6233	299	0	0
T9	57884	665	0	0
T10	209009	99	0	0
T11	45935	1164	0	0
T12	5632	34	0	0
T13	352130	887	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	21432	0	900
T1	515214	2	0	1
T2	7514	0	0	1
T3	52009	0	0	1
T7	54186	1	0	1
T8	6233	3	0	1
T9	57884	0	0	1
T10	209009	0	0	1
T11	45935	0	0	1
T12	5632	0	0	1
T13	352130	0	0	1
T15	0	11	0	0
T16	0	8	0	0
T17	0	4	0	0
T18	0	683	0	0
T19	0	34	0	0
T20	0	16	0	0
T21	0	22	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	880393	0	0
T1	515214	4809	0	0
T2	7514	32	0	0
T3	52009	662	0	0
T7	54186	662	0	0
T8	6233	299	0	0
T9	57884	442	0	0
T10	209009	83	0	0
T11	45935	611	0	0
T12	5632	33	0	0
T13	352130	691	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407018650	406889141	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407018650	884025	0	0
GntImpliesValid_A	407018650	884025	0	0
GrantKnown_A	407018650	406889141	0	0
IdxKnown_A	407018650	406889141	0	0
IndexIsCorrect_A	407018650	884025	0	0
LockArbDecision_A	407018650	0	0	0
NoReadyValidNoGrant_A	407018650	339959863	0	0
ReadyAndValidImplyGrant_A	407018650	884025	0	0
ReqAndReadyImplyGrant_A	407018650	884025	0	0
ReqImpliesValid_A	407018650	11400027	0	0
ReqStaysHighUntilGranted0_M	407018650	0	0	0
RoundRobin_A	407018650	32825	0	900
ValidKnown_A	407018650	406889141	0	0
gen_data_port_assertion.DataFlow_A	407018650	884025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	339959863	0	0
T1	515214	410724	0	0
T2	7514	6497	0	0
T3	52009	41103	0	0
T7	54186	44717	0	0
T8	6233	1	0	0
T9	57884	49800	0	0
T10	209009	173725	0	0
T11	45935	36620	0	0
T12	5632	4920	0	0
T13	352130	292945	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	11400027	0	0
T1	515214	44609	0	0
T2	7514	385	0	0
T3	52009	5009	0	0
T7	54186	5182	0	0
T8	6233	275	0	0
T9	57884	3377	0	0
T10	209009	389	0	0
T11	45935	4104	0	0
T12	5632	235	0	0
T13	352130	6252	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	32825	0	900
T1	515214	59	0	1
T2	7514	0	0	1
T3	52009	1	0	1
T7	54186	1	0	1
T8	6233	4	0	1
T9	57884	0	0	1
T10	209009	0	0	1
T11	45935	2	0	1
T12	5632	0	0	1
T13	352130	12	0	1
T15	0	10	0	0
T16	0	9	0	0
T17	0	3	0	0
T18	0	809	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	406889141	0	0
T1	515214	515172	0	0
T2	7514	7498	0	0
T3	52009	52002	0	0
T7	54186	54173	0	0
T8	6233	6221	0	0
T9	57884	57879	0	0
T10	209009	208922	0	0
T11	45935	45883	0	0
T12	5632	5620	0	0
T13	352130	352129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407018650	884025	0	0
T1	515214	6262	0	0
T2	7514	41	0	0
T3	52009	642	0	0
T7	54186	674	0	0
T8	6233	275	0	0
T9	57884	447	0	0
T10	209009	92	0	0
T11	45935	579	0	0
T12	5632	38	0	0
T13	352130	1368	0	0